summaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-shmobile/intc-sh73a0.c
AgeCommit message (Collapse)Author
2011-06-14ARM: mach-shmobile: sh73a0 gic_arch_extn.irq_set_wake() fixMagnus Damm
Initialize ->irq_set_wake() in gic_arch_extn to unbreak wake up from the KEYSC device on AG5EVM in case of Suspend-to-RAM. Without this patch "echo mem > /sys/power/state" and a key press results in the following message on resume: WARNING: at kernel/irq/manage.c:507 irq_set_irq_wake+0x7c/0xd8() Unbalanced IRQ 103 wake disable Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2011-01-14ARM: mach-shmobile: fix cpu_base of gic_init() on sh73a0Yoshii Takashi
The latest rmobile-latest doesn't run on ag5evm because of a small mistake on initialization. Though, I don't have any idea to write them smart. anyway, On sh73a0, GIC cpu_base is 0xf0000100 but 0xf0001000. Signed-off-by: Takashi YOSHII <takashi.yoshii.zj@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2011-01-07ARM: mach-shmobile: update for GIC changes.Paul Mundt
This fixes up the SMP support to use the refactored GIC APIs. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-12-22ARM: mach-shmobile: sh73a0 INTCS supportMagnus Damm
Add INTCS support for the sh73a0 processor. The interrupts on the sh73a0 processor are managed through controllers such as GIC, INTCS and INTCA. The ARM cores use the GIC as primary interrupt controller and the INTCS and INTCA are hanging off the GIC as cascaded interrupt controllers. Peripherals connected both to the GIC and the INTC controllers should if possible only use the GIC. If no GIC connection is available then INTCS and INTCA may be used instead. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>