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2013-12-11ARM: tegra: pass reset to tegra_powergate_sequence_power_up()Stephen Warren
Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Acked-By: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com>
2013-12-11ARM: tegra: select the reset frameworkStephen Warren
The Tegra clock driver is built unconditionally when Tegra support is enabled. In order to avoid having to ifdef the forthcoming reset driver implementation, have ARCH_TEGRA select RESET_CONTROLLER. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2013-11-23Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6Linus Torvalds
Pull crypto update from Herbert Xu: - Made x86 ablk_helper generic for ARM - Phase out chainiv in favour of eseqiv (affects IPsec) - Fixed aes-cbc IV corruption on s390 - Added constant-time crypto_memneq which replaces memcmp - Fixed aes-ctr in omap-aes - Added OMAP3 ROM RNG support - Add PRNG support for MSM SoC's - Add and use Job Ring API in caam - Misc fixes [ NOTE! This pull request was sent within the merge window, but Herbert has some questionable email sending setup that makes him public enemy #1 as far as gmail is concerned. So most of his emails seem to be trapped by gmail as spam, resulting in me not seeing them. - Linus ] * git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (49 commits) crypto: s390 - Fix aes-cbc IV corruption crypto: omap-aes - Fix CTR mode counter length crypto: omap-sham - Add missing modalias padata: make the sequence counter an atomic_t crypto: caam - Modify the interface layers to use JR API's crypto: caam - Add API's to allocate/free Job Rings crypto: caam - Add Platform driver for Job Ring hwrng: msm - Add PRNG support for MSM SoC's ARM: DT: msm: Add Qualcomm's PRNG driver binding document crypto: skcipher - Use eseqiv even on UP machines crypto: talitos - Simplify key parsing crypto: picoxcell - Simplify and harden key parsing crypto: ixp4xx - Simplify and harden key parsing crypto: authencesn - Simplify key parsing crypto: authenc - Export key parsing helper function crypto: mv_cesa: remove deprecated IRQF_DISABLED hwrng: OMAP3 ROM Random Number Generator support crypto: sha256_ssse3 - also test for BMI2 crypto: mv_cesa - Remove redundant of_match_ptr crypto: sahara - Remove redundant of_match_ptr ...
2013-11-16Merge tag 'fixes-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC fixes from Olof Johansson: "A first set of batches of fixes for 3.13. The diffstat is large mostly because we're adding a defconfig for a family that's been lacking it, and there's some missing clock information added for i.MX and OMAP. The at91 new code is around dealing with RTC/RTT reset at boot to fix possible hangs due to pending wakeup interrupts coming in during early boot" * tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (29 commits) ARM: OMAP2+: Fix build for dra7xx without omap4 and 5 ARM: OMAP2+: omap_device: maintain sane runtime pm status around suspend/resume doc: devicetree: Add bindings documentation for omap-des driver ARM: dts: doc: Document missing compatible property for omap-sham driver ARM: OMAP3: Beagle: fix return value check in beagle_opp_init() ARM: at91: fix hanged boot due to early rtt-interrupt ARM: at91: fix hanged boot due to early rtc-interrupt video: exynos_mipi_dsim: Remove unused variable ARM: highbank: only select errata 764369 if SMP ARM: sti: only select errata 764369 if SMP ARM: tegra: init fuse before setting reset handler ARM: vt8500: add defconfig for v6/v7 chips ARM: integrator_cp: Set LCD{0,1} enable lines when turning on CLCD ARM: OMAP: devicetree: fix SPI node compatible property syntax items pinctrl: single: call pcs_soc->rearm() whenever IRQ mask is changed ARM: OMAP2+: smsc911x: fix return value check in gpmc_smsc911x_init() MAINTAINERS: drop discontinued mailing list ARM: dts: i.MX51: Fix OTG PHY clock ARM: imx: set up pllv3 POWER and BYPASS sequentially ARM: imx: pllv3 needs relock in .set_rate() call ...
2013-11-15tree-wide: use reinit_completion instead of INIT_COMPLETIONWolfram Sang
Use this new function to make code more comprehensible, since we are reinitialzing the completion, not initializing. [akpm@linux-foundation.org: linux-next resyncs] Signed-off-by: Wolfram Sang <wsa@the-dreams.de> Acked-by: Linus Walleij <linus.walleij@linaro.org> (personally at LCE13) Cc: Ingo Molnar <mingo@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2013-11-14ARM: tegra: init fuse before setting reset handlerAlexandre Courbot
CPU reset handler was set before fuse is initialized, but tegra_cpu_reset_handler_enable() uses tegra_chip_id, which is set by tegra_init_fuse(). This patch reorders the calls so the CPU reset handler code does not read an uninitialized variable. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2013-11-14Merge branch 'for-linus' of git://git.linaro.org/people/rmk/linux-armLinus Torvalds
Pull ARM updates from Russell King: "Included in this series are: 1. BE8 (modern big endian) changes for ARM from Ben Dooks 2. big.Little support from Nicolas Pitre and Dave Martin 3. support for LPAE systems with all system memory above 4GB 4. Perf updates from Will Deacon 5. Additional prefetching and other performance improvements from Will. 6. Neon-optimised AES implementation fro Ard. 7. A number of smaller fixes scattered around the place. There is a rather horrid merge conflict in tools/perf - I was never notified of the conflict because it originally occurred between Will's tree and other stuff. Consequently I have a resolution which Will forwarded me, which I'll forward on immediately after sending this mail. The other notable thing is I'm expecting some build breakage in the crypto stuff on ARM only with Ard's AES patches. These were merged into a stable git branch which others had already pulled, so there's little I can do about this. The problem is caused because these patches have a dependency on some code in the crypto git tree - I tried requesting a branch I can pull to resolve these, and all I got each time from the crypto people was "we'll revert our patches then" which would only make things worse since I still don't have the dependent patches. I've no idea what's going on there or how to resolve that, and since I can't split these patches from the rest of this pull request, I'm rather stuck with pushing this as-is or reverting Ard's patches. Since it should "come out in the wash" I've left them in - the only build problems they seem to cause at the moment are with randconfigs, and since it's a new feature anyway. However, if by -rc1 the dependencies aren't in, I think it'd be best to revert Ard's patches" I resolved the perf conflict roughly as per the patch sent by Russell, but there may be some differences. Any errors are likely mine. Let's see how the crypto issues work out.. * 'for-linus' of git://git.linaro.org/people/rmk/linux-arm: (110 commits) ARM: 7868/1: arm/arm64: remove atomic_clear_mask() in "include/asm/atomic.h" ARM: 7867/1: include: asm: use 'int' instead of 'unsigned long' for 'oldval' in atomic_cmpxchg(). ARM: 7866/1: include: asm: use 'long long' instead of 'u64' within atomic.h ARM: 7871/1: amba: Extend number of IRQS ARM: 7887/1: Don't smp_cross_call() on UP devices in arch_irq_work_raise() ARM: 7872/1: Support arch_irq_work_raise() via self IPIs ARM: 7880/1: Clear the IT state independent of the Thumb-2 mode ARM: 7878/1: nommu: Implement dummy early_paging_init() ARM: 7876/1: clear Thumb-2 IT state on exception handling ARM: 7874/2: bL_switcher: Remove cpu_hotplug_driver_{lock,unlock}() ARM: footbridge: fix build warnings for netwinder ARM: 7873/1: vfp: clear vfp_current_hw_state for dying cpu ARM: fix misplaced arch_virt_to_idmap() ARM: 7848/1: mcpm: Implement cpu_kill() to synchronise on powerdown ARM: 7847/1: mcpm: Factor out logical-to-physical CPU translation ARM: 7869/1: remove unused XSCALE_PMU Kconfig param ARM: 7864/1: Handle 64-bit memory in case of 32-bit phys_addr_t ARM: 7863/1: Let arm_add_memory() always use 64-bit arguments ARM: 7862/1: pcpu: replace __get_cpu_var_uses ARM: 7861/1: cacheflush: consolidate single-CPU ARMv7 cache disabling code ...
2013-11-11Merge tag 'soc-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform changes from Olof Johansson: "New and updated SoC support. Among the things new for this release are: - More support for the AM33xx platforms from TI - Tegra 124 support, and some updates to older tegra families as well - imx cleanups and updates across the board - A rename of Broadcom's Mobile platforms which were introduced as ARCH_BCM, and turned out to be too broad a name. New name is ARCH_BCM_MOBILE. - A whole bunch of updates and fixes for integrator, making the platform code more modern and switches over to DT-only booting. - Support for two new Renesas shmobile chipsets. Next up for them is more work on consolidation instead of introduction of new non-multiplatform SoCs, we're all looking forward to that! - Misc cleanups for older Samsung platforms, some Allwinner updates, etc" * tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (159 commits) ARM: bcm281xx: Add ARCH_BCM_MOBILE to bcm config ARM: bcm_defconfig: Run "make savedefconfig" ARM: bcm281xx: Add ARCH Timers to config rename ARCH_BCM to ARCH_BCM_MOBILE (mach-bcm) ARM: vexpress: Enable platform-specific options in defconfig ARM: vexpress: Make defconfig work again ARM: sunxi: remove .init_time hooks ARM: imx: enable suspend for imx6sl ARM: imx: ensure dsm_request signal is not asserted when setting LPM ARM: imx6q: call WB and RBC configuration from imx6q_pm_enter() ARM: imx6q: move low-power code out of clock driver ARM: imx: drop extern with function prototypes in common.h ARM: imx: reset core along with enable/disable operation ARM: imx: do not return from imx_cpu_die() call ARM: imx_v6_v7_defconfig: Select CONFIG_PROVE_LOCKING ARM: imx_v6_v7_defconfig: Enable LEDS_GPIO related options ARM: mxs_defconfig: Turn off CONFIG_DEBUG_GPIO ARM: imx: replace imx6q_restart() with mxc_restart() ARM: mach-imx: mm-imx5: Retrieve iomuxc base address from dt ARM: mach-imx: mm-imx5: Retrieve tzic base address from dt ...
2013-10-28Merge branch 'cleanup/dt-clock' into next/socOlof Johansson
Merging in dt clock cleanup as a pre-req with some of the later SoC branches. There are a handful of conflicts here -- some of the already merged SoC branches should have been based on the cleanup but weren't. In particular, a remove/add of include on highbank and two remove/remove conflicts on kirkwood were fixed up. * cleanup/dt-clock: (28 commits) ARM: vt8500: remove custom .init_time hook ARM: vexpress: remove custom .init_time hook ARM: tegra: remove custom .init_time hook ARM: sunxi: remove custom .init_time hook ARM: sti: remove custom .init_time hook ARM: socfpga: remove custom .init_time hook ARM: rockchip: remove custom .init_time hook ARM: prima2: remove custom .init_time hook ARM: nspire: remove custom .init_time hook ARM: nomadik: remove custom .init_time hook ARM: mxs: remove custom .init_time hook ARM: kirkwood: remove custom .init_time hook ARM: imx: remove custom .init_time hook ARM: highbank: remove custom .init_time hook ARM: exynos: remove custom .init_time hook ARM: dove: remove custom .init_time hook ARM: bcm2835: remove custom .init_time hook ARM: bcm: provide common arch init for DT clocks ARM: call of_clk_init from default time_init handler ARM: vt8500: prepare for arch-wide .init_time callback ... Signed-off-by: Olof Johansson <olof@lixom.net>
2013-10-21ARM: fix build errors caused by selection of errata 798181Russell King
Several configurations are selecting errata 798181 without SMP being selected. This causes a warning from Kconfig: warning: (ARCH_HIGHBANK && ARCH_KEYSTONE && SOC_OMAP5 && ARCH_TEGRA_114_SOC) selects ARM_ERRATA_798181 which has unmet direct dependencies (CPU_V7 && SMP) The dependencies are compile time dependencies; select violates these, resulting in: arch/arm/kernel/built-in.o: In function `setup_processor': psci.c:(.init.text+0x808): undefined reference to `erratum_a15_798181_init' at build time. Fix this by fixing the select statements for Tegra and Highbank. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-10-18ARM: tegra: Add Tegra114 powergate supportThierry Reding
Extend the list of power gates found on Tegra114. Note that there are now holes in the list, so perhaps a simple array is no longer the best data structure to represent it. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-18ARM: tegra: Constify list of CPU domainsThierry Reding
There's no need to modify these at runtime, it is static data and never needs to change. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-18ARM: tegra: Remove duplicate powergate definesThierry Reding
Instead of duplicating powergate defines, reuse the ones from the include/linux/tegra-powergate.h header file. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-18ARM: tegra: add LP1 support code for Tegra124Joseph Lo
The LP1 suspend procedure is the same with Tegra30 and Tegra114. Just need to update the difference of the register address, then we can continue to share the code. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-18ARM: tegra: re-calculate the LP1 data for Tegra30/114Joseph Lo
This patch re-calculates the LP1 data of tegra30/114_sdram_pad_address to base on its label not rely on others. This can make easier to maintain if some other Tegra chips keep re-using these codes in the future. And change the name of tegra30_sdram_pad_save to tegra_sdram_pad_save to make it more common to other chips. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-18ARM: tegra: enable CPU idle for Tegra124Joseph Lo
The CPUIdle function of Tegra124 is identical to Tegra114, so we share the same driver with Tegra114. Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-18ARM: tegra: make tegra_resume can work with current and later chipsJoseph Lo
Because the CPU0 was the first up and the last down core when cluster power up/down or platform suspend. So only CPU0 needs the rest of the functions to reset flow controller and re-enable SCU and L2. We also move the L2 init function for Cortex-A15 to there. The secondery CPU can just call cpu_resume. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-18ARM: tegra: CPU hotplug support for Tegra124Joseph Lo
The procedure of CPU hotplug for Tegra124 is same with Tegra114. We re-use the same function with it. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-18ARM: tegra: add PMC compatible value for Tegra124Joseph Lo
The PMC HW is not identical to the existing Tegra SoC. Hence add to it. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-18ARM: tegra: add Tegra124 SoC supportJoseph Lo
Add Tegra124 SoC support that base on CortexA15MP Core. And enable the SMP function that can re-use the same procedure with Tegra114. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-18ARM: tegra: add fuses as device randomnessStephen Warren
Various fuses on Tegra include information that's unique to an individual chip, or a subset of chips. Call add_device_randomness() with this data to perturb the initial state of the random pool. Suggested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2013-10-17Merge tag 'tegra-for-3.13-cleanup' of ↵Kevin Hilman
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/cleanup ARM: tegra: cleanup for 3.13 This branch mainly removes dead code and defines that were useful only when booting using board files. A few other misc cleanups are also included. This branch is based on previous pull request tegra-for-3.13-deps-for-arm-init-time-cleanup. * tag 'tegra-for-3.13-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: ARM: tegra: fix ARCH_TEGRA_114_SOC select sort order ARM: tegra: make tegra_init_fuse() __init ARM: tegra: remove much of iomap.h ARM: tegra: move resume vector define to irammap.h ARM: tegra: delete gpio-names.h ARM: tegra: delete stale header content ARM: tegra: remove common.c Signed-off-by: Kevin Hilman <khilman@linaro.org>
2013-10-07ARM: tegra: fix ARCH_TEGRA_114_SOC select sort orderStephen Warren
All the other select statements are alphabetically sorted. Fix the one remaining escape. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-07ARM: drop explicit selection of HAVE_CLK and CLKDEV_LOOKUPUwe Kleine-König
CLKDEV_LOOKUP selects HAVE_CLK and COMMON_CLK selects CLKDEV_LOOKUP. So all symbols that select at least two of these symbols can be simplified. For imx, omap2 and ux500 some rearrangements were necessary before the simplification. Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Dinh Nguyen <dinguyen@altera.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Pawel Moll <pawel.moll@arm.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Olof Johansson <olof@lixom.net>
2013-09-29ARM: tegra: remove custom .init_time hookSebastian Hesselbarth
With arch/arm calling of_clk_init(NULL) from time_init(), we can now remove custom .init_time hooks. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2013-09-24ARM: tegra: remove tegra_chip_uid()Stephen Warren
Following commit f5b38c5 "crypto: tegra - use kernel entropy instead of ad-hoc", this function is no longer used. It's also only accurate for Tegra20 and not later SoCs. So, remove it. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2013-09-17ARM: tegra: make tegra_init_fuse() __initStephen Warren
It's a one-time initialization function, called early during boot. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-09-17ARM: tegra: remove much of iomap.hStephen Warren
iomap.h defines the base address of Tegra peripherals. Most of this information comes from device tree now, and hence can be deleted. Entries are kept for various system peripherals that low-level code (such as initial boot, system suspend/resume, debug) still requires. Removing the values removes the temptation for someone to use them. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-09-17ARM: tegra: move resume vector define to irammap.hStephen Warren
irammap.h's purpose is to define the layout/usage of IRAM. As such, TEGRA_IRAM_CODE_AREA should have been added there rather than iomap.h. Move the define, and rename it something more descriptive. Cc: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-09-17ARM: tegra: delete gpio-names.hStephen Warren
gpio-names.h defines IDs for GPIOs. This information now comes from device tree, so delete this stale header. The one remaining use-case is board-paz00.c's wifi_rfkill device. Isolate the knowledge of those GPIO IDs into that file. Let's hope the values stay valid:-) Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-09-17ARM: tegra: delete stale header contentStephen Warren
A few function prototypes were left in header files during code re- organization. Delete them. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-09-17ARM: tegra: remove common.cStephen Warren
common.c was create to contain code shared across the various Tegra board files. There is now only one board file, tegra.c. So, move the code there. One exception is the PMC reboot routine, which moves to pmc.c, and now takes advantage of the 'standard' tegra_pmc_readl/writel functions. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-09-17ARM: tegra: split tegra_pmc_init() in twoStephen Warren
Tegra's board file currently initializes clocks much earlier than those for most other ARM SoCs. The reason is: * The PMC HW block is involved in the path of some interrupts (i.e. it inverts, or not, the IRQ input pin dedicated to the PMIC). * So, that part of the PMC must be initialized early so that the IRQ polarity is correct. * The PMC initialization is currently monolithic, and the PMC has some clock inputs, so the init routine ends up calling of_clk_get_by_name(), and hence clocks must be set up early too. In order to defer clock initialization to the more typical location, split out the portions of tegra_pmc_init() that are truly IRQ-related into a separate tegra_pmc_init_irq(), which can be called from the machine descriptor's .init_irq() function, and defer the rest until the machine descriptor's .init_machine() function. This allows the clock initiliazation to happen from the machine descriptor's .init_time() function, as is typical. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-09-06Merge tag 'soc-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform changes from Olof Johansson: "This branch contains mostly additions and changes to platform enablement and SoC-level drivers. Since there's sometimes a dependency on device-tree changes, there's also a fair amount of those in this branch. Pieces worth mentioning are: - Mbus driver for Marvell platforms, allowing kernel configuration and resource allocation of on-chip peripherals. - Enablement of the mbus infrastructure from Marvell PCI-e drivers. - Preparation of MSI support for Marvell platforms. - Addition of new PCI-e host controller driver for Tegra platforms - Some churn caused by sharing of macro names between i.MX 6Q and 6DL platforms in the device tree sources and header files. - Various suspend/PM updates for Tegra, including LP1 support. - Versatile Express support for MCPM, part of big little support. - Allwinner platform support for A20 and A31 SoCs (dual and quad Cortex-A7) - OMAP2+ support for DRA7, a new Cortex-A15-based SoC. The code that touches other architectures are patches moving MSI arch-specific functions over to weak symbols and removal of ARCH_SUPPORTS_MSI, acked by PCI maintainers" * tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (266 commits) tegra-cpuidle: provide stub when !CONFIG_CPU_IDLE PCI: tegra: replace devm_request_and_ioremap by devm_ioremap_resource ARM: tegra: Drop ARCH_SUPPORTS_MSI and sort list ARM: dts: vf610-twr: enable i2c0 device ARM: dts: i.MX51: Add one more I2C2 pinmux entry ARM: dts: i.MX51: Move pins configuration under "iomuxc" label ARM: dtsi: imx6qdl-sabresd: Add USB OTG vbus pin to pinctrl_hog ARM: dtsi: imx6qdl-sabresd: Add USB host 1 VBUS regulator ARM: dts: imx27-phytec-phycore-som: Enable AUDMUX ARM: dts: i.MX27: Disable AUDMUX in the template ARM: dts: wandboard: Add support for SDIO bcm4329 ARM: i.MX5 clocks: Remove optional clock setup (CKIH1) from i.MX51 template ARM: dts: imx53-qsb: Make USBH1 functional ARM i.MX6Q: dts: Enable I2C1 with EEPROM and PMIC on Phytec phyFLEX-i.MX6 Ouad module ARM i.MX6Q: dts: Enable SPI NOR flash on Phytec phyFLEX-i.MX6 Ouad module ARM: dts: imx6qdl-sabresd: Add touchscreen support ARM: imx: add ocram clock for imx53 ARM: dts: imx: ocram size is different between imx6q and imx6dl ARM: dts: imx27-phytec-phycore-som: Fix regulator settings ARM: dts: i.MX27: Remove clock name from CPU node ...
2013-09-06Merge tag 'cleanup-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC cleanups from Olof Johansson: "This branch contains code cleanups, moves and removals for 3.12. There's a large number of various cleanups, and a nice net removal of 13500 lines of code. Highlights worth mentioning are: - A series of patches from Stephen Boyd removing the ARM local timer API. - Move of Qualcomm MSM IOMMU code to drivers/iommu. - Samsung PWM driver cleanups from Tomasz Figa, removing legacy PWM driver and switching over to the drivers/pwm one. - Removal of some unusued auto-generated headers for OMAP2+ (PRM/CM). There's also a move of a header file out of include/linux/i2c/ to platform_data, where it really belongs. It touches mostly ARM platform code for include changes so we took it through our tree" * tag 'cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (83 commits) ARM: OMAP2+: Add back the define for AM33XX_RST_GLOBAL_WARM_SW_MASK gpio: (gpio-pca953x) move header to linux/platform_data/ arm: zynq: hotplug: Remove unreachable code ARM: SAMSUNG: Remove unnecessary exynos4_default_sdhci*() tegra: simplify use of devm_ioremap_resource ARM: SAMSUNG: Remove plat/regs-timer.h header ARM: SAMSUNG: Remove remaining uses of plat/regs-timer.h header ARM: SAMSUNG: Remove pwm-clock infrastructure ARM: SAMSUNG: Remove old PWM timer platform devices pwm: Remove superseded pwm-samsung-legacy driver ARM: SAMSUNG: Modify board files to use new PWM platform device ARM: SAMSUNG: Rework private data handling in dev-backlight pwm: Add new pwm-samsung driver ARM: mach-mvebu: remove redundant DT parsing and validation ARM: msm: Only compile io.c on platforms that use it iommu/msm: Move mach includes to iommu directory ARM: msm: Remove devices-iommu.c ARM: msm: Move mach/board.h contents to common.h ARM: msm: Migrate msm_timer to CLOCKSOURCE_OF_DECLARE ARM: msm: Remove TMR and TMR0 static mappings ...
2013-08-29ARM: tegra: Drop ARCH_SUPPORTS_MSI and sort listThierry Reding
The ARCH_SUPPORTS_MSI symbol was removed during the recent patches that introduce the MSI chip infrastructure. Drop it from the list of selected symbols. While at it, move the MIGHT_HAVE_PCI symbol so the list stays sorted alphabetically. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2013-08-21Merge tag 'tegra-for-3.12-soc' of ↵Kevin Hilman
git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc From: Stephen Warren: ARM: tegra: core SoC enhancements for 3.12 This branch includes a number of enhancements to core SoC support for Tegra devices. The major new features are: * Adds a new CPU-power-gated cpuidle state for Tegra114. * Adds initial system suspend support for Tegra114, initially supporting just CPU-power-gating during suspend. * Adds "LP1" suspend mode support for all of Tegra20/30/114. This mode both gates CPU power, and places the DRAM into self-refresh mode. * A new DT-driven PCIe driver to Tegra20/30. The driver is also moved from arch/arm/mach-tegra/ to drivers/pci/host/. The PCIe driver work depends on the following tag from Thomas Petazzoni: git://git.infradead.org/linux-mvebu.git mis-3.12.2 ... which is merged into the middle of this pull request. * tag 'tegra-for-3.12-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (33 commits) ARM: tegra: disable LP2 cpuidle state if PCIe is enabled MAINTAINERS: Add myself as Tegra PCIe maintainer PCI: tegra: set up PADS_REFCLK_CFG1 PCI: tegra: Add Tegra 30 PCIe support PCI: tegra: Move PCIe driver to drivers/pci/host PCI: msi: add default MSI operations for !HAVE_GENERIC_HARDIRQS platforms ARM: tegra: add LP1 suspend support for Tegra114 ARM: tegra: add LP1 suspend support for Tegra20 ARM: tegra: add LP1 suspend support for Tegra30 ARM: tegra: add common LP1 suspend support clk: tegra114: add LP1 suspend/resume support ARM: tegra: config the polarity of the request of sys clock ARM: tegra: add common resume handling code for LP1 resuming ARM: pci: add ->add_bus() and ->remove_bus() hooks to hw_pci of: pci: add registry of MSI chips PCI: Introduce new MSI chip infrastructure PCI: remove ARCH_SUPPORTS_MSI kconfig option PCI: use weak functions for MSI arch-specific functions ARM: tegra: unify Tegra's Kconfig a bit more ARM: tegra: remove the limitation that Tegra114 can't support suspend ... Signed-off-by: Kevin Hilman <khilman@linaro.org>
2013-08-13ARM: tegra: disable LP2 cpuidle state if PCIe is enabledStephen Warren
Tegra20 HW appears to have a bug such that PCIe device interrupts, whether they are legacy IRQs or MSI, are lost when LP2 is enabled. To work around this, simply disable LP2 if any PCIe devices with interrupts are present. Detect this via the IRQ domain map operation. This is slightly over-conservative; if a device with an interrupt is present but the driver does not actually use them, LP2 will still be disabled. However, this is a reasonable trade-off which enables a simpler workaround. Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com>
2013-08-13PCI: tegra: Move PCIe driver to drivers/pci/hostThierry Reding
Move the PCIe driver from arch/arm/mach-tegra into the drivers/pci/host directory. The motivation is to collect various host controller drivers in the same location in order to facilitate refactoring. The Tegra PCIe driver has been largely rewritten, both in order to turn it into a proper platform driver and to add MSI (based on code by Krishna Kishore <kthota@nvidia.com>) as well as device tree support. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> [swarren, split DT changes into a separate patch in another branch] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-08-12ARM: tegra: add LP1 suspend support for Tegra114Joseph Lo
The LP1 suspend mode will power off the CPU, clock gated the PLLs and put SDRAM to self-refresh mode. Any interrupt can wake up device from LP1. The sequence when LP1 suspending: * tunning off L1 data cache and the MMU * storing some EMC registers, DPD (deep power down) status, clk source of mselect and SCLK burst policy * putting SDRAM into self-refresh * switching CPU to CLK_M (12MHz OSC) * tunning off PLLM, PLLP, PLLA, PLLC and PLLX * switching SCLK to CLK_S (32KHz OSC) * shutting off the CPU rail The sequence of LP1 resuming: * re-enabling PLLM, PLLP, PLLA, PLLC and PLLX * restoring the clk source of mselect and SCLK burst policy * setting up CCLK burst policy to PLLX * restoring DPD status and some EMC registers * resuming SDRAM to normal mode * jumping to the "tegra_resume" from PMC_SCRATCH41 Due to the SDRAM will be put into self-refresh mode, the low level procedures of LP1 suspending and resuming should be copied to TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K) when suspending. Before restoring the CPU context when resuming, the SDRAM needs to be switched back to normal mode. And the PLLs need to be re-enabled, SCLK burst policy be restored. Then jumping to "tegra_resume" that was expected to be stored in PMC_SCRATCH41 to restore CPU context and back to kernel. Based on the work by: Bo Yan <byan@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-08-12ARM: tegra: add LP1 suspend support for Tegra20Joseph Lo
The LP1 suspend mode will power off the CPU, clock gated the PLLs and put SDRAM to self-refresh mode. Any interrupt can wake up device from LP1. The sequence when LP1 suspending: * tunning off L1 data cache and the MMU * putting SDRAM into self-refresh * storing some EMC registers and SCLK burst policy * switching CPU to CLK_M (12MHz OSC) * switching SCLK to CLK_S (32KHz OSC) * tunning off PLLM, PLLP and PLLC * shutting off the CPU rail The sequence of LP1 resuming: * re-enabling PLLM, PLLP, and PLLC * restoring some EMC registers and SCLK burst policy * setting up CCLK burst policy to PLLP * resuming SDRAM to normal mode * jumping to the "tegra_resume" from PMC_SCRATCH41 Due to the SDRAM will be put into self-refresh mode, the low level procedures of LP1 suspending and resuming should be copied to TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K) when suspending. Before restoring the CPU context when resuming, the SDRAM needs to be switched back to normal mode. And the PLLs need to be re-enabled, SCLK burst policy be restored, CCLK burst policy be set in PLLP. Then jumping to "tegra_resume" that was expected to be stored in PMC_SCRATCH41 to restore CPU context and back to kernel. Based on the work by: Colin Cross <ccross@android.com> Gary King <gking@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-08-12ARM: tegra: add LP1 suspend support for Tegra30Joseph Lo
The LP1 suspend mode will power off the CPU, clock gated the PLLs and put SDRAM to self-refresh mode. Any interrupt can wake up device from LP1. The sequence when LP1 suspending: * tunning off L1 data cache and the MMU * storing some EMC registers, DPD (deep power down) status, clk source of mselect and SCLK burst policy * putting SDRAM into self-refresh * switching CPU to CLK_M (12MHz OSC) * tunning off PLLM, PLLP, PLLA, PLLC and PLLX * switching SCLK to CLK_S (32KHz OSC) * shutting off the CPU rail The sequence of LP1 resuming: * re-enabling PLLM, PLLP, PLLA, PLLC and PLLX * restoring the clk source of mselect and SCLK burst policy * setting up CCLK burst policy to PLLX * restoring DPD status and some EMC registers * resuming SDRAM to normal mode * jumping to the "tegra_resume" from PMC_SCRATCH41 Due to the SDRAM will be put into self-refresh mode, the low level procedures of LP1 suspending and resuming should be copied to TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K) when suspending. Before restoring the CPU context when resuming, the SDRAM needs to be switched back to normal mode. And the PLLs need to be re-enabled, SCLK burst policy be restored, CCLK burst policy be set in PLLX. Then jumping to "tegra_resume" that was expected to be stored in PMC_SCRATCH41 to restore CPU context and back to kernel. Based on the work by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-08-12ARM: tegra: add common LP1 suspend supportJoseph Lo
The LP1 suspending mode on Tegra means CPU rail off, devices and PLLs are clock gated and SDRAM in self-refresh mode. That means the low level LP1 suspending and resuming code couldn't be run on DRAM and the CPU must switch to the always on clock domain (a.k.a. CLK_M 12MHz oscillator). And the system clock (SCLK) would be switched to CLK_S, a 32KHz oscillator. The LP1 low level handling code need to be moved to IRAM area first. And marking the LP1 mask for indicating the Tegra device is in LP1. The CPU power timer needs to be re-calculated based on 32KHz that was originally based on PCLK. When resuming from LP1, the LP1 reset handler will resume PLLs and then put DRAM to normal mode. Then jumping to the "tegra_resume" that will restore full context before back to kernel. The "tegra_resume" handler was expected to be found in PMC_SCRATCH41 register. This is common LP1 procedures for Tegra, so we do these jobs mainly in this patch: * moving LP1 low level handling code to IRAM * marking LP1 mask * copying the physical address of "tegra_resume" to PMC_SCRATCH41 * re-calculate the CPU power timer based on 32KHz Signed-off-by: Joseph Lo <josephl@nvidia.com> [swarren, replaced IRAM_CODE macro with IO_ADDRESS(TEGRA_IRAM_CODE_AREA)] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-08-12ARM: tegra: config the polarity of the request of sys clockJoseph Lo
When suspending to LP1 mode, the SYSCLK will be clock gated. And different board may have different polarity of the request of SYSCLK, this patch configure the polarity from the DT for the board. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-08-12ARM: tegra: add common resume handling code for LP1 resumingJoseph Lo
Add support to the Tegra CPU reset vector to detect whether the CPU is resuming from LP1 suspend state. If it is, branch to the LP1-specific resume code. When Tegra enters the LP1 suspend state, the SDRAM controller is placed into a self-refresh state. For this reason, we must place the LP1 resume code into IRAM, so that it is accessible before SDRAM access has been re-enabled. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-08-08ARM: tegra: unify Tegra's Kconfig a bit moreStephen Warren
Move all common select clauses from ARCH_TEGRA_*_SOC to ARCH_TEGRA to eliminate duplication. The USB-related selects all should have been common too, but were missing from Tegra114 previously. Move these to ARCH_TEGRA too. The latter fixes a build break when only Tegra114 support was enabled, but not Tegra20 or Tegra30 support. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-07-29ARM: tegra: Remove USB platform dataTuomas Tynkkynen
USB-related platform data is not used anymore in the Tegra USB drivers, so remove all of it. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
2013-07-23Merge tag 'remove-local-timers' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/davidb/linux-msm into next/cleanup From Stephen Boyd: Now that we have a generic arch hook for broadcast we can remove the local timer API entirely. Doing so will reduce code in ARM core, reduce the architecture dependencies of our timer drivers, and simplify the code because we no longer go through an architecture layer that is essentially a hotplug notifier. * tag 'remove-local-timers' of git://git.kernel.org/pub/scm/linux/kernel/git/davidb/linux-msm: ARM: smp: Remove local timer API clocksource: time-armada-370-xp: Divorce from local timer API clocksource: time-armada-370-xp: Fix sparse warning ARM: msm: Divorce msm_timer from local timer API ARM: PRIMA2: Divorce timer-marco from local timer API ARM: EXYNOS4: Divorce mct from local timer API ARM: OMAP2+: Divorce from local timer API ARM: smp_twd: Divorce smp_twd from local timer API ARM: smp: Remove duplicate dummy timer implementation Resolved a large number of conflicts due to __cpuinit cleanups, etc. Signed-off-by: Olof Johansson <olof@lixom.net>
2013-07-19ARM: tegra: remove the limitation that Tegra114 can't support suspendJoseph Lo
The Tegra114 can support suspend function now, removing the limitation. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-07-19ARM: tegra: flowctrl: add support for cpu_suspend_enter/exitJoseph Lo
The flow controller can help CPU to go into suspend mode (powered-down state). When CPU goes into powered-down state, it needs some careful settings before getting into and after leaving. The enter and exit functions do that by configuring appropriate mode for flow controller. For Tegra114, the setting is compatible with Tegra30. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>