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path: root/arch/arm/mm/context.c
AgeCommit message (Expand)Author
2012-11-26ARM: 7582/2: rename kvm_seq to vmalloc_seq so to avoid confusion with KVMNicolas Pitre
2012-11-05ARM: mm: use bitmap operations when allocating new ASIDsWill Deacon
2012-11-05ARM: mm: avoid taking ASID spinlock on fastpathWill Deacon
2012-11-05ARM: mm: remove IPI broadcasting on ASID rolloverWill Deacon
2012-08-25ARM: 7502/1: contextidr: avoid using bfi instruction during notifierWill Deacon
2012-07-09ARM: 7445/1: mm: update CONTEXTIDR register to contain PID of current processWill Deacon
2012-04-17ARM: Remove current_mm per-cpu variableCatalin Marinas
2012-04-17ARM: Remove __ARCH_WANT_INTERRUPTS_ON_CTXSW on ASID-capable CPUsCatalin Marinas
2012-04-17ARM: Use TTBR1 instead of reserved context IDWill Deacon
2011-12-08ARM: LPAE: Add context switching supportCatalin Marinas
2011-09-13locking, ARM: Annotate low level hw locks as rawThomas Gleixner
2011-06-09Revert "ARM: 6944/1: mm: allow ASID 0 to be allocated to tasks"Russell King
2011-06-09Revert "ARM: 6943/1: mm: use TTBR1 instead of reserved context ID"Russell King
2011-05-26ARM: 6944/1: mm: allow ASID 0 to be allocated to tasksWill Deacon
2011-05-26ARM: 6943/1: mm: use TTBR1 instead of reserved context IDWill Deacon
2010-02-15ARM: 5905/1: ARM: Global ASID allocation on SMPCatalin Marinas
2009-10-29ARM: Fix errata 411920 workaroundsRussell King
2009-09-24cpumask: use mm_cpumask() wrapper: armRusty Russell
2007-05-09Merge branches 'armv7', 'at91', 'misc' and 'omap' into develRussell King
2007-05-09[ARM] armv7: add support for asid-tagged VIVT I-cacheCatalin Marinas
2007-05-08[ARM] Fix ASID version switchRussell King
2007-02-08[ARM] 4128/1: Architecture compliant TTBR changing sequenceCatalin Marinas
2006-09-20[ARM] Move mmu.c out of the wayRussell King
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