Age | Commit message (Expand) | Author |
---|---|---|
2012-04-17 | ARM: Remove __ARCH_WANT_INTERRUPTS_ON_CTXSW on ASID-capable CPUs | Catalin Marinas |
2012-04-17 | ARM: Use TTBR1 instead of reserved context ID | Will Deacon |
2011-12-08 | ARM: LPAE: Factor out classic-MMU specific code into proc-v7-2level.S | Catalin Marinas |