| Age | Commit message (Expand) | Author |
|---|---|---|
| 2013-05-30 | ARM: LPAE: accomodate >32-bit addresses for page table base | Cyril Chemparathy |
| 2013-05-30 | ARM: LPAE: factor out T1SZ and TTBR1 computations | Cyril Chemparathy |
| 2013-05-30 | ARM: LPAE: use phys_addr_t in switch_mm() | Cyril Chemparathy |
| 2013-04-03 | ARM: 7691/1: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP instead | Will Deacon |
| 2013-03-03 | ARM: 7652/1: mm: fix missing use of 'asid' to get asid value from mm->context.id | Ben Dooks |
| 2013-02-16 | ARM: 7650/1: mm: replace direct access to mm->context.id with new macro | Ben Dooks |
| 2012-11-09 | ARM: mm: introduce present, faulting entries for PAGE_NONE | Will Deacon |
| 2012-11-09 | ARM: mm: introduce L_PTE_VALID for page table entries | Will Deacon |
| 2011-12-08 | ARM: LPAE: MMU setup for the 3-level page table format | Catalin Marinas |
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