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path: root/arch/arm/mm/proc-v7-3level.S
AgeCommit message (Expand)Author
2014-09-25ARM: 8164/1: mm: clear SCTLR.HA instead of setting it for LPAEWill Deacon
2014-09-02ARM: 8132/1: LPAE: drop wrong carry flag correction after adding TTBR1_OFFSETKonstantin Khlebnikov
2014-08-09ARM: 8114/1: LPAE: load upper bits of early TTBR0/TTBR1Konstantin Khlebnikov
2014-07-24ARM: 8109/1: mm: Modify pte_write and pmd_write logic for LPAESteven Capper
2014-07-18ARM: convert all "mov.* pc, reg" to "bx reg" for ARMv6+Russell King
2014-04-25ARM: 8037/1: mm: support big-endian page tablesJianguo Wu
2013-07-22ARM: 7784/1: mm: ensure SMP alternates assemble to exactly 4 bytes with Thumb-2Will Deacon
2013-07-14arm: delete __cpuinit/__CPUINIT usage from all ARM usersPaul Gortmaker
2013-05-30ARM: LPAE: accomodate >32-bit addresses for page table baseCyril Chemparathy
2013-05-30ARM: LPAE: factor out T1SZ and TTBR1 computationsCyril Chemparathy
2013-05-30ARM: LPAE: use phys_addr_t in switch_mm()Cyril Chemparathy
2013-04-03ARM: 7691/1: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP insteadWill Deacon
2013-03-03ARM: 7652/1: mm: fix missing use of 'asid' to get asid value from mm->context.idBen Dooks
2013-02-16ARM: 7650/1: mm: replace direct access to mm->context.id with new macroBen Dooks
2012-11-09ARM: mm: introduce present, faulting entries for PAGE_NONEWill Deacon
2012-11-09ARM: mm: introduce L_PTE_VALID for page table entriesWill Deacon
2011-12-08ARM: LPAE: MMU setup for the 3-level page table formatCatalin Marinas