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path: root/arch/arm/mm/proc-v7-3level.S
AgeCommit message (Expand)Author
2013-05-30ARM: LPAE: accomodate >32-bit addresses for page table baseCyril Chemparathy
2013-05-30ARM: LPAE: factor out T1SZ and TTBR1 computationsCyril Chemparathy
2013-05-30ARM: LPAE: use phys_addr_t in switch_mm()Cyril Chemparathy
2013-04-03ARM: 7691/1: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP insteadWill Deacon
2013-03-03ARM: 7652/1: mm: fix missing use of 'asid' to get asid value from mm->context.idBen Dooks
2013-02-16ARM: 7650/1: mm: replace direct access to mm->context.id with new macroBen Dooks
2012-11-09ARM: mm: introduce present, faulting entries for PAGE_NONEWill Deacon
2012-11-09ARM: mm: introduce L_PTE_VALID for page table entriesWill Deacon
2011-12-08ARM: LPAE: MMU setup for the 3-level page table formatCatalin Marinas