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2011-07-07ARM: mm: tlb-v4wbi: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: tlb-v4wb: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: tlb-v4: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: tlb-v3: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: tlb-fa: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-xscale: Use new generic struct definition macrosDave Martin
Without this patch, xscale_80200_A0_A1 is missing the icache_flush_all entry, which would result in the wrong functions being called at run-time. This patch re-uses xscale_icache_flush_all for xscale_80200_A0_A1_cache_fns. Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-xsc3: Use new generic struct definition macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-v7: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-v6: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-sa1100: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-sa110: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-mohawk: Use the new processor struct macrosDave Martin
This patch also defines a suitable flush_icache_all implementation which would otherwise be missing, resulting in a link failure. Thanks to Nicolas Pitre for suggesting the code for this. Signed-off-by: Dave Martin <dave.martin@linaro.org> Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-07-07ARM: mm: proc-feroceon: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-07-07ARM: mm: proc-fa526: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-arm9tdmi: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-arm946: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-arm940: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-arm926: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-arm925: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-arm922: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-arm920: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-arm7tdmi: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-arm740: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-arm720: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-arm6_7: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-arm1026: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-arm1022: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-arm1020e: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-arm1020: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: cache-v7: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: cache-v6: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: cache-v4wt: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: cache-v4wb: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: cache-v4: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: cache-v3: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: cache-fa: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-macros: Add generic proc/cache/tlb struct definition macrosDave Martin
This patch adds some generic macros to reduce boilerplate when declaring certain common structures in arch/arm/mm/*.S Thanks to Russell King for outlining what the define_processor_functions macro could look like. Signed-off-by: Dave Martin <dave.martin@linaro.org> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-06-24ARM: pm: ensure ARMv7 CPUs save and restore the TLS registerRussell King
Ensure that the TLS register is saved and restored over a suspend cycle, so that userspace programs don't see a corrupted TLS value. Tested-by: Kevin Hilman <khilman@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-06-24ARM: pm: proc-v7: fix missing struct processor pointers for suspend codeRussell King
Add the missing suspend/resume pointers for the suspend code. This is needed when building for multiple CPUs. Tested-by: Kevin Hilman <khilman@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-06-11ARM: initrd: disable initrds outside of memoryRussell King
We can't cope with initrds outside of memory, so check that the initrd is within some declared memory to the kernel before using it. Otherwise we're likely to OOPS during boot. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-06-09Revert "ARM: 6944/1: mm: allow ASID 0 to be allocated to tasks"Russell King
This reverts commit 45b95235b0ac86cef2ad4480b0618b8778847479. Will Deacon reports that: In 52af9c6c ("ARM: 6943/1: mm: use TTBR1 instead of reserved context ID") I updated the ASID rollover code to use only the kernel page tables whilst updating the ASID. Unfortunately, the code to restore the user page tables was part of a later patch which isn't yet in mainline, so this leaves the code quite broken. We're also in the process of eliminating __ARCH_WANT_INTERRUPTS_ON_CTXSW from ARM, so lets revert these until we can properly sort out what we're doing with the context switching. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-06-09Revert "ARM: 6943/1: mm: use TTBR1 instead of reserved context ID"Russell King
This reverts commit 52af9c6cd863fe37d1103035ec7ee22ac1296458. Will Deacon reports that: In 52af9c6c ("ARM: 6943/1: mm: use TTBR1 instead of reserved context ID") I updated the ASID rollover code to use only the kernel page tables whilst updating the ASID. Unfortunately, the code to restore the user page tables was part of a later patch which isn't yet in mainline, so this leaves the code quite broken. We're also in the process of eliminating __ARCH_WANT_INTERRUPTS_ON_CTXSW from ARM, so lets revert these until we can properly sort out what we're doing with the ARM context switching. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-06-06ARM: 6951/1: include .bss in memory layout informationRabin Vincent
The "Virtual memory kernel layout" message at startup already prints .text and .data. Print .bss too. Signed-off-by: Rabin Vincent <rabin@rab.in> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-06-06ARM: 6948/1: Fix .size directives for __arm{7,9}tdmi_proc_infoBen Hutchings
gas used to accept (and ignore?) .size directives which referred to undefined symbols, as these do. In binutils 2.21 these are treated as fatal errors. The issue in proc-arm7tdmi.S was also fixed independently by Peter Chubb. Signed-off-by: Ben Hutchings <ben@decadent.org.uk> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-05-27Merge branches 'devel', 'devel-stable' and 'fixes' into for-linusRussell King
2011-05-26ARM: kill pmd_off()Russell King
pmd_off() has only one user, so lets consolidate this into its only user. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-05-26ARM: 6944/1: mm: allow ASID 0 to be allocated to tasksWill Deacon
Now that ASID 0 is no longer used as a reserved value, allow it to be allocated to tasks. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-05-26ARM: 6943/1: mm: use TTBR1 instead of reserved context IDWill Deacon
On ARMv7 CPUs that cache first level page table entries (like the Cortex-A15), using a reserved ASID while changing the TTBR or flushing the TLB is unsafe. This is because the CPU may cache the first level entry as the result of a speculative memory access while the reserved ASID is assigned. After the process owning the page tables dies, the memory will be reallocated and may be written with junk values which can be interpreted as global, valid PTEs by the processor. This will result in the TLB being populated with bogus global entries. This patch avoids the use of a reserved context ID in the v7 switch_mm and ASID rollover code by temporarily using the swapper_pg_dir pointed at by TTBR1, which contains only global entries that are not tagged with ASIDs. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-05-26ARM: 6942/1: mm: make TTBR1 always point to swapper_pg_dir on ARMv6/7Catalin Marinas
This patch makes TTBR1 point to swapper_pg_dir so that global, kernel mappings can be used exclusively on v6 and v7 cores where they are needed. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-05-26ARM: 6941/1: cache: ensure MVA is cacheline aligned in flush_kern_dcache_areaWill Deacon
The v6 and v7 implementations of flush_kern_dcache_area do not align the passed MVA to the size of a cacheline in the data cache. If a misaligned address is used, only a subset of the requested area will be flushed. This has been observed to cause failures in SMP boot where the secondary_data initialised by the primary CPU is not cacheline aligned, causing the secondary CPUs to read incorrect values for their pgd and stack pointers. This patch ensures that the base address is cacheline aligned before flushing the d-cache. Cc: <stable@kernel.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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