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2008-11-28[ARM] remove bogus #ifdef CONFIG_HIGHMEM in show_pte()Nicolas Pitre
The restriction on !CONFIG_HIGHMEM is unneeded since page tables are currently never allocated with highmem pages, and actually disable PTE dump whenever highmem is configured. Let's have a dynamic test to better describe the current limitation instead. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-28[ARM] prevent the vmalloc cmdline argument from eating all memoryNicolas Pitre
Commit 8d5796d2ec6b5a4e7a52861144e63af438d6f8f7 allows for the vmalloc area to be resized from the kernel cmdline. Make sure it cannot overlap with RAM entirely. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-28[ARM] mem_init() cleanupsNicolas Pitre
Make free_area() arguments pfn based, and return number of freed pages. This will simplify highmem initialization later. Also, codepages, datapages and initpages are actually codesize, datasize and initsize. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-28[ARM] split highmem into its own memory bankNicolas Pitre
Doing so will greatly simplify the bootmem initialization code as each bank is therefore entirely lowmem or highmem with no crossing between those zones. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-28[ARM] rationalize memory configuration code some moreNicolas Pitre
Currently there are two instances of struct meminfo: one in kernel/setup.c marked __initdata, and another in mm/init.c with permanent storage. Let's keep only the later to directly populate the permanent version from arm_add_memory(). Also move common validation tests between the MMU and non-MMU cases into arm_add_memory() to remove some duplication. Protection against overflowing the membank array is also moved in there in order to cover the kernel cmdline parsing path as well. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-28[ARM] fix a couple clear_user_highpage assembly constraintsNicolas Pitre
In all cases the kaddr is assigned an input register even though it is modified in the assembly code. Let's assign a new variable to the modified value and mark those inline asm with volatile otherwise they get optimized away because the output variable is otherwise not used. Also fix a few conversion errors in copypage-feroceon.c and copypage-v4mc.c. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-27[ARM] clearpage: provide our own clear_user_highpage()Russell King
For similar reasons as copy_user_page(), we want to avoid the additional kmap_atomic if it's unnecessary. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-27[ARM] copypage: provide our own copy_user_highpage()Russell King
We used to override the copy_user_page() function. However, this is not only inefficient, it also causes additional complexity for highmem support, since we convert from a struct page to a kernel direct mapped address and back to a struct page again. Moreover, with highmem support, we end up pointlessly setting up kmap entries for pages which we're going to remap. So, push the kmapping down into the copypage implementation files where it's required. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-27[ARM] copypage: convert assembly files to CRussell King
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-09[ARM] iop: iop3xx needs registers mapped uncached+unbufferedRussell King
Mikael Pettersson reported: The 2.6.28-rc kernels fail to detect PCI device 0000:00:01.0 (the first ethernet port) on my Thecus n2100 XScale box. There is however still a strange "ghost" device that gets partially detected in 2.6.28-rc2 vanilla. The IOP321 manual says: The user designates the memory region containing the OCCDR as non-cacheable and non-bufferable from the IntelR XScaleTM core. This guarantees that all load/stores to the OCCDR are only of DWORD quantities. Ensure that the OCCDR is so mapped. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-08[ARM] 5329/1: Feroceon: fix feroceon_l2_inv_rangeNicolas Pitre
Same fix as commit c7cf72dcadb: when 'start' and 'end' are less than a cacheline apart and 'start' is unaligned we are done after cleaning and invalidating the first cacheline. Cc: <stable@kernel.org> Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-06Merge branch 'fixes' of ↵Russell King
git://git.kernel.org/pub/scm/linux/kernel/git/djbw/xscaleiop
2008-11-06[ARM] xsc3: fix xsc3_l2_inv_rangeDan Williams
When 'start' and 'end' are less than a cacheline apart and 'start' is unaligned we are done after cleaning and invalidating the first cacheline. So check for (start < end) which will not walk off into invalid address ranges when (start > end). This issue was caught by drivers/dma/dmatest. 2.6.27 is susceptible. Cc: <stable@kernel.org> Cc: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> Cc: Lothar WaÃ<9f>mann <LW@KARO-electronics.de> Cc: Lennert Buytenhek <buytenh@marvell.com> Cc: Eric Miao <eric.miao@marvell.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2008-11-06[ARM] mm: fix page table initializationRussell King
As a result of the ptebits changes, we ended up marking device mappings as normal memory on ARMv7 CPUs, resulting in undesirable behaviour with serial ports and the like. While reviewing the section mapping table entries, other errors in the memory type settings for devices were detected and confirmed to prevent Xscale3 platforms booting. Tested on: OMAP34xx (ARMv7), OMAP24xx (ARMv6), OMAP16xx (ARM926T, ARMv5), PXA311 (Xscale3), PXA272 (Xscale), PXA255 (Xscale), IXP42x (Xscale), S3C2410 (ARM920T, ARMv4T), ARM720T (ARMv4T) StrongARM-110 (ARMv4) Acked-by: Tony Lindgren <tony@atomide.com> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Tested-by: Mike Rapoport <mike@compulab.co.il> Tested-by: Ben Dooks <ben-linux@fluff.org> Tested-by: Anders Grafström <grfstrm@users.sourceforge.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-06[ARM] fix naming of MODULE_START / MODULE_ENDRussell King
As of 73bdf0a60e607f4b8ecc5aec597105976565a84f, the kernel needs to know where modules are located in the virtual address space. On ARM, we located this region between MODULE_START and MODULE_END. Unfortunately, everyone else calls it MODULES_VADDR and MODULES_END. Update ARM to use the same naming, so is_vmalloc_or_module_addr() can work properly. Also update the comment on mm/vmalloc.c to reflect that ARM also places modules in a separate region from the vmalloc space. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-24[ARM] xsc3: revert writethrough memory-type encoding changeDan Williams
Commit 40df2d1d "[ARM] Update Xscale and Xscale3 PTE mappings" was fingered by git-bisect for a boot failure on iop13xx. The change made L_PTE_MT_WRITETHROUGH mappings L2-uncacheable. Russell points out that this mapping is used for the vector page. Given the regression, and the fact this page is used often, restore the old behaviour. Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2008-10-22[ARM] 5318/1: Swap the PRRR and NMRR values in proc-v7.SCatalin Marinas
A typo caused these values to be swapped leading to incorrect memory type attributes. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-22Merge branch 'for-rmk' of git://git.android.com/kernel into develRussell King
2008-10-22[ARM] msm: rename ARCH_MSM7X00A to ARCH_MSMBrian Swetland
The MSM architecture covers a wider family of chips than just the MSM7X00A. Move to a more generic name, in perparation for supporting the specific SoC variants as sub-architectures (ARCH_MSM7X01A, ARCH_MSM722X, etc). This gives us ARCH_MSM for the (many) common peripherals. This also removes the unused/obsolete config item MSM7X00A_IDLE. Signed-off-by: Brian Swetland <swetland@google.com>
2008-10-17[ARM] 5310/1: Fix cache flush functions for ARMv4Anders Grafström
ARMv4 (ARM720T) cache flush functions are broken in 2.6.19+ kernels. The issue was introduced by commit f12d0d7c7786af39435ef6ae9defe47fb58f6091 This patch corrects the CPU_CP15 ifdef statements so that they actually do something. Signed-off-by: Anders Grafström <grfstrm@users.sourceforge.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-14Merge branch 'omap-all' into develRussell King
Conflicts: arch/arm/mach-omap2/gpmc.c arch/arm/mach-omap2/irq.c
2008-10-09Merge branch 'for-rmk' of git://git.marvell.com/orionRussell King
Merge branch 'orion-devel' into devel
2008-10-09Merge branch 'ptebits' into develRussell King
Conflicts: arch/arm/Kconfig
2008-10-09ARM: OMAP3: Add minimal Beagle board supportSyed Mohammed, Khasim
Add minimal Beagle board support. Based on earlier patches by Syed Mohammed Khasim with some fixes from linux-omap tree. Signed-off-by: Syed Mohammed Khasim <khasim@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-10-03[ARM] 5229/3: Replace some ARMv7 opcodes with the instruction nameCatalin Marinas
These instructions were placed in the code directly as opcodes because early compilers didn't support them. Toolchains supporting ARMv7 understand these instructions and the patch puts the mnemonics back. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01[ARM] mm: finish ARM sparsemem supportRussell King
... including some comments about the ordering required to bring sparsemem up. You have to repeatedly guess, test, reguess, try again and again to work out what the right ordering is. Many hours later... Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01[ARM] mm: provide helpers for accessing membanksRussell King
Provide helpers for getting physical addresses or pfns from the meminfo array, and use them. Move for_each_nodebank() to asm/setup.h alongside the meminfo structure definition. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01[ARM] Don't include asm/elf.h in asm codeRussell King
asm code really wants asm/hwcap.h, so include that instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01[ARM] Remove MT_DEVICE_IXP2000 and associated definitionsRussell King
As of the previous commit, MT_DEVICE_IXP2000 encodes to the same PTE bit encoding as MT_DEVICE, so it's now redundant. Convert MT_DEVICE_IXP2000 to use MT_DEVICE instead, and remove its aliases. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01[ARM] Update Xscale and Xscale3 PTE mappingsRussell King
Use 'shared device' mappings for devices, and use the standard bit combinations for Xscale3. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01[ARM] remove 'prot_pte_ext' from memory type tableRussell King
This member is now redundant; the memory type is encoded in the Linux PTE bits. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01[ARM] Convert ARMv7 to use TEX remappingRussell King
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01[ARM] Convert ARMv6 and ARMv7 to use new memory typesRussell King
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01[ARM] Convert Xscale and Xscale3 to use new memory typesRussell King
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01[ARM] Introduce new PTE memory type bitsRussell King
Provide L_PTE_MT_xxx definitions to describe the memory types that we use in Linux/ARM. These definitions are carefully picked such that: 1. their LSBs match what is required for pre-ARMv6 CPUs. 2. they all have a unique encoding, including after modification by build_mem_type_table() (the result being that some have more than one combination.) Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01[ARM] Convert set_pte_ext implementions to macrosRussell King
There are actually only four separate implementations of set_pte_ext. Use assembler macros to insert code for these into the proc-*.S files. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-30[ARM] mm: move vmalloc= parsing to arch/arm/mm/mmu.cRussell King
There's no point scattering this around the tree, the parsing of the parameter might as well live beside the code which uses it. That also means we can make vmalloc_reserve a static variable. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-30[ARM] mm: move validation of membanks to one placeRussell King
The newly introduced sanity_check_meminfo() function should be used to collect all validation of the meminfo array, which we have in bootmem_init(). Move it there. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-30[ARM] Feroceon: small cleanups to L2 cache codeNicolas Pitre
- Make sure that coprocessor instructions for range ops are contiguous and not reordered. - s/invalidate_and_disable_dcache/flush_and_disable_dcache/ - Don't re-enable I/D caches if they were not enabled initially. - Change some masks to shifts for better generated code. Signed-off-by: Nicolas Pitre <nico@marvell.com> Acked-by: Lennert Buytenhek <buytenh@marvell.com>
2008-09-30[ARM] 5272/1: remove conditional compilation in show_pte()Nicolas Pitre
The PTRS_PER_PMD != 1 condition can be evaluated with C code and optimized at compile time. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-30[ARM] dma: don't touch cache on dma_*_for_cpu()Russell King
As per the dma_unmap_* calls, we don't touch the cache when a DMA buffer transitions from device to CPU ownership. Presently, no problems have been identified with speculative cache prefetching which in itself is a new feature in later architectures. We may have to revisit the DMA API later for these architectures anyway. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-29[ARM] dma: Reduce to one dma_sync_sg_* implementationRussell King
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-25[ARM] dma: Reduce to one dma_map_sg()/dma_unmap_sg() implementationRussell King
No point having two of these; dma_map_page() can do all the work for us. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-25[ARM] Kirkwood: add support for L2 cache WB/WT selectionRonen Shitrit
Feroceon L2 cache can work in eighther write through or write back mode on Kirkwood. Add the option to configure this mode according to Kconfig. Signed-off-by: Ronen Shitrit <rshitrit@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
2008-09-25[ARM] Update dma_map_sg()/dma_unmap_sg() APIRussell King
Update the ARM DMA scatter gather APIs for the scatterlist changes. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-25[ARM] dma: rename consistent.c to dma-mapping.cRussell King
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-06[ARM] 5241/1: provide ioremap_wc()Lennert Buytenhek
This patch provides an ARM implementation of ioremap_wc(). We use different page table attributes depending on which CPU we are running on: - Non-XScale ARMv5 and earlier systems: The ARMv5 ARM documents four possible mapping types (CB=00/01/10/11). We can't use any of the cached memory types (CB=10/11), since that breaks coherency with peripheral devices. Both CB=00 and CB=01 are suitable for _wc, and CB=01 (Uncached/Buffered) allows the hardware more freedom than CB=00, so we'll use that. (The ARMv5 ARM seems to suggest that CB=01 is allowed to delay stores but isn't allowed to merge them, but there is no other mapping type we can use that allows the hardware to delay and merge stores, so we'll go with CB=01.) - XScale v1/v2 (ARMv5): same as the ARMv5 case above, with the slight difference that on these platforms, CB=01 actually _does_ allow merging stores. (If you want noncoalescing bufferable behavior on Xscale v1/v2, you need to use XCB=101.) - Xscale v3 (ARMv5) and ARMv6+: on these systems, we use TEXCB=00100 mappings (Inner/Outer Uncacheable in xsc3 parlance, Uncached Normal in ARMv6 parlance). The ARMv6 ARM explicitly says that any accesses to Normal memory can be merged, which makes Normal memory more suitable for _wc mappings than Device or Strongly Ordered memory, as the latter two mapping types are guaranteed to maintain transaction number, size and order. We use the Uncached variety of Normal mappings for the same reason that we can't use C=1 mappings on ARMv5. The xsc3 Architecture Specification documents TEXCB=00100 as being Uncacheable and allowing coalescing of writes, which is also just what we need. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-06[ARM] Convert asm/io.h to linux/io.hRussell King
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-06[ARM] Convert asm/uaccess.h to linux/uaccess.hRussell King
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-06[ARM] clean up a load of old declarationsRussell King
... some of which are now in linux/*.h headers. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>