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2010-02-15ARM: 5928/1: Change type of VMALLOC_END to unsigned long.Fenkart/Bostandzhyan
Makes it consistent with VMALLOC_START Tested-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Andreas Fenkart <andreas.fenkart@streamunlimited.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-02-15ARM: 5927/1: Make delimiters of DMA area globally visibly.Fenkart/Bostandzhyan
Adds DMA area to 'virtual memory map' startup message Tested-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Andreas Fenkart <andreas.fenkart@streamunlimited.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-02-15ARM: 5926/1: Add "Virtual kernel memory..." printout.Fenkart/Bostandzhyan
Code based on parisc and x86_32. Tested-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Andreas Fenkart <andreas.fenkart@streamunlimited.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-02-15ARM: 5919/1: ARM: L2 : Errata 588369: Clean & Invalidate do not invalidate ↵Santosh Shilimkar
clean lines This patch implements the work-around for the errata 588369.The secure API is used to alter L2 debug register because of trust-zone. This version updated with comments from Russell and Catalin and generated against 2.6.33-rc6 mainline kernel. Detail comments can be found: http://www.spinics.net/lists/linux-omap/msg23431.html Signed-off-by: Woodruff Richard <r-woodruff2@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-02-15ARM: 5917/1: OMAP4: Add L2 Cache supportSantosh Shilimkar
This patch adds L2 Cache support for OMAP4. External L2 cache is used in OMAP4 CC: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-02-15ARM: 5916/1: ARM: L2 : Add maintainace by line helper functionsSantosh Shilimkar
This patch adds the cache maintainance by line helper functions. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-02-15ARM: 5911/1: ARM: Select CPU_32v6K for CPU_V7 only if ARCH_OMAP2 is not selectedTony Lindgren
Otherwise the kernel built with both CPU_V6 and CPU_V7 will not boot on omap2. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-02-15ARM: 5905/1: ARM: Global ASID allocation on SMPCatalin Marinas
The current ASID allocation algorithm doesn't ensure the notification of the other CPUs when the ASID rolls over. This may lead to two processes using the same ASID (but different generation) or multiple threads of the same process using different ASIDs. This patch adds the broadcasting of the ASID rollover event to the other CPUs. To avoid a race on multiple CPUs modifying "cpu_last_asid" during the handling of the broadcast, the ASID numbering now starts at "smp_processor_id() + 1". At rollover, the cpu_last_asid will be set to NR_CPUS. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-02-15ARM: 5880/1: arm: use generic infrastructure for early paramsJeremy Kerr
The ARM setup code includes its own parser for early params, there's also one in the generic init code. This patch removes __early_init (and related code) from arch/arm/kernel/setup.c, and changes users to the generic early_init macro instead. The generic macro takes a char * argument, rather than char **, so we need to update the parser functions a little. Signed-off-by: Jeremy Kerr <jeremy.kerr@canonical.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-02-15ARM: Move creation of /proc/cpu out of alignment.cRussell King
Always creating this directory avoids other users having to jump through silly hoops when they want to share this directory. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-02-15ARM: Add caller information to ioremapRussell King
This allows the procfs vmallocinfo file to show who created the ioremap regions. Note: __builtin_return_address(0) doesn't do what's expected if its used in an inline function, so we leave __arm_ioremap callers in such places alone. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-01-12Merge master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds
* master.kernel.org:/home/rmk/linux-2.6-arm: ARM: Ensure ARMv6/7 mm files are built using appropriate assembler options ARM: Fix wrong dmb ARM: 5874/1: serial21285: fix disable_irq-from-interrupt-handler deadlock ARM: 5873/1: ARM: Fix the reset logic for ARM RealView boards ARM: 5872/1: ARM: include needed linux/cpu.h in asm/cpu.h ARM: 5871/1: arch/arm: Fix build failure for lpd7a404_defconfig caused by missing includes ARM: 5870/1: arch/arm: Fix build failure for defconfigs without CONFIG_ISA_DMA_API set ARM: 5868/1: ARM: fix "BUG: using smp_processor_id() in preemptible code" ARM: 5867/1: Update U300 defconfig ARM: 5866/1: arm ptrace: use unsigned types for kernel pt_regs [ARM] pxa: fix strange characters in zaurus gpio .desc ARM: add missing recvmmsg syscall number [ARM] pxa: fix compiler warnings of unused variable 'id' in cpu_is_pxa9*() [ARM] pxa: update pwm_backlight->notify() to include missed 'struct device *' [ARM] pxa: enable L2 if present in XSC3 [ARM] pxa: do not enable L2 after MMU is enabled
2010-01-12ARM: Ensure ARMv6/7 mm files are built using appropriate assembler optionsRussell King
A kernel with both ARMv6 and ARMv7 selected results in build errors. Fix this by specifying the proper architectures for these assembly files. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-01-11mm: make totalhigh_pages unsigned longAndreas Fenkart
Makes it consistent with the extern declaration, used when CONFIG_HIGHMEM is set Removes redundant casts in printout messages Signed-off-by: Andreas Fenkart <andreas.fenkart@streamunlimited.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: David Howells <dhowells@redhat.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Chen Liqin <liqin.chen@sunplusct.com> Cc: Lennox Wu <lennox.wu@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-01-08Merge branch 'fix' of ↵Russell King
git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6
2010-01-05ARM: 5858/1: Remove unused vma_vm_flags macro from v7wbi_flush_user_tlb_rangeBahadir Balban
Signed-off-by: Bahadir Balban <bbalban@b-labs.co.uk> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-01-01[ARM] pxa: enable L2 if present in XSC3Haojian Zhuang
Check whether L2 is present or not in XSC3. If it's present, enable L2 immediately. Disabling L2 after L2 is enabled that would result in unpredicatable behavior of XSC3 processor. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
2010-01-01[ARM] pxa: do not enable L2 after MMU is enabledHaojian Zhuang
Outer cache checked whether L2 is enabled or not. If L2 isn't enabled in XSC3, it would enable L2. This operation is evil that would make system hang. In XSC3 core document, these words are mentioned in below. "Following reset, the L2 Unified Cache Enable bit is cleared. To enable the L2 Cache, software may set the bit to a '1' before or at the same time as enabling the MMU. Enabling the L2 Cache after the MMU has been enabled or disabling the L2 Cache after the L2 Cache has been enabled, may result in unpredictable behavior of the processor." When outer cache is initialized, the MMU is already enabled. We couldn't enable L2 after MMU enabled. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
2009-12-24ARM: fix PAGE_KERNELRussell King
PAGE_KERNEL should not be executable; any area marked executable can be prefetched into the instruction cache. We don't want vmalloc areas to be read in this way. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-12-23ARM: Fix wrong shared bit for CPU write buffer bug testRussell King
It is unpredictable to have the same memory mapped using different shared bit settings for ARMv6 and ARMv7 CPUs. Fix this for the CPU write buffer bug test. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-12-18ARM: Kill CONFIG_CPU_32Russell King
26-bit ARM support was removed a long time ago, and this symbol has been defined to be 'y' ever since. As it's never disabled anymore, we can kill it without any side effects. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-12-18ARM: 5853/1: ARM: Fix build break on ARM v6 and v7Anand Gadiyar
Commit 2c9b9c849 added an argument to __cpuc_flush_dcache_page and renamed it. Update a caller of the old function to fix this build error: CC arch/arm/mm/copypage-v6.o arch/arm/mm/copypage-v6.c: In function 'v6_copy_user_highpage_nonaliasing': arch/arm/mm/copypage-v6.c:51: error: implicit declaration of function '__cpuc_flush_dcache_page' make[1]: *** [arch/arm/mm/copypage-v6.o] Error 1 make: *** [arch/arm/mm] Error 2 Reported-by: Jinsung Yang <jsgood.yang@samsung.com> Signed-off-by: Anand Gadiyar <gadiyar@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-12-17Merge branch 'cache' (early part)Russell King
2009-12-16Merge branch 'for-rmk' of git://git.marvell.com/orionRussell King
2009-12-14Merge branch 'pending-l2x0' into cacheRussell King
2009-12-14ARM: add size argument to __cpuc_flush_dcache_pageRussell King
... and rename the function since it no longer operates on just pages. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-12-14ARM: 5848/1: kill flush_ioremap_region()Nicolas Pitre
There is not enough users to warrant its existence, and it is actually an obstacle to progress with the new DMA API which cannot cover this case properly. To keep backward compatibility, let's perform the necessary custom cache maintenance locally in the only driver affected. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-12-14ARM: cache-l2x0: make better use of background cache handlingRussell King
There's no point having the hardware support background operations if we issue a cache operation, and then wait for it to complete before calculating the address of the next operation. We gain no advantage in the cache controller stalling the bus until completion. What we should be doing is using the 'wait' time productively by calculating the address of the next operation, and only then waiting for the previous operation to complete. This means that cache operations can occur in parallel with the CPU calculating the next address. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
2009-12-14ARM: cache-l2x0: avoid taking spinlock for every iterationRussell King
Taking the spinlock for every iteration is very expensive; instead, batch iterations up into 4K blocks, releasing and reacquiring the spinlock between each block. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
2009-12-11fix broken aliasing checks for MAP_FIXED on sparc32, mips, arm and shAl Viro
We want addr - (pgoff << PAGE_SHIFT) consistently coloured... Acked-by: Paul Mundt <lethal@linux-sh.org> Acked-by: Hugh Dickins <hugh.dickins@tiscali.co.uk> Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2009-12-07ARM: dove: fix the mm mmu flags of the pj4 procinfoSaeed Bishara
... to be the same as proc-v6 Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
2009-12-05Merge branch 'devel-stable' into develRussell King
2009-12-04Merge branch 'devel' of ↵Russell King
git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6 into devel-stable
2009-12-04Merge branch 'pending-dma-coherent' into develRussell King
2009-12-04Merge branch 'pending-misc' (early part) into develRussell King
2009-12-04ARM: I-cache: flush executable mappings in flush_cache_range()Russell King
Dirk Behme reported instability on ARM11 SMP (VIPT non-aliasing cache) caused by the dynamic linker changing protection on text pages to write GOT entries. The problem is due to an interaction between the write faulting code providing new anonymous pages which are incoherent with the I-cache due to write buffering, and the I-cache not having been invalidated. a4db94d plugs the hole with the data cache coherency. This patch provides the other half of the fix by flushing the I-cache in flush_cache_range() for VM_EXEC VMAs (which is what we have when the region is being made executable again.) This ensures that the I-cache will be up to date with the newly COW'd pages. Note: if users are writing instructions, then they still need to use the ARM sys_cacheflush API to ensure that the caches are correctly synchronized. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-12-04ARM: I-cache: avoid flushing in flush_cache_mm()Russell King
flush_cache_mm() is called in two cases: 1. when a process exits, just before the page tables are torn down. We can allow the stale lines to evict themselves over time without causing any harm. 2. when a process forks, and we've allocated a new ASID. The instruction cache issues are dealt with as pages are brought into the new process address space. Flushing the I-cache here is therefore unnecessary. However, we must keep the VIPT aliasing D-cache flush to ensure that any dirty cache lines are not written back after the pages have been reallocated for some other use - which would result in corruption. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-12-04ARM: I-cache: Add invalidation for VIVT ASID tagged cachesRussell King
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-12-04ARM: 5794/1: Flush the D-cache during copy_user_highpage()Catalin Marinas
The I and D caches for copy-on-write pages on processors with write-allocate caches become incoherent causing problems on application relying on CoW for text pages (dynamic linker relocating symbols in a text page). This patch flushes the D-cache for such pages. Cc: Nicolas Pitre <nico@fluxnic.net> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-12-04ARM: Remove __flush_icache_all() from __flush_dcache_page()Russell King
Both call sites for __flush_dcache_page() end up calling __flush_icache_all() themselves, so having __flush_dcache_page() do this as well is wasteful. Remove the duplicated icache flushing. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-12-04ARM: Move __flush_icache_all() out of flush_pfn_alias()Russell King
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-12-04ARM: Reduce __flush_dcache_page() visibilityRussell King
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-12-03ARM: 5845/1: l2x0: check whether l2x0 already enabledSrinidhi Kasagar
If running in non-secure mode accessing some registers of l2x0 will fault. So check if l2x0 is already enabled, if so do not access those secure registers. Signed-off-by: srinidhi kasagar <srinidhi.kasagar@stericsson.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-12-01Merge branch 'for-rmk' of git://git.marvell.com/orion into devel-stableRussell King
2009-12-01ARM: ZERO_PAGE: Avoid flush_dcache_page() for zero pageRussell King
The zero page is read-only, and has its cache state cleared during boot. No further maintanence for this page is required. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-12-01ARM: Avoid evaluating page_address() multiple timesRussell King
page_address() is a function call rather than a macro, and so: if (page_address(page)) do_something(page_address(page)); results in two calls to this function. This is unnecessary; remove the duplication. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-12-01ARM: Avoid duplicated implementation for VIVT cache flushingRussell King
We had two copies of the wrapper code for VIVT cache flushing - one in asm/cacheflush.h and one in arch/arm/mm/flush.c. Reduce this down to one common copy. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-12-01[ARM] pxa/treo: add Palm Centro 685 supportTomáš Čech
Signed-off-by: Tomáš Čech <sleep_walker@suse.cz> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
2009-11-27ARM: Add Tauros2 L2 cache controller supportLennert Buytenhek
Support for the Tauros2 L2 cache controller as used with the PJ1 and PJ4 CPUs. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
2009-11-27ARM: add base support for Marvell Dove SoCSaeed Bishara
The Marvell Dove (88AP510) is a high-performance, highly integrated, low power SoC with high-end ARM-compatible processor (known as PJ4), graphics processing unit, high-definition video decoding acceleration hardware, and a broad range of peripherals. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
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