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2011-07-07ARM: vmlinux.lds: move init sections between text and data sectionsRussell King
Place the init sections between the text and data sections. This means all code is grouped together at the beginning of the kernel image, and all data is at the end of the image. This avoids problems with the 24-bit branch instruction relocations becoming invalid with large initramfs images. Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Tested-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-07-07ARM: proc: add definition of cpu_reset for ARMv6 and ARMv7 coresWill Deacon
This patch adds simple definitions of cpu_reset for ARMv6 and ARMv7 cores, which disable the MMU via the SCTLR. Signed-off-by: Will Deacon <will.deacon@arm.com>
2011-07-07ARM: proc: add proc info for Cortex-A15MP using classic page tablesWill Deacon
Multicore implementations of the Cortex-A15 require bit 6 of the auxiliary control register to be set in order for cache and TLB maintenance operations to be broadcast between CPUs. This patch adds a new proc_info structure for Cortex-A15, which enables the SMP bit during setup and includes the new HWCAP for integer division. Signed-off-by: Will Deacon <will.deacon@arm.com>
2011-07-07ARM: proc: add Cortex-A5 proc infoPawel Moll
This patch adds processor info for ARM Ltd. Cortex A5, which has SCU initialisation procedure identical to A9. Signed-off-by: Pawel Moll <pawel.moll@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2011-07-07ARM: proc: convert v7 proc infos into a common macroPawel Moll
As most of the proc info content is common across all v7 processors, this patch converts existing A9 and generic v7 descriptions into a macro (allowing extra flags in future). Signed-off-by: Pawel Moll <pawel.moll@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2011-07-07ARM: cns3xxx: Add support for L2 Cache ControllerAnton Vorontsov
CNS3xxx SOCs have L310-compatible cache controller, so let's use it. With this patch benchmarking with 'gzip' shows that performance is doubled, and I'm still able to boot full-fledged userland over NFS (using PCIe NIC), so the support should be pretty robust. p.s. While CNS3xxx reports that it has PL310, it still needs to wait on cache line operations, so we should not select 'CACHE_PL310', which is a micro-optimization that removes these waits for v7 CPUs. Someday we'd better rename CACHE_PL310 Kconfig option into NO_CACHE_WAIT or something less ambiguous. Signed-off-by: Anton Vorontsov <avorontsov@mvista.com>
2011-07-07ARM: mm: tlb-v7: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: tlb-v6: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: tlb-v4wbi: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: tlb-v4wb: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: tlb-v4: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: tlb-v3: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: tlb-fa: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-xscale: Use new generic struct definition macrosDave Martin
Without this patch, xscale_80200_A0_A1 is missing the icache_flush_all entry, which would result in the wrong functions being called at run-time. This patch re-uses xscale_icache_flush_all for xscale_80200_A0_A1_cache_fns. Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-xsc3: Use new generic struct definition macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-v7: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-v6: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-sa1100: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-sa110: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-mohawk: Use the new processor struct macrosDave Martin
This patch also defines a suitable flush_icache_all implementation which would otherwise be missing, resulting in a link failure. Thanks to Nicolas Pitre for suggesting the code for this. Signed-off-by: Dave Martin <dave.martin@linaro.org> Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-07-07ARM: mm: proc-feroceon: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-07-07ARM: mm: proc-fa526: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-arm9tdmi: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-arm946: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-arm940: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-arm926: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-arm925: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-arm922: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-arm920: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-arm7tdmi: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-arm740: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-arm720: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-arm6_7: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-arm1026: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-arm1022: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-arm1020e: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-arm1020: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: cache-v7: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: cache-v6: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: cache-v4wt: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: cache-v4wb: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: cache-v4: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: cache-v3: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: cache-fa: Use the new processor struct macrosDave Martin
Signed-off-by: Dave Martin <dave.martin@linaro.org>
2011-07-07ARM: mm: proc-macros: Add generic proc/cache/tlb struct definition macrosDave Martin
This patch adds some generic macros to reduce boilerplate when declaring certain common structures in arch/arm/mm/*.S Thanks to Russell King for outlining what the define_processor_functions macro could look like. Signed-off-by: Dave Martin <dave.martin@linaro.org> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-07-06ARM: 6987/1: l2x0: fix disabling function to avoid deadlockWill Deacon
The l2x0_disable function attempts to writel with the l2x0_lock held. This results in deadlock when the writel contains an outer_sync call for the platform since the l2x0_lock is already held by the disable function. A further problem is that disabling the L2 without flushing it first can lead to the spin_lock operation becoming visible after the spin_unlock, causing any subsequent L2 maintenance to deadlock. This patch replaces the writel with a call to writel_relaxed in the disabling code and adds a flush before disabling in the control register, preventing livelock from occurring. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-07-05ARM: move memory layout sanity checking before meminfo initializationRussell King
Ensure that the meminfo array is sanity checked before we pass the memory to memblock. This helps to ensure that memblock and meminfo agree on the dimensions of memory, especially when more memory is passed than the kernel can deal with. Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-07-02ARM: entry: data abort: ensure r5 is preserved by abort functionsRussell King
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-07-02ARM: entry: data abort: always use r6 for offsetRussell King
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-07-02ARM: entry: data abort: use r2 as base of pt_regs rather than stackRussell King
Now that we pass r2 into these helper functions as the pointer to pt_regs, use r2 as the base of the registers on the stack rather than using the stack pointer directly. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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