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2013-06-17ARM: 7754/1: Fix the CPU ID and the mask associated to the PJ4BGregory CLEMENT
This commit fixes the ID and mask for the PJ4B which was too restrictive and didn't match the CPU of the Armada 370 SoC. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Cc: <stable@vger.kernel.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-06-17ARM: 7753/1: map_init_section flushes incorrect pmdPo-Yu Chuang
This bug was introduced in commit e651eab0. Some v4/v5 platforms failed to boot due to this. Signed-off-by: Po-Yu Chuang <ratbert.chuang@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-06-17ARM: 7752/1: errata: LoUIS bit field in CLIDR register is incorrectJon Medhurst
On Cortex-A9 before version r1p0, the LoUIS bit field of the CLIDR register returns zero when it should return one. This leads to cache maintenance operations which rely on this value to not function as intended, causing data corruption. The workaround for this errata is to detect affected CPUs and correct the LoUIS value read. Acked-by: Will Deacon <will.deacon@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Cc: stable@vger.kernel.org Signed-off-by: Jon Medhurst <tixy@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-06-17ARM: shmobile: r8a7790: don't use external clock for SCIFsUlrich Hecht
This is an external component and may or may not be there, while the internal clock always works. Signed-off-by: Ulrich Hecht <ulrich.hecht@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-06-17ARM: shmobile: r8a7790: HSCIF supportUlrich Hecht
Adds support for HSCIF0 and HSCIF1 on the r8a7790. Signed-off-by: Ulrich Hecht <ulrich.hecht@gmail.com> [ horms+renesas@verge.net.au this is the setup-r8a7790.c which I somehow miss-applied as part of another patch. The clock-r8a7790.c portion of this patch has already been merged. ] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-06-17arm: dt: zynq: Add support for the zed platformSoren Brinkmann
Add a DT fragment for the Zed Zynq platform and a corresponding target to the Makefile Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Reviewed-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-06-17arm: dt: zynq: Add support for the zc706 platformSoren Brinkmann
Add a DT fragment for the zc706 Zynq platform and a corresponding target to the Makefile. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Reviewed-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-06-17arm: dt: zynq: Use 'status' property for UART nodesSoren Brinkmann
Set the default status for UARTs to disabled in the zynq-7000.dtsi file and let board dts files enable the UARTs on demand. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Reviewed-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-06-17arm: zynq: Remove board specific compatibility stringSoren Brinkmann
It is not necessary to have board specific compatibility strings in the platform code. The board dts files can use the more generic 'xlnx,zynq-7000' string. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Reviewed-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-06-17ARM: 7758/1: introduce config HAS_BANDGAPEduardo Valentin
Bandgap is a device used to measure temperature on electronic equipments. It is widely used in digital integrated circuits. It is based on the dependency between silicon voltage and temperature. This patch introduce HAS_BANDGAP config entry. This config is a boolean value so that arch code can flag if they feature a bandgap device. This config entry follows the same idea behind ARCH_HAS_CPUFREQ. Cc: linux-arm-kernel@lists.infradead.org Cc: linux-omap@vger.kernel.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Fabio Stevam <festevam@gmail.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Amit Daniel Kachhap <amit.daniel@samsung.com> Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-06-17ARM: 7757/1: mm: don't flush icache in switch_mm with hardware broadcastingWill Deacon
When scheduling an mm on a CPU where it hasn't previously been used, we flush the icache on that CPU so that any code loaded previously on a different core can be safely executed. For cores with hardware broadcasting of cache maintenance operations, this is clearly unnecessary, since the inner-shareable invalidation in __sync_icache_dcache will affect all CPUs. This patch conditionalises the icache flush in switch_mm based on cache_ops_need_broadcast(). Acked-by: Catalin Marinas <catalin.marinas@arm.com> Reported-by: Albin Tonnerre <albin.tonnerre@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-06-17ARM: 7751/1: zImage: don't overwrite ourself with a page tableNicolas Pitre
When zImage is loaded into RAM at a low address but TEXT_OFFSET is set higher, we risk overwriting ourself with the page table needed to turn on the cache as it is located relative to the relocation address. Let's defer the cache setup after relocation in that case. Signed-off-by: Nicolas Pitre <nico@linaro.org> Reported-by: Stephen Boyd <sboyd@codeurora.org> Tested-by: Stephen Boyd <sboyd@codeurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-06-17ARM: 7749/1: spinlock: retry trylock operation if strex fails on free lockWill Deacon
An exclusive store instruction may fail for reasons other than lock contention (e.g. a cache eviction during the critical section) so, in line with other architectures using similar exclusive instructions (alpha, mips, powerpc), retry the trylock operation if the lock appears to be free but the strex reported failure. Reported-by: Tony Thompson <anthony.thompson@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-06-17ARM: 7748/1: oabi: handle faults when loading swi instruction from userspaceWill Deacon
Running an OABI_COMPAT kernel on an SMP platform can lead to fun and games with page aging. If one CPU issues a swi instruction immediately before another CPU decides to mkold the page containing the swi instruction, then we will fault attempting to load the instruction during the vector_swi handler in order to retrieve its immediate field. Since this fault is not currently dealt with by our exception tables, this results in a panic: Unable to handle kernel paging request at virtual address 4020841c pgd = c490c000 [4020841c] *pgd=84451831, *pte=bf05859d, *ppte=00000000 Internal error: Oops: 17 [#1] PREEMPT SMP ARM Modules linked in: hid_sony(O) CPU: 1 Tainted: G W O (3.4.0-perf-gf496dca-01162-gcbcc62b #1) PC is at vector_swi+0x28/0x88 LR is at 0x40208420 This patch wraps all of the swi instruction loads with the USER macro and provides a shared exception table entry which simply rewinds the saved user PC and returns from the system call (without setting tbl, so there's no worries with tracing or syscall restarting). Returning to userspace will re-enter the page fault handler, from where we will probably send SIGSEGV to the current task. Reported-by: Wang, Yalin <yalin.wang@sonymobile.com> Reviewed-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-06-17ARM: dts: imx27: Add VPU devicetree nodeAlexander Shiyan
This patch adds the missing VPU devicetree node for i.MX27 CPUs. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17ARM: mxc: fix gpio-ranges for VF610Stephen Warren
The gpio-ranges properties in vf610.dtsi were written according to an older version of the GPIO bindings. Unfortunately, these were changed incompatibly in commit 86853c8 "gpio: add gpio offset in gpio range cells property". This patch adds the missing required extra cell in each gpio-ranges property. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17ARM: dtsi: imx6qdl-sabresd: Enable WM8962 audio supportNicolin Chen
Enable WM8962 ALSA machine driver via devicetree. Signed-off-by: Nicolin Chen <b42378@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17ARM: dtsi: imx6qdl-sabresd: Enable SSI2 and AUDMUXNicolin Chen
Enable SSI2 and its pin configuration in AUDMUX. Signed-off-by: Nicolin Chen <b42378@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17ARM: dtsi: imx6qdl-sabresd: Add WM8962 CODEC supportNicolin Chen
Add WM8962 CODEC support and enable its parent I2C bus. Signed-off-by: Nicolin Chen <b42378@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17ARM: dtsi: imx6qdl-sabresd: add a fixed regulator for WM8962Nicolin Chen
On Sabre SD, system controls WM8962 power by pulling up/down GPIO_4_10, so add a regulator controled by GPIO_4_10 for WM8962. Signed-off-by: Nicolin Chen <b42378@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17ARM: dtsi: imx6dl: Add a pinctrl for AUDMUXNicolin Chen
Add a pinctrl for AUDMUX used on imx6dl-sabresd. Signed-off-by: Nicolin Chen <b42378@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17ARM: dtsi: imx6q/imx6dl: Add a pinctrl for I2C1Nicolin Chen
Add a pinctrl for I2C1 used on imx6q/dl-sabresd. Signed-off-by: Nicolin Chen <b42378@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17ARM: dts: imx6qdl-sabresd: add clko1 iomux configurationNicolin Chen
Setting GPIO_0 pad as clko1 clock output to provide MCLK for WM8962. Signed-off-by: Nicolin Chen <b42378@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17ARM: dts: Phytec imx6q pfla02 and pbab01 supportChristian Hemp
Add support for imx6q Phytec phyFLEX-i.MX6 Quad (aka pfla02 and pbab01). - Module pfla02 - Carrier-Board pbab01 Signed-off-by: Christian Hemp <c.hemp@phytec.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17ARM: dts: imx6q: Add pinctrl for usdhc2 and enetChristian Hemp
Add a group to the usdhc2 and enet pinctrl. Signed-off-by: Christian Hemp <c.hemp@phytec.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17ARM: dts: imx27-phytec-phycore-rdk: Add MTD name for NOR flashAlexander Shiyan
This patch adds name for NOR flash. This keeps compatibility for commandline partitions parsing from old bootloaders and make name of device same for DT and non-DT boot. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Acked-by: Sascha Hauer <s.hauer@pengutonix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17ARM: dts: imx27-phytec-phycore-rdk: Add SDHC supportAlexander Shiyan
This patch adds the SHDC devicetree node for PCM970 board. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Acked-by: Sascha Hauer <s.hauer@pengutonix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17ARM: dts: i.MX27: Add SDHC devicetree nodesAlexander Shiyan
This patch adds the missing SDHC devicetree nodes for i.MX27 SoCs. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Acked-by: Sascha Hauer <s.hauer@pengutonix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17ARM: dts: i.MX27: Add DMA devicetree nodeAlexander Shiyan
This patch adds the missing DMA devicetree node for i.MX27 SoCs. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Acked-by: Sascha Hauer <s.hauer@pengutonix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17ARM: dts: imx6qdl-sabreauto: enable the WEIM NORHuang Shijie
Enable the WEIM NOR for imx6q{dl}-sabreauto boards. For the pin conflict with SPI NOR, its status is set to "disabled". Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17ARM: dts: imx6dl: add pinctrls for WEIM NORHuang Shijie
Add two pinctrls for WEIM: one for the weim nor, another for the chipselect. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17ARM: dts: imx6q: add pinctrls for WEIM NORHuang Shijie
Add two pinctrls for WEIM: one for the weim nor, another for the chipselect. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17ARM: dts: imx6qdl: add more information for WEIMHuang Shijie
Add the clock and compatible information for the weim. Also adds the weim label. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17ARM: dts: imx6q{dl}: fix the pin conflict between SPI and WEIMHuang Shijie
In the imx6q-sabreauto and imx6dl-sabreauto boards, the pin MX6Q{DL}_PAD_EIM_D19 is used as a GPIO for SPI NOR, but it is used as a data pin for the WEIM NOR. In order to fix the conflict, this patch removes the pin from the hog, and adds a new board-level pinctrl: pinctrl_ecspi1_sabreauto. The SPI NOR selects this pinctrl_ecspi1_sabreauto when it is enabled. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17ARM i.MX53: mba53: add DI1_CLK to pinctrl for disp1Markus Niebel
Add missing pin config Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17ARM i.MX53: mba53: fix lvds/disp pinctrlSteffen Trumtrar
use NO_PAD_CTL / 0x80000000 instead of 0x10000 to prevent misconfigured pads Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de> [Steffen: split up patch into tqma53+mba53 part] Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17ARM i.MX53: mba53: use reset gpio for FECMarkus Niebel
Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17ARM i.MX53: mba53: add missing gpio stuff for pca9554Markus Niebel
Add properties to make use of pca9554 gpio expander. Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17ARM i.MX53: mba53: add sound supportMarkus Niebel
Enable the sgtl5000 found on MBa53 mainboard. Also enable audio muxer and ssi, which are needed for sound to work. Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17ARM i.MX53: mba53: add Tevision EncoderPhilipp Zabel
Enable tve on MBa53. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17ARM i.MX53: mba53: Add display supportSascha Hauer
As the displays are optional and we have more than one, also set the status of the parallel display and the ldb to disabled. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17ARM i.MX53: mba53: enable usbotg & usbh1Michael Olbrich
Signed-off-by: Michael Olbrich <m.olbrich@pengutronix.de> Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17ARM i.MX53: tqma53: add WP/CD pinctrl and vmmc to esdhc2Steffen Trumtrar
Add WP/CD pinctrl for esdhc2. Also, add vmmc-supply for esdhc2. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17ARM i.MX53: Add TVE entry to i.MX53 dtsiPhilipp Zabel
This adds the Television Encoder (TVEv2) device tree node to the i.MX53 dtsi. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17ARM i.MX53: tqma53: rev 300 specific pin configurationPhilipp Zabel
I2S_MCLK is moved from pad GPIO19 to GPIO0, which can be muxed to the ssi_ext1 clock signal. #SYSTEM_DOWN is moved from pad GPIO0 to GPIO19. Add #PHY_RESET and LCD_CONTRAST. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17ARM i.MX53: tqma53: fix pinctrl settingsPhilipp Zabel
BIT(31) is NO_PAD_CTL, not BIT(16) Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17ARM i.MX53: tqma53: Fix interrupt polarity for the mc34708Sascha Hauer
It's active high, not active low. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17ARM: dts: imx27-phytec-phycore-som: Add initial support for PCM970 RDKAlexander Shiyan
Patch adds initial dts for Phytec PCM970 Rapid development kit. - Added definition for UART0 and UART1. - Added additional SPI chipselect which used on RDK for ZegBee module. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17ARM: dts: imx27-phytec-phycore-som: Remove UART definitionsAlexander Shiyan
UART1 and UART2 can be unused on some designs with PCM038 module. Remove these definitions from basic dts and lets choose user only necessary UARTs in custom designs. Keep UART0 for using this one as boot console, but since we have not way to disable usage RTSCTS signals, remove this parameter for UART0. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17ARM: dts: imx27-phytec-phycore: Rename file to match functionalityAlexander Shiyan
PCM038 dts can be used as base for development kit board or any custom PCB designs. Renames this file to match functionality. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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