| Age | Commit message (Collapse) | Author |
|---|
|
Printing low-level debug messages make an assumption that the specified
UART port has been preconfigured by the bootloader. Incorrectly
specified UART port results in system getting stalled while printing the
message "Uncompressing Linux... done, booting the kernel"
This UART port number is specified through S3C_LOWLEVEL_UART_PORT. Since
the UART port might different for different board, it is not possible to
specify it correctly for every board that use a common defconfig file.
Calling this print subroutine only when DEBUG_LL fixes the problem. By
disabling DEBUG_LL in default config file, we would be able to boot
multiple boards with different default UART ports.
With this current approach, we miss the print "Uncompressing Linux...
done, booting the kernel." when DEBUG_LL is not defined.
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
|
|
next/dt
From Tony Prisk, vt8500 devicetree updates for 3.11.
* tag 'vt8500/dts-3.11' of git://github.com/linux-wmt/linux-vtwm:
dts: vt8500: Correct reference clock on WM8850 SoCs
dts: vt8500: Add ARM, AHB, APB and DDR clock nodes to SoC files
dts: vt8500: Populate missing PLL nodes
dts: clk: vt8500: Update SoC dtsi to use WM8850 PLL clocks
dts: vt8500: Update serial nodes and disable by default in SoC files
dts: vt8500: Add devicetree support for WM8750 SoC and APC8750 board
dts: vt8500: Fix invalid/missing cpu nodes for soc files.
Signed-off-by: Olof Johansson <olof@lixom.net>
|
|
From Lorenzo Pieralisi, this is a series of patches that cleans up the CPU
nodes in most of the SoC dtsi files to conform to the standard bindings.
* 'dts-cpus-updates' of git://linux-arm.org/linux-2.6-lp:
ARM: dts: sunxi: cpus/cpu nodes dts updates
ARM: dts: spear: cpus/cpu nodes dts updates
ARM: dts: sh7372: cpus/cpu nodes dts updates
ARM: dts: r8a7740: cpus/cpu nodes dts updates
ARM: dts: pxa2xx: cpus/cpu nodes dts updates
ARM: dts: prima2: cpus/cpu node dts updates
ARM: dts: picoxcell: cpus/cpu nodes dts updates
ARM: dts: omap: cpus/cpu nodes dts updates
ARM: dts: lpc32xx: cpus/cpu nodes dts updates
ARM: dts: imx: cpus/cpu nodes dts updates
ARM: dts: exynos5440: cpus/cpu nodes dts updates
ARM: dts: at91: cpus/cpu node dts updates
ARM: dts: armada-370-xp: cpus/cpu node dts updates
ARM: dts: am33xx: cpus/cpu nodes dts updates
Signed-off-by: Olof Johansson <olof@lixom.net>
|
|
git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.10/fixes
More OMAP hwmod and clock fixes for v3.10-rc. Fixes the AM33xx UART2.
Also fixes some CCF-related breakage on OMAP36xx/37xx, affecting DSS
at the very least.
Basic test logs for this branch are here:
http://www.pwsan.com/omap/testlogs/fixes_b_v3.10-rc/20130606093449/
|
|
git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt into omap-for-v3.10/fixes
|
|
- The IO resource information like dma request lines, irq number and
ocp address space can be populated via dt blob. So such data is stripped
from OMAP4 SOC hwmod data file.
- The devices which are still missing the device tree bindings,
address space entries are not removed yet. When such devices add
the dt bindings, respective address space data can be deleted.
- Also other unnecessary hwmods like firewalls are removed as a part of this.
Since emif was getting registered only because of this firewalls links,
the mpu->emif direct link is added now.
The above update, results in reduction of about ~1650 lines of code.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Acked-by: Benoit Cousson <benoit.cousson@linaro.org>
Acked-by: Paul Walmsley <paul@pwsan.com>
[tony@atomide.com: updated for omap44xx_usb_phy_and_pll_addrs, dropped
mcspi and mmc changes to avoid regressions on omap4sdp]
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
|
|
|
AM33XX only supports DT boot mode and with addition of
extracting module resources like, irq, dma and address space
from DT block, so now we can remove duplicate information from
hwmod data file.
This patch cleanups-up/deletes,
- All references to "omap_hwmod_irq_info" data.
- All references to "omap_hwmod_dma_info" data.
- References to "omap_hwmod_addr_space" of the modules
for which DT node is available with required address
space information.
- For the modules where "sysc" field is not applicable,
we don't need module address space, so remove them as well.
- The hwmod like firewall etc which are not useful are also
deleted.
This cleanup gets us around ~1100 LOC of negative diff.
Patch is boot tested on AM335x-EVM along with below modules -
- Matrix-keypad
- Volume up/down keys
- Ethernet
- RTC
- WDT
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
|
The MPU initialisation on the primary core is performed in two stages, one
minimal stage to ensure the CPU can boot and a second one after
sanity_check_meminfo. As the memory configuration is known by the time we
boot secondary cores only a single step is necessary, provided the values
for DRSR are passed to secondaries.
This patch implements this arrangement. The configuration generated for the
MPU regions is made available to the secondary core, which can then use the
asm MPU intialisation code to program a complete region configuration.
This is necessary for SMP configurations without an MMU, as the MPU
initialisation is the only way to ensure that memory is specified as
'shared'.
Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
CC: Nicolas Pitre <nico@linaro.org>
|
|
Much like with the MMU, MPU initialisation is performed in two stages; the
first in the pre-C world and the 'real' initialisation during arch setup.
This patch wires in previously added MPU initialisation functions so that
the whole of memory is mapped with the appropriate region properties for
'normal' RAM (the appropriate properties depend on whether the system is
SMP).
Stub initialisation functions are added for the case that there MPU support
is not configured in to the kernel.
Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
CC: Hyok S. Choi <hyok.choi@samsung.com>
|
|
This patch adds new functions for probing and initialising the ARMv7
PMSA-compliant MPU.
These use the pre-defined and reserved MPU_PROBE_REGION for establishing
properties of the MPU, which is necessary because certain probe operations
require modifying region properties and reading back the results.
This patch also introduces a minimal sanity_check_meminfo_mpu function, that
ensures that the memory set-up passed to the kernel can be used in conjunction
with the MPU. The base address of a region must be aligned to the region size,
otherwise behavior is unpredictable and region sizes can only be specified as a
power-of-two. To simplify the satisfaction of these requirements this
implementation currently enforces that all memory is contiguous from
PHYS_OFFSET, merging banks that are contiguous but passed in separately.
The functions are added in this patch but wired in to the boot process later
in the series.
Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
CC: Hyok S. Choi <hyok.choi@samsung.com>
|
|
This patch adds initial support for using the MPU, which is necessary for
SMP operation on PMSAv7 processors because it is the only way to ensure
memory is shared. This is an initial patch and full SMP support is added
later in this series.
The setup of the MPU is performed in a way analagous to that for the MMU:
Very early initialisation before the C environment is brought up, followed
by a sanity check and more complete initialisation in C.
This patch provides the simplest possible memory region configuration:
MPU_PROBE_REGION: Reserved for probing MPU details, not enabled
MPU_BG_REGION: A 'background' region that specifies all memory strongly ordered
MPU_RAM_REGION: A single shared, cacheable, normal region for the valid RAM.
In this early initialisation code we simply map the whole of the address
space with the BG_REGION and (at least) the kernel with the RAM_REGION. The
MPU has region alignment constraints that require us to round past the end
of the kernel.
As region 2 has a higher priority than region 1, it overrides the strongly-
ordered behaviour for RAM only.
Subsequent patches will add more complete initialisation from the C-world
and support for bringing up secondary CPUs.
Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
CC: Hyok S. Choi <hyok.choi@samsung.com>
|
|
This commit adds definitions relevant to the ARM v7 PMSA compliant MPU.
The register layouts and region configuration data is made accessible to asm
as well as C-code so that it can be used in early bring-up of the MPU.
The mpu region information structs assume that the properties for the I/D side
are the same, though the implementation could be trivially extended for future
platforms where this is no-longer true.
The MPU_*_REGION defines are used for the basic, static MPU region setup.
Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
|
|
This patch adds the following definitions relevant to the PMSA:
Add SCTLR bit 17, (CR_BR - Background Region bit) to the list of CR_*
bitfields. This bit determines whether to use the architecturally defined
memory map
Add the MPUIR to the available registers when using read_cpuid macro. The
MPUIR is the MPU type register.
Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
CC:"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>
|
|
The Cortex-R series processors on Versatile Express have a different memory
map to the RS1 and CA9X4 tiles. Most of the platform difference can be
expressed in device-trees, but the UART definitions for LL_DEBUG cannot.
This patch defines the UART location for R-Series processors on
versatile-express, allowing low-level debug and output from the decompressor.
These definitions are selectable via Kconfig
Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
CC: Pawel Moll <pawel.moll@arm.com>
|
|
This patch adds processor info for ARM Ltd. Cortex-R7.
The R7 has many similarities to the A9 and though the ACTLR layout is not
identical, the bits associated with cache operations broadcasting and SMP
modes are the same for A9, A5 and R7 (Though in the A-class processors the
same bits toggle TLB-ops broadcasting as well as cache-ops)
Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
CC: Catalin Marinas <catalin.marinas@arm.com>
CC: Stephen Boyd <sboyd@codeaurora.org>
|
|
Currently CPU_V7 selects CPU_CP15_MMU, however in the case of a V7 CPU
implementing the PMSA, such as the Cortex-R7, the CP15_MMU operations are
not available. Selecting CPU_CP15_MPU is appropriate in this case.
This patch makes CPU_CP15_MMU dependent on the use of the MMU, selecting
CPU_CP15_MPU for v7 processors when !MMU is chosen.
Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
|
|
Since the merging of Will's tlb-ops branch, specifically 89c7e4b8bbb3
(ARM: 7661/1: mm: perform explicit branch predictor maintenance when required),
building SMP without CONFIG_MMU has been broken.
The local_flush_bp_all function is only called for operations related to
changing the kernel's view of memory and ASID rollover - both of which are
irrelevant to an !MMU kernel.
This patch adds a stub local_flush_bp_all() function to the other tlb
maintenance stubs and restores the ability to build an SMP !MMU kernel.
Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
|
|
Without an MMU we don't need to do any TLB maintenance. Until the addition
of 93dc68876b60 (ARM: 7684/1: errata: Workaround for Cortex-A15 erratum 798181
(TLBI/DSB operations)) building the tlb maintenance ops in smp_tlb.c worked,
though none of the contents were used.
Since that commit, however, SMP NOMMU has not been able to build. This patch
restores that ability by making the building of smp_tlb.c dependent on MMU.
Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
CC: Will Deacon <will.deacon@arm.com>
|
|
The ARM CPU suspend code can be selected even for a !CONFIG_MMU
configuration. The resulting kernel will not compile and, even if it did,
would access undefined co-processor registers when executing.
This patch fixes the v6 and v7 CPU suspend code for the nommu case.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Tested-by: Jonathan Austin <jonathan.austin@arm.com>
CC: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> (commit_signer:1/3=33%)
CC: Santosh Shilimkar <santosh.shilimkar@ti.com> (commit_signer:1/3=33%)
CC: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
|
|
nommu systems do not require any page tables, so don't try to initialise
them when bringing up secondary cores.
Signed-off-by: Will Deacon <will.deacon@arm.com>
|
|
cpu_switch_mm is a logical nop on nommu systems, so define it as such
when !CONFIG_MMU.
Signed-off-by: Will Deacon <will.deacon@arm.com>
|
|
nommu platforms do not perform address translation and therefore clearly
don't have TLBs. However, some SMP code assumes the presence of the TLB
flushing routines and will therefore fail to compile for a nommu system.
This patch defines dummy local_* TLB operations and #defines
tlb_ops_need_broadcast() as 0, therefore causing the usual ARM SMP TLB
operations to call the local variants instead.
Signed-off-by: Will Deacon <will.deacon@arm.com>
CC: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
CC: Nicolas Pitre <nico@linaro.org>
|
|
This patch adds a secondary_startup entry point to head-nommu.S so that
we can boot secondary CPUs on an SMP nommu configuration.
Signed-off-by: Will Deacon <will.deacon@arm.com>
CC: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
CC: Nicolas Pitre <nico@linaro.org>
|
|
into pm-cpufreq
ARM cpufreq updates from Viresh Kumar.
|
|
When booting the kernel, a bootloader could have left the virtual
timer ticking away, potentially generating interrupts. This could
be troublesome if the user of the virtual timer is not careful
when enabling the interrupt.
In order to avoid any surprise, stop the virtual timer from
interrupting us when booted in HYP mode, as we'll use the physical
timer in this case.
Reported-by: Giridhar Maruthy <giridhar.m@samsung.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Dave Martin <dave.martin@linaro.org>
|
|
In 8a4da6e: "arm: arch_timer: move core to drivers/clocksource", the
selection of ARM_ARCH_TIMER was indirected via HAVE_ARM_ARCH_TIMER,
though mach-exynos's selection of ARM_ARCH_TIMER was missed, and since
then mach-shmobile, mach-tegra, and mach-virt have begun selecting
ARM_ARCH_TIMER. This can lead to architected timer support erroneously
appearing to not be selected in menuconfig.
This patch fixes up the Kconfigs for those platforms to select
HAVE_ARM_ARCH_TIMER.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
|
|
Switching between reading the virtual or physical counters is
problematic, as some core code wants a view of time before we're fully
set up. Using a function pointer and switching the source after the
first read can make time appear to go backwards, and having a check in
the read function is an unfortunate block on what we want to be a fast
path.
Instead, this patch makes us always use the virtual counters. If we're a
guest, or don't have hyp mode, we'll use the virtual timers, and as such
don't care about CNTVOFF as long as it doesn't change in such a way as
to make time appear to travel backwards. As the guest will use the
virtual timers, a (potential) KVM host must use the physical timers
(which can wake up the host even if they fire while a guest is
executing), and hence a host must have CNTVOFF set to zero so as to have
a consistent view of time between the physical timers and virtual
counters.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Rob Herring <rob.herring@calxeda.com>
|
|
To use the virtual counters from the host, we need to ensure that
CNTVOFF doesn't change unexpectedly. When we change to a guest, we
replace the host's CNTVOFF, but we don't restore it when returning to
the host.
As the host sets CNTVOFF to zero, and never changes it, we can simply
zero CNTVOFF when returning to the host. This patch adds said zeroing to
the return to host path.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Christoffer Dall <cdall@cs.columbia.edu>
|
|
In order to be able to use the virtual counter in a safe way,
make sure it is initialized to zero before dropping to SVC.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Dave Martin <dave.martin@linaro.org>
|
|
Merge 'net' into 'net-next' to get the MSG_CMSG_COMPAT
regression fix.
Signed-off-by: David S. Miller <davem@davemloft.net>
|
|
marzen_init_late() should be static
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
|
|
This patch is directly accessing to PUPR4 register which can
control SDHI0 CD/WP pin pull-up setting.
It should be replaced in the future.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
|
|
Update the marzen board to use the INTC External IRQ pin driver for SMSC.
This code was originally posted by Magnus Damm as part of
"ARM: shmobile: INTC External IRQ pin driver on r8a7779"
but somehow omitted when I applied that patch.
Cc: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
|
|
The lager board has pins 1 - 4 of SW2 wired up to GPIO pins.
This patch allows access to those pins as KEYS 1 - 4 using
gpio-keys.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
|
|
The board has 3 LEDs connected to GPIOs. Add a led-gpio device to
support them.
Based on "ARM: shmobile: marzen: Add GPIO LEDs" by Laurent Pinchart.
Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
|
|
SMSC driver will try to get regulator if .config had CONFIG_REGULATOR,
and, shmobile_defconfig has it.
SMSC driver on Bock-W board will be failed if it doens't have
dummy regulator settings.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
|
|
Debug serial (= SCIF0) is connected to CN9 upper side,
and it is shared by RCAN.
This patch adds SCIF/RCAN dipswitch explanation on
comment area for developers.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
|
|
KZM9G uses an AS3711 PMIC to supply power to the CPU and the LCD backlight.
The PMIC on the board is pre-programmed to supply correct voltages to the
CPU, power supply to the backlight has to be turned on at run-time. The
latter is currently performed by a hard-coded I2C command sequence in the
board file. This patch removes the backlight hack and instead adds an I2C
device to instantiate the AS3711 MFD driver, which will add a regulator
device to dynamically adjust CPU voltages and a backlight device.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
|
|
As the kzm9d only has one smsc911x device it
may be registered as a platform device with id -1.
This allows the kzm9d board to access the smsc911x device
when CONFIG_REGULATOR (and CONFIG_REGULATOR_FIXED_VOLTAGE)
are set. The motivation for which is twofold: using regulators
seems to be generally a good thing; it will move the kzm9d defconfig
one step closer to being able to be consolidated with other
shmobile defconfigs.
An alternate but so far untested approach would be to
update the definition of dummy_supplies in board-kzm9d.c
to use "smsc911x.0" instead of "smsc911x".
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
|
|
Bock-W board will needs more board specific ioremap() method.
This patch tidyup current FPGA specific settings
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
|
|
The orignal commit 3263e09d287fbaa8a9424b5e69396599a3bbd518
(ARM: shmobile: Initial r8a73a4 SoC support V3)
put MP clock parent as EXTAL2, but its code was removed
on DIV6 clock support commit.
This patch makes it consistent.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
|
|
Conflicts:
arch/arm/mach-shmobile/Kconfig
arch/arm/mach-shmobile/include/mach/r8a7778.h
arch/arm/mach-shmobile/setup-r8a7778.c
|
|
According to the datasheet, it is not allowed to change div4 clock rates
if an earlier rate change operation is still in progress, as indicated by
a set kick bit.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
|
|
An earlier commit "ARM: shmobile: sh73a0: add support for adjusting CPU
frequency" intended to replace some clock operations only for the Z-clock,
instead it replaced them for all div4 clocks, since all div4 clocks share
the same copy of clock operations. Fix this by using a separate clock
operations structure for Z-clock.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
|
|
Break out the function sh73a0_init_delay() that now
gets called both for the C version of the code and
the DT -reference boards. This way we handle both
cases in the same way.
Allows us to boot with TWD only in the kernel configuration
for C board code. TWD is not yet enabled in the case of
DT -reference - this due to a dependency on CCF.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
|
|
This patch enables the use of the generic cpufreq-cpu0 driver on sh73a0.
Providing a regulator, a list of OPPs in DT, combined with a virtual
cpufreq-cpu0 platform device and a clock, attached to it is everything,
the cpufreq-cpu0 driver needs. The first sh73a0 platform, implementing
such CPUFreq support is kzm9g-reference.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
|
|
On SH73A0 the output of PLL0 is supplied to two dividers, feeding clock to
the CPU core and SGX. Lower CPU frequencies allow the use of lower supply
voltages and thus reduce power consumption.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
|
|
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
|
|
Both clock-r8a7740.c and clock-r8a7790.c define a div4_clks array as
non-static. Compiling support for both SoCs thus result in a symbol
redefinition. Fix it by defining the arrays as static.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
|
