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2013-08-23ARM: OMAP: TI81XX: add always-on powerdomain for TI81XXAida Mynzhasova
This patch adds alwon powerdomain support for TI81XX, which is required for stable functioning of a big number of TI81XX subsystems. Signed-off-by: Aida Mynzhasova <aida.mynzhasova@skitlab.ru> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-08-23ARM: OMAP4: clock: Lock PLLs in the right sequenceRajendra Nayak
On OMAP4 we have clk_set_rate()s being done for a few DPLL clock nodes, as part of the clock init code, since the bootloaders no longer locks these DPLLs. So we have a clk_set_rate() done for a ABE DPLL node (which inturn locks it) followed by a clk_set_rate() for the USB DPLL. With USB DPLL being in bypass, we have this parent->child relationship thats formed while the clocks get registered. dpll_abe_ck | V dpll_abe_x2_ck | V dpll_abe_m3x2_ck | V usb_hs_clk_div_ck | V dpll_usb_ck This is because usb_hs_clk_div_ck is bypass clock for dpll_usb_ck. So with this parent->child relationship in place, a clk_set_rate() on ABE DPLL results eventually in a clk_set_rate() call on USB DPLL, because CCF does a clk_change_rate() (as part of clk_set_rate()) on all downstream clocks resulting from a rate change on the top clock. So its important that we lock USB DPLL before we lock ABE DPLL. Without which we see these error logs at boot. [These error logs will not be seen if using a bootloader that locks USB DPLL] [ 0.000000] clock: dpll_usb_ck failed transition to 'locked' [ 0.000000] Division by zero in kernel. [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7 [ 0.000000] [<c001bfe8>] (unwind_backtrace+0x0/0xf4) from [<c001868c>] (show_stack+0x10/0x14) [ 0.000000] [<c001868c>] (show_stack+0x10/0x14) from [<c02deb28>] (Ldiv0+0x8/0x10) [ 0.000000] [<c02deb28>] (Ldiv0+0x8/0x10) from [<c0477030>] (clk_divider_set_rate+0x10/0x114) [ 0.000000] [<c0477030>] (clk_divider_set_rate+0x10/0x114) from [<c0476ef4>] (clk_change_rate+0x38/0xb8) [ 0.000000] [<c0476ef4>] (clk_change_rate+0x38/0xb8) from [<c0476f5c>] (clk_change_rate+0xa0/0xb8) [ 0.000000] Division by zero in kernel. [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7 [ 0.000000] [<c001bfe8>] (unwind_backtrace+0x0/0xf4) from [<c001868c>] (show_stack+0x10/0x14) [ 0.000000] [<c001868c>] (show_stack+0x10/0x14) from [<c02deb28>] (Ldiv0+0x8/0x10) [ 0.000000] [<c02deb28>] (Ldiv0+0x8/0x10) from [<c0477030>] (clk_divider_set_rate+0x10/0x114) [ 0.000000] [<c0477030>] (clk_divider_set_rate+0x10/0x114) from [<c0476ef4>] (clk_change_rate+0x38/0xb8) [ 0.000000] [<c0476ef4>] (clk_change_rate+0x38/0xb8) from [<c0476f5c>] (clk_change_rate+0xa0/0xb8) [ 0.000000] Division by zero in kernel. [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7 [ 0.000000] [<c001bfe8>] (unwind_backtrace+0x0/0xf4) from [<c001868c>] (show_stack+0x10/0x14) [ 0.000000] [<c001868c>] (show_stack+0x10/0x14) from [<c02deb28>] (Ldiv0+0x8/0x10) [ 0.000000] [<c02deb28>] (Ldiv0+0x8/0x10) from [<c0477030>] (clk_divider_set_rate+0x10/0x114) [ 0.000000] [<c0477030>] (clk_divider_set_rate+0x10/0x114) from [<c0476ef4>] (clk_change_rate+0x38/0xb8) [ 0.000000] [<c0476ef4>] (clk_change_rate+0x38/0xb8) from [<c0476f5c>] (clk_change_rate+0xa0/0xb8) [ 0.000000] Division by zero in kernel. [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7 [ 0.000000] [<c001bfe8>] (unwind_backtrace+0x0/0xf4) from [<c001868c>] (show_stack+0x10/0x14) [ 0.000000] [<c001868c>] (show_stack+0x10/0x14) from [<c02deb28>] (Ldiv0+0x8/0x10) [ 0.000000] [<c02deb28>] (Ldiv0+0x8/0x10) from [<c0477030>] (clk_divider_set_rate+0x10/0x114) [ 0.000000] [<c0477030>] (clk_divider_set_rate+0x10/0x114) from [<c0476ef4>] (clk_change_rate+0x38/0xb8) [ 0.000000] [<c0476ef4>] (clk_change_rate+0x38/0xb8) from [<c0476f5c>] (clk_change_rate+0xa0/0xb8) [ 0.000000] Division by zero in kernel. [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7 [ 0.000000] [<c001bfe8>] (unwind_backtrace+0x0/0xf4) from [<c001868c>] (show_stack+0x10/0x14) [ 0.000000] [<c001868c>] (show_stack+0x10/0x14) from [<c02deb28>] (Ldiv0+0x8/0x10) [ 0.000000] [<c02deb28>] (Ldiv0+0x8/0x10) from [<c0477030>] (clk_divider_set_rate+0x10/0x114) [ 0.000000] [<c0477030>] (clk_divider_set_rate+0x10/0x114) from [<c0476ef4>] (clk_change_rate+0x38/0xb8) [ 0.000000] [<c0476ef4>] (clk_change_rate+0x38/0xb8) from [<c0476f5c>] (clk_change_rate+0xa0/0xb8) [ 0.000000] Division by zero in kernel. [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7 [ 0.000000] [<c001bfe8>] (unwind_backtrace+0x0/0xf4) from [<c001868c>] (show_stack+0x10/0x14) [ 0.000000] [<c001868c>] (show_stack+0x10/0x14) from [<c02deb28>] (Ldiv0+0x8/0x10) [ 0.000000] [<c02deb28>] (Ldiv0+0x8/0x10) from [<c0477030>] (clk_divider_set_rate+0x10/0x114) [ 0.000000] [<c0477030>] (clk_divider_set_rate+0x10/0x114) from [<c0476ef4>] (clk_change_rate+0x38/0xb8) [ 0.000000] [<c0476ef4>] (clk_change_rate+0x38/0xb8) from [<c0476f5c>] (clk_change_rate+0xa0/0xb8) [ 0.000000] clock: trace_clk_div_ck: could not find divisor for target rate 0 for parent pmd_trace_clk_mux_ck [ 0.000000] Division by zero in kernel. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-08-23ARM: OMAP: AM33XX: hwmod: Add hwmod data for debugSSVaibhav Hiremath
In the original hwmod data file, DebugSS entry was disabled, since we didn't (and do not) have SW to control it. This patch enables it back with right data, so that it can be controlled by different ways; and the suggested method it to have modular driver for debugSS as well. Refer to the link for more discussion on handling of debugSS - https://patchwork.kernel.org/patch/2212111/ Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-08-23ARM: OMAP2+: Only write the sysconfig on idle when necessaryJon Hunter
Currently, whenever we idle a device _idle_sysc() is called and writes to the devices SYSCONFIG register to set the idle mode. A lot devices are using the smart-idle mode and so the write to the SYSCONFIG register is programming the same value that is already stored in the register. Writes to the devices SYSCONFIG register can be slow, for example, writing to the DMTIMER SYSCONFIG register takes 3 interface clock cycles and 3 functional clock cycles. If the DMTIMER is using the slow 32kHz functional clock this can take ~100us. Furthermore, during boot on an OMAP4430 panda board, I see that there are 100 calls to _idle_sysc(), however, only 3 out of the 100 calls actually write the SYSCONFIG register with a new value. Therefore, to avoid unnecessary writes to device SYSCONFIG registers when idling the device, only write the value if the value has changed. It should be safe to do this on idle as the context of the register will never be lost while the device is active. Verified that suspend, CORE off and retention states are working with this change on OMAP3430 Beagle board. Signed-off-by: Jon Hunter <jon-hunter@ti.com> [paul@pwsan.com: updated to apply] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-08-23ARM: OMAP: DRA7: Enable PM framework initializationsAmbresh K
Initialise powerdomains, clockdomains, and hwmod frameworks. Signed-off-by: Ambresh K <ambresh@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: updated to apply] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-08-23ARM: OMAP: DRA7: hwmod: Create initial DRA7XX SoC dataAmbresh K
Adding the hwmod data for DRA7XX platforms. Signed-off-by: Ambresh K <ambresh@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-08-23ARM: OMAP: DRA7: Reuse the omap44xx_restart and fix the device instanceRajendra Nayak
The omap44xx_restart used on omap4 and omap5 devices can be reused on dra7 devices as well. The device instance however is different across omap5 and dra7 as compared to omap4. So fix this for omap5 as well as dra7. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-08-23ARM: OMAP: DRA7: powerdomain: Handle missing vc/vpRajendra Nayak
DRA7 belongs to the omap4plus devices which reuse the omap4_pwrdm_operations ops for powerdomain control. DRA7 however has no VC/VP while all the earlier omap4plus devices did. So use the .pwrdm_has_voltdm() ops to pass this info on to the core. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-08-23ARM: OMAP: DRA7: powerdomain: Add DRA7XX data and update headerAmbresh K
Add the data file to describe all power domains inside the DRA7XX SoC. Signed-off-by: Ambresh K <ambresh@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: added generation notation to comments] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-08-23ARM: OMAP: DRA7: clockdomain: Add DRA7XX data and update headerAmbresh K
Add the data file to describe all clock domains inside the DRA7XX SoC Signed-off-by: Ambresh K <ambresh@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: added generation notation to comments] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-08-23ARM: OMAP: DRA7: PRCM: Add DRA7XX local MPU PRCM regsitersAmbresh K
Add the PRCM MPU registers for DRA7XX platforms Signed-off-by: Ambresh K <ambresh@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: added generation notation to comments] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-08-23ARM: OMAP: DRA7: CM: Add minimal regbit shiftsRajendra Nayak
This header contains minimal regbits that are currently used in code. This header has traditionally been autogenerated on OMAP4+ devices but the autogenerated contents are largely (95%) unused and hence to reduce unsued data in the kernel this header has been cut down (from the autogen output) to whatever is currently needed. This is done by running a cleanup script on top of the existing autogen script. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Ambresh K <ambresh@ti.com> [paul@pwsan.com: added generation notation in the comments] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-08-23ARM: OMAP: DRA7: CM: Add DRA7XX register definesAmbresh K
Add the new defines for DRA7XX CM registers. Signed-off-by: Ambresh K <ambresh@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: added generation notation in comments] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-08-23ARM: OMAP: DRA7: PRM: Add DRA7XX register definitionsAmbresh K
Add the new defines for DRA7xx prm module registers. Signed-off-by: Ambresh K <ambresh@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: added generation notation in the comments] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-08-23pinctrl: sirf: add lost atlas6 uart0-no-stream-control pingroupQipan Li
the old codes defined uart0_nostreamctrl_pins, but missed pingroup and padmux definition for it. this patch fixes it. Signed-off-by: Qipan Li <Qipan.Li@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-23ARM: at91/dt: sama5d3xek: reduce the ROM code mapping for pmecc lookup tableJosh Wu
Signed-off-by: Josh Wu <josh.wu@atmel.com>
2013-08-23ARM: at91/dt: sama5d3xek: Enable NFC support in dtsJosh Wu
Signed-off-by: Josh Wu <josh.wu@atmel.com>
2013-08-23ARM: at91/dt: sama5d3xek: remove the useless NFC dt parametersJosh Wu
The NFC driver code doesn't use atmel,has-nfc and atmel,use-nfc-sram. Signed-off-by: Josh Wu <josh.wu@atmel.com>
2013-08-22ARM: highbank: avoid L2 cache smc calls when PL310 is not presentRob Herring
While Midway firmware handles L2 smc calls as nops, the custom smc calls present a problem when running virtualized Midway guest. They aren't needed so just avoid calling them. In the process, cleanup the L2X0 ifdefs and use IS_ENABLED instead. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-08-22ARM: move outer_cache declaration out of ifdefRob Herring
Move the outer_cache declaration of the CONFIG_OUTER_CACHE ifdef so that outer_cache can be used inside IS_ENABLED condition. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Russell King <linux@arm.linux.org.uk>
2013-08-22ARM: highbank: select ARCH_DMA_ADDR_T_64BIT for LPAERob Herring
ECX-2000 has some 64-bit capable DMA and therefore needs dma_addr_t to be a 64-bit size. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-08-22Kconfig: Remove hotplug enable hints in CONFIG_KEXEC help textsGeert Uytterhoeven
commit 40b313608ad4ea655addd2ec6cdd106477ae8e15 ("Finally eradicate CONFIG_HOTPLUG") removed remaining references to CONFIG_HOTPLUG, but missed a few plain English references in the CONFIG_KEXEC help texts. Remove them, too. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Stephen Rothwell <sfr@canb.auug.org.au> Acked-by: Ingo Molnar <mingo@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-08-22Merge tag 'davinci-for-v3.12/dt' of ↵Kevin Hilman
git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/soc From Sekhar Nori: DaVinci DT updates for v3.12 ---------------------------- This set of patches add ethernet DT nodes for DA850 and also remove now unneeded specification of UART clock frequency so kernel can now boot irrespective of what the bootloader setting of UART frequency is. * tag 'davinci-for-v3.12/dt' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci: ARM: davinci: da850: do not specify clock_frequency for UART DT node ARM: davinci: da850: add DT node for ethernet ARM: davinci: da850: add OF_DEV_AUXDATA entry for davinci_emac ARM: davinci: da850: add OF_DEV_AUXDATA entry for mdio. ARM: davinci: da850: add DT node for mdio device Signed-off-by: Kevin Hilman <khilman@linaro.org>
2013-08-22Merge tag 'davinci-for-v3.12/soc' of ↵Kevin Hilman
git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/soc From Sekhar Nori: DaVinci SoC updates for v3.12 ----------------------------- This set of SoC updates contains changes to the way UART clock is handled to enabled DT-boot to obtain UART clock frequency instead of relying on DT-binding being supplied. Similarly handling of MDIO clock is fixed to make it easier to support MDIO in DT-boot. Finally there is patch to remove now unnecessary setting of wake-up capable flag for RTC. * tag 'davinci-for-v3.12/soc' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci: ARM: davinci: fix clock lookup for mdio device ARM: davinci: da8xx: remove hard coding of rtc device wakeup ARM: davinci: serial: remove davinci_serial_setup_clk() ARM: davinci: serial: get rid of davinci_uart_config ARM: davinci: da8xx: remove da8xx_uart_clk_enable ARM: davinci: uart: move to devid based clk_get Signed-off-by: Kevin Hilman <khilman@linaro.org>
2013-08-22Merge tag 'at91-dt' of git://github.com/at91linux/linux-at91 into next/dtKevin Hilman
From Nicolas Ferre: More DT work on AT91: - sound support for at91sam9x5 family - at91sam9n12: touch button, i2c and gpio-keys - adding missing pinctrl-names to MCI on at91rm9200 and at91sam9260/9g20 - adding ARM Performance Monitor Unit (PMU) on sama5d3 * tag 'at91-dt' of git://github.com/at91linux/linux-at91: ARM: at91/dt: sam9x5ek: add sound configuration ARM: at91/dt: sam9x5ek: enable SSC ARM: at91/dt: sam9x5ek: add WM8731 codec ARM: at91/dt: sam9x5: add SSC DMA parameters ARM: at91/dt: add at91rm9200 PQFP package version ARM: at91: at91rm9200: set default mmc0 pinctrl-names ARM: at91: at91sam9n12: correct pin number of gpio-key ARM: at91: at91sam9n12: add qt1070 support ARM: at91: at91sam9n12: add pinctrl of TWI ARM: at91: Add PMU support for sama5d3 ARM: at91: at91sam9260: add missing pinctrl-names on mmc Signed-off-by: Kevin Hilman <khilman@linaro.org>
2013-08-22Merge tag 'fixes-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC fixes from Olof Johansson: "A handful of fixes for 3.11 are still trickling in. These are: - A couple of fixes for older OMAP platforms - Another few fixes for at91 (lateish due to European summer vacations) - A late-found problem with USB on Tegra, fix is to keep VBUS regulator on at all times - One fix for Exynos 5440 dealing with CPU detection - One MAINTAINERS update" * tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: ARM: tegra: always enable USB VBUS regulators ARM: davinci: nand: specify ecc strength ARM: OMAP: rx51: change musb mode to OTG ARM: OMAP2: fix musb usage for n8x0 MAINTAINERS: Update email address for Benoit Cousson ARM: at91/DT: fix at91sam9n12ek memory node ARM: at91: add missing uart clocks DT entries ARM: SAMSUNG: fix to support for missing cpu specific map_io ARM: at91/DT: at91sam9x5ek: fix USB host property to enable port C
2013-08-22Merge tag 'ux500-core-for-arm-soc' of ↵Kevin Hilman
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/soc From Linus Walleij: Core ux500 changes for v3.12: - Add support for restart using the PRCMU - Move secondary startup out of INIT section - set coherent_dma_mask for DMA40 * tag 'ux500-core-for-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson: ARM: ux500: set coherent_dma_mask for dma40 ARM: ux500: remove u8500_secondary_startup from INIT section. ARM: ux500: add restart support via prcmu
2013-08-22Merge tag 'nomadik-i2c-for-arm-soc' of ↵Kevin Hilman
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into next/dt From Linus Walleij: Enables the standard Nomadik I2C driver for use on the original Nomadik instead of using a bit-banged driver. * tag 'nomadik-i2c-for-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik: ARM: nomadik: switch to use the Nomadik I2C driver Signed-off-by: Kevin Hilman <khilman@linaro.org>
2013-08-22ARM: dts: vf610-twr: enable i2c0 deviceJingchang Lu
enable i2c0 device on Vybrid VF610 Tower Board Signed-off-by: Jingchang Lu <b35083@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-22ARM: dts: i.MX51: Add one more I2C2 pinmux entryAlexander Shiyan
This adds one more I2C2 alternate pinmux entry. GPIO1_2 <=> SCL GPIO1_3 <=> SDA Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-22ARM: dts: i.MX51: Move pins configuration under "iomuxc" labelAlexander Shiyan
This unmix module/pin definitions and reduce indentation for pin groups, so makes template a bit cleaner. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-22ARM: dtsi: imx6qdl-sabresd: Add USB OTG vbus pin to pinctrl_hogPeter Chen
USB OTG vbus pin needs to be configured as gpio function at sabresd board. Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-22ARM: dtsi: imx6qdl-sabresd: Add USB host 1 VBUS regulatorPeter Chen
We enabled USB host 1, so host 1's vbus should be on to let host 1 work. Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-22ARM: dts: imx27-phytec-phycore-som: Enable AUDMUXAlexander Shiyan
Patch adds AUDMUX routing for Phytec PCM-038 module. This route i.MX SSI0 (Port 1) to the slave port 4 where MC13783 codec interface is connected. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-22ARM: dts: i.MX27: Disable AUDMUX in the templateAlexander Shiyan
AUDMUX expects additional parameters to be configured correctly, so turn it off into a template. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-22ARM: dts: wandboard: Add support for SDIO bcm4329Tony Prisk
The wandboard has a Broadcom 4329 WiFi connected via SDIO. This patch sets the required pins to enable the wifi module. Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-22ARM: i.MX5 clocks: Remove optional clock setup (CKIH1) from i.MX51 templateAlexander Shiyan
External high frequency clock CKIH1 is optional for i.MX51, so move it setup into boards where it is used. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-22ARM: dts: imx53-qsb: Make USBH1 functionalFabio Estevam
mx53qsb uses GPIO7_8 to turn on VBUS, so add support for it. Also specify the PHY type in the device tree. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Arnaud Patard <arnaud.patard@rtp-net.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-22ARM i.MX6Q: dts: Enable I2C1 with EEPROM and PMIC on Phytec phyFLEX-i.MX6 ↵Philipp Zabel
Ouad module This patch enables I2C1 and adds device tree nodes for the EEPROM and the DA9063 PMIC connected to this I2C bus. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-22ARM i.MX6Q: dts: Enable SPI NOR flash on Phytec phyFLEX-i.MX6 Ouad modulePhilipp Zabel
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-22ARM: dts: imx6qdl-sabresd: Add touchscreen supportFabio Estevam
mx6 sabresd boards have a egalax touchscreen controller connected via I2C3. Add support for it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-22ARM: imx: add ocram clock for imx53Shawn Guo
Add missing ocram gate clock for imx53 and also represent it in device tree ocram node. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-22ARM: dts: imx: ocram size is different between imx6q and imx6dlShawn Guo
The ocram on imx6q is 256 KiB while on imx6dl it's 128 KiB. Let's have separate node for imx6q and imx6dl. It also changes imx6q size 0x3f000 to 0x40000 to match the hardware. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Liu Ying <Ying.Liu@freescale.com>
2013-08-22ARM: dts: imx27-phytec-phycore-som: Fix regulator settingsAlexander Shiyan
Outputs regulator SW1A and SW1A, SW2A and SW2B are connected together, so it determined as "joined" operation for MC13783. Separate work of these outputs in this case would be wrong, so we define only one of the outputs. Additionally, define the full range of voltages for the CPU (1.2v - 1.52v). Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-22ARM: dts: i.MX27: Remove clock name from CPU nodeAlexander Shiyan
Clock name is not needed for "cpufreq-cpu0". Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-22ARM: dts: i.MX27: Increase "clock-latency" valueAlexander Shiyan
i.MX27 CPU can be clocked with a 32 kHz quartz, and not just 32768 Hz, so increase "clock-latency" value, which will ensure that we use two clock cycles on frequency change. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-22ARM: dts: i.MX27: Add label to CPU nodeAlexander Shiyan
Add a label to i.MX27 CPU node. This change allows the reuse this node in the upper levels of the DTS. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-22ARM: dts: i.MX27: Remove optional "ptp" clock source for FECAlexander Shiyan
Patch removes optional "ptp" clock source for FEC. This clock is missing in i.MX27. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-22ARM: dts: i.MX27: Using "wdog_ipg_gate" clock source for watchdogAlexander Shiyan
Patch replaces "dummy" clock source for watchdog with "wdog_ipg_gate". Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-22ARM: dts: imx6qdl-sabresd: Allow buttons to wake-up the systemFabio Estevam
This is useful for testing suspend/resume sequence. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-03-16 20:52:52 +0000