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The MOXA ART SoC is based on Faraday's FA526. This is a ARMv4 32-bit
192 MHz CPU with MMU and 16KB/8KB D/I-cache.
Add platform support for this SoC.
Also add UC-7112-LX as a machine.
Signed-off-by: Jonas Jensen <jonas.jensen@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
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Merging at91/dt as a prereq for the at91/drivers code.
* at91/dt: (43 commits)
ARM: at91/at91rm9200ek.dts: rearrange nodes in address ascending order
ARM: at91: dt: at91rm9200ek: add emac and nor flash support
ARM: at91: add uart aliases to sama5d3 dtsi
ARM: at91: add i2c2 pinctrl speficifation to sama5d3 DT
ARM: at91: Animeo IP: fix mtd partition table
ARM: at91: at91sam9g45: add i2c pinctrl
ARM: at91: at91sam9g45: set default mmc pinctrl-names
ARM: at91: sama5d3: enable qt1070 as a wakeup source
ARM: at91: add support for Cosino board series by HCE Engineering
ARM: at91/dt/sama5d3: add DMA information to SHA/AES/TDES nodes
ARM: at91/dt/trivial: before sama5d3, Atmel MPU were using at91 prefix
ARM: at91/dt/trivial: use macro for AES irq type
ARM: at91: sam9263ek: add dt lcd support
ARM: at91: at9sam9m10g45ek: add dt lcd support
ARM: at91: sam9263: add fb dt support
ARM: at91: sam9g45: add fb dt support
ARM: at91/dt: binding: add missing compatibility string in SDRAM/DDR documentation
ARM: at91/dt: binding: add precision to AIC documentation
ARM: at91/dt: add atmel,pullup-gpio to at91rm9200ek usb1 definition
ARM: at91/dt: add ethernet phy to at91rm9200ek board
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next/cleanup
From Michal Simek:
ARM: Xilinx Zynq cleanup patches for v3.14
This branch contains these fixes:
- SMP cleanups
- platform initialization cleanup
* tag 'zynq-cleanup-for-3.14' of git://git.xilinx.com/linux-xlnx:
ARM: zynq: remove unnecessary setting of cpu_present_mask
arm: zynq: Set proper GIC flags
arm: zynq: Use of_platform_populate instead of bus_probe
arm: zynq: Add support for zynq_cpu_kill function
arm: zynq: Invalidate L1 in secondary boot
arm: zynq: platsmp: Remove CPU presence check
Signed-off-by: Olof Johansson <olof@lixom.net>
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From Michal Simek:
arm: Xilinx Zynq dt patches for v3.14
- Add gem support
- Add cpus node
- TTC cleanup
* tag 'zynq-dt-for-3.14' of git://git.xilinx.com/linux-xlnx:
arm: dt: zynq: Add 'cpus' node
arm: dt: zynq: Remove 'clock-ranges' from TTC nodes
ARM: zynq: add gem support
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"Much smaller batch of fixes this week.
Biggest one is a revert of an OMAP display change that removed some
non-DT pinmux code that was still needed for 3.13 to get DSI displays
to work.
There's also a fix that resolves some misdescribed GPIO controller
resources on shmobile. The rest are mostly smaller fixes, a couple of
MAINTAINERS updates, etc"
* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
Revert "ARM: OMAP2+: Remove legacy mux code for display.c"
MAINTAINERS: Add keystone clock drivers
MAINTAINERS: Add keystone git tree information
ARM: s3c64xx: dt: Fix boot failure due to double clock initialization
ARM: shmobile: r8a7790: Fix GPIO resources in DTS
irqchip: renesas-intc-irqpin: Fix register bitfield shift calculation
ARM: shmobile: lager: phy fixup needs CONFIG_PHYLIB
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We recently sorted the nodes in dove, orion5x, kirkwood, and armada
370/xp. However, I missed this file. -6281 is fine.
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Add nodes for the two SATA PHYs on kirkwood.
Add node for the one SATA PHY on Dove.
Add pHandles to the PHYs in the sata nodes.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Add infrastructure to handle distributor and cpu interface register
accesses through the KVM_{GET/SET}_DEVICE_ATTR interface by adding the
KVM_DEV_ARM_VGIC_GRP_DIST_REGS and KVM_DEV_ARM_VGIC_GRP_CPU_REGS groups
and defining the semantics of the attr field to be the MMIO offset as
specified in the GICv2 specs.
Missing register accesses or other changes in individual register access
functions to support save/restore of the VGIC state is added in
subsequent patches.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
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The arch-generic KVM code expects the cpu field of a vcpu to be -1 if
the vcpu is no longer assigned to a cpu. This is used for the optimized
make_all_cpus_request path and will be used by the vgic code to check
that no vcpus are running.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
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Support setting the distributor and cpu interface base addresses in the
VM physical address space through the KVM_{SET,GET}_DEVICE_ATTR API
in addition to the ARM specific API.
This has the added benefit of being able to share more code in user
space and do things in a uniform manner.
Also deprecate the older API at the same time, but backwards
compatibility will be maintained.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
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Support creating the ARM VGIC device through the KVM_CREATE_DEVICE
ioctl, which can then later be leveraged to use the
KVM_{GET/SET}_DEVICE_ATTR, which is useful both for setting addresses in
a more generic API than the ARM-specific one and is useful for
save/restore of VGIC state.
Adds KVM_CAP_DEVICE_CTRL to ARM capabilities.
Note that we change the check for creating a VGIC from bailing out if
any VCPUs were created, to bailing out if any VCPUs were ever run. This
is an important distinction that shouldn't break anything, but allows
creating the VGIC after the VCPUs have been created.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
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Rework the VGIC initialization slightly to allow initialization of the
vgic cpu-specific state even if the irqchip (the VGIC) hasn't been
created by user space yet. This is safe, because the vgic data
structures are already allocated when the CPU is allocated if VGIC
support is compiled into the kernel. Further, the init process does not
depend on any other information and the sacrifice is a slight
performance degradation for creating VMs in the no-VGIC case.
The reason is that the new device control API doesn't mandate creating
the VGIC before creating the VCPU and it is unreasonable to require user
space to create the VGIC before creating the VCPUs.
At the same time move the irqchip_in_kernel check out of
kvm_vcpu_first_run_init and into the init function to make the per-vcpu
and global init functions symmetric and add comments on the exported
functions making it a bit easier to understand the init flow by only
looking at vgic.c.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
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For migration to work we need to save (and later restore) the state of
each core's virtual generic timer.
Since this is per VCPU, we can use the [gs]et_one_reg ioctl and export
the three needed registers (control, counter, compare value).
Though they live in cp15 space, we don't use the existing list, since
they need special accessor functions and the arch timer is optional.
Acked-by: Marc Zynger <marc.zyngier@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
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Initialize the cntvoff at kvm_init_vm time, not before running the VCPUs
at the first time because that will overwrite any potentially restored
values from user space.
Cc: Andre Przywara <andre.przywara@linaro.org>
Acked-by: Marc Zynger <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
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The current KVM implementation of PSCI returns INVALID_PARAMETERS if the
waitqueue for the corresponding CPU is not active. This does not seem
correct, since KVM should not care what the specific thread is doing,
for example, user space may not have called KVM_RUN on this VCPU yet or
the thread may be busy looping to user space because it received a
signal; this is really up to the user space implementation. Instead we
should check specifically that the CPU is marked as being turned off,
regardless of the VCPU thread state, and if it is, we shall
simply clear the pause flag on the CPU and wake up the thread if it
happens to be blocked for us.
Further, the implementation seems to be racy when executing multiple
VCPU threads. There really isn't a reasonable user space programming
scheme to ensure all secondary CPUs have reached kvm_vcpu_first_run_init
before turning on the boot CPU.
Therefore, set the pause flag on the vcpu at VCPU init time (which can
reasonably be expected to be completed for all CPUs by user space before
running any VCPUs) and clear both this flag and the feature (in case the
feature can somehow get set again in the future) and ping the waitqueue
on turning on a VCPU using PSCI.
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
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Make it easier to notice the common file for ChromeOS devices based on
the Exynos5250 by giving it the exynos5250 prefix that the boards have.
Signed-off-by: Mark Brown <broonie@linaro.org>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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Ensure that unused I2C controllers are not activated, causing problems due
to inappropriate pinmuxing or similar, by marking the controllers as
disabled by default and requiring boards to explicitly enable those that
are in use.
Signed-off-by: Mark Brown <broonie@linaro.org>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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Rather than requiring each board to explicitly disable the SPI controllers
it is not using instead require boards to enable those that they are using.
This is less work overall since normally at most one of the controllers is
in use and avoids issues caused by inappropriate pinmuxing.
Signed-off-by: Mark Brown <broonie@linaro.org>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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There is a 16.934MHz fixed rate clock connected to MCLK1 on the CODEC, add
this to the device tree bindings.
Signed-off-by: Mark Brown <broonie@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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Exynos5420 SoC has per core thermal management unit.
5 TMU channels 4 for CPUs and 5th for GPU.
This patch adds the device tree nodes to the DT device list.
Nodes carry the misplaced second base address and the second
clock to access the misplaced base address.
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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Commit e908d5c5 ("ARM: dts: change status property of dwmmc nodes
for exynos5250") missed out handling the exynos5250 snow dts file.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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For consistency with other device tree nodes, this patch adds missing
spaces after node labels.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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There is no need to use two cells for interrupt specifiers inside the
MCT interrupt map, so this patch simplifies the map to use one cell.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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For MCT block compatible with "samsung,exynos4412-mct", that uses PPI
interrupts for local timers, only one local interrupt needs to be
specified, since it is a per-processor interrupt.
This allows moving MCT node of Exynos4x12 SoCs back to common
exynos4x12.dtsi, since they have the same set of interrupts to be
specified, which was the only difference.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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MCT is not an interrupt controller and so there is no point for device
tree nodes representing it to contain interrupt-controller
and #interrupt-cells properties.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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Add the device-tree binding for the PWM controller to Exynos5250 and Exynos5420
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Olof Johansson <olofj@chromium.org>
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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Add SPI device tree nodes to Exynos5420 SoC
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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This patch adds dma controller node info on Exynos5420.
Exynos5420 has adma for audio IPs. As adma clk is dependent
on audss clk provider that will be added later.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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This patch removes device tree node of SDHCI0 controller and replaces
it with MSHC to enable support MMC 4.4 and improve performance of eMMC
memory.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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All SoCs from Exynos4x12 series contain the MSHC block, so its node can
be located in exynos4x12.dtsi. In addition, missing clock specifiers
are added, generic SoC attributes are moved from board dts files
to common dtsi file of SoC family and the node is renamed to a more
generic name to follow node naming recommendations.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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Clock lookup information is required as driver can manipulate
clock rate properly.
Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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The only thing exynos_pm_late_initcall() does is calling
pm_genpd_poweroff_unused(), which is already stubbed when
CONFIG_PM_GENERIC_DOMAINS is not enabled. So replace
exynos_pm_late_initcall() with a direct call to
pm_genpd_poweroff_unused().
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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Instead of repeating "select PM_GENERIC_DOMAINS" for all Exynos4
variants add relevant entry in the Kconfig section common to the
SoC series.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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The device tree sent upstream for exynos5250-snow encoded the search
key as CAPSLK. However in all ChromeOS kernels it is L_META. One can
certainly have long debates about which it ought to be, but I'm
proposing setting it to L_META because:
* That's how _all_ ChromeOS kernels do it and will do it.
* There is no L_META key on the board, so it's nice to have.
* For those people who really want it to be caps lock, they can use
xmodmap or somesuch.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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When the exynos5250 device tree was sent upstream the keyboard mapping
was missing the 2nd instance of the "\" key. There are two copies of
the "\" because it simply has a different row and column on US and
non-US keyboards.
For more details, see the previous patch in this series: (mkbp: Fix
problems with backslash).
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
From Simon Horman:
Renesas ARM based SoC DT updates for v3.14
* Global
- Use interrupt macros
- Use #include in device tree sources
- Tidyup DT node naming
* emev2 (Emma Mobile EV2) SoC
- Setup internal peripheral interrupts as level high
- Use interrupt macros in DT files
- Add clock tree description in DT
* r8a7791 (R-Car M2) SoC
- Correct GPIO resources
* r8a7791 (R-Car M2) based Koelsch board
- Configure PFC and GPO
- Use r8a7791 suffix for IRQC compat string
- Add DT reference
* r8a7790 (R-Car H2) based Lager board
- Include all 4 GiB of memory
- Use r8a7790 suffix for IRQC and MMCIF compat strings
- Enable MMCIF
- Add default PFC settings
* r8a7778 (R-Car M1) SoC
- Suffix for INTC compat string
- Add HSPI, MMCIF, SDHI and I2C suppport on DTSI
- Correct pin control device addresses
* r8a7778 (R-Car M1) based Bock-W board
- Use falling edge IRQ for LAN9221 in DT reference
- Enable I2C, HSPI0, MMCIF and SDHI
- Correct MMC pin conflict
- Remove manual PFC settings from DT reference
- Add default PFC settings
* r8a7779 (R-Car H1) SoC
- Add HSPI and SDHI support
- Suffix for INTC compat string
* r8a7779 (R-Car H1) based Marzen board
- Enable HSPI0 and SDHI in DTS
- Remove SDHI0 WP pin setting
- Use falling edge IRQ for LAN9221 in DT reference
- Add SDHI support
* r8a7740 (R-Mobile A1) SoC
- Suffix for INTC compat string
- Add FSI support via DTSI
- Use interrupt macros
* r8a7740 based Armadillo board
- Add FSI support for DTS
- Use low level IRQ for ST1231 in DT reference
* r8a73a4 (SH-Mobile APE6) SoC
- Use interrupt macros in DT files
* r8a73a4 (R-Mobile APE6) based ape6evm board
- Include all 2 GiB of memory
* r8a73a0 (SH-Mobile AG5) SoC
- Correct SDHI compat string
* r8a73a0 (SH-Mobile AG5) based kzm9d board
- Add GPIO keys and Add PCF8575 GPIO extender to DT
- Enable DSW2 with gpio-keys
- Use falling edge IRQ for LAN9221 in DT reference
* tag 'renesas-dt-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (102 commits)
ARM: shmobile: marzen: enable HSPI0 in DTS
ARM: shmobile: r8a7779: add HSPI support to DTSI
ARM: shmobile: Use r8a7779 suffix for INTC compat string
ARM: shmobile: Use r8a7778 suffix for INTC compat string
ARM: shmobile: Use r8a7740 suffix for INTC compat string
ARM: shmobile: Use sh73a0 suffix for INTC compat string
ARM: shmobile: armadillo: add FSI support for DTS
ARM: shmobile: r8a7740: add FSI support via DTSI
ARM: shmobile: emev2: Setup internal peripheral interrupts as level high
ARM: shmobile: emev2: Use interrupt macros in DT files
ARM: shmobile: Use interrupt macros in r8a73a4 and r8a7778 DT files
ARM: shmobile: Fix r8a7791 GPIO resources in DTS
ARM: shmobile: Include all 4 GiB of memory on Lager DT Ref
ARM: shmobile: Include all 4 GiB of memory on Lager
ARM: shmobile: Include all 2 GiB of memory on APE6EVM
ARM: shmobile: Include all 2 GiB of memory on APE6EVM DT Ref
ARM: shmobile: kzm9g-reference: Add GPIO keys to DT
ARM: shmobile: kzm9g-reference: Add PCF8575 GPIO extender to DT
ARM: shmobile: Koelsch DT reference GPIO LED support
ARM: shmobile: Enable DSW2 with gpio-keys on KZM9D
...
Signed-off-by: Kevin Hilman <khilman@linaro.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into fixes
From Simon Horman:
Renesas ARM based SoC fixes for v3.13
* r8a7790 (R-Car H1) SoC
- Correct GPIO resources in DT.
This problem has been present since GPIOs were added to the r8a7790 SoC
by f98e10c88aa95bf7 ("ARM: shmobile: r8a7790: Add GPIO controller
devices to device tree") in v3.12-rc1.
* irqchip renesas-intc-irqpin
- Correct register bitfield shift calculation
This bug has been present since the renesas-intc-irqpin driver was
introduced by 443580486e3b9657 ("irqchip: Renesas INTC External IRQ pin
driver") in v3.10-rc1
* Lager board
- Do not build the phy fixup unless CONFIG_PHYLIB is enabled
This problem was introduced by 48c8b96f21817aad
* tag 'renesas-fixes-for-v3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: r8a7790: Fix GPIO resources in DTS
irqchip: renesas-intc-irqpin: Fix register bitfield shift calculation
ARM: shmobile: lager: phy fixup needs CONFIG_PHYLIB
Signed-off-by: Kevin Hilman <khilman@linaro.org>
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Contrary to the rest of the keyboard, which is connected to the ChromeOS
embedded controller, the power key is hooked up to a GPIO. Add a device
tree node to handle it.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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The keyboard on Venice2 is attached to the ChromeOS embedded controller.
Add the corresponding device tree nodes and use the MATRIX_KEY define to
encode keycodes.
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
From Simon Horman:
Renesas ARM based SoC updates for v3.14
* Rename ARCH_SHMOBILE to ARCH_SHMOBILE_LEGACY
* r8a7791 SoC (R-Car M2)
- Add thermal platform device
- Add DU and LVDS clocks
- GPIO platform device support
- PFC platform device support
- Select IRQC
* r8a7790 SoC (R-Car H2)
- Tidyup clock table order
- Fixup I2C clock source
- Correct EXTAL divider settings
- Add clocks for thermal devices and SSI
* r8a7779 SoC (R-Car H1)
- Add I2C clock for DT
* r8a7778 SoC (R-Car M1)
- Add HSPI clocks for DT
- Add I2C clock for DT
- Add HPBIFx DMAEngine support
* r8a7740 SoC (R-Mobile A1)
- Add FSI clocks for DT
* emev2 SoC (Emma Mobile)
- Move to Multi-platform
- Remove legacy board code
* r7s72100 SoC (RZ/A1H)
- Select GPIO
* r8a73a4 SoC (R-Mobile APE6)
- Don't used named IRC for DMAEngine
* tag 'renesas-soc-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (33 commits)
ARM: shmobile: r8a7779: add HSPI clock support for DT
ARM: shmobile: r8a7740: add FSI clock support for DT
ARM: shmobile: r8a7790: add SSI MSTP clocks
ARM: shmobile: r8a7778: add HPBIFx DMAEngine support
ARM: shmobile: Select AUTO_ZRELADDR for EMEV2
ARM: shmobile: r8a7790: tidyup clock table order
ARM: shmobile: r8a7790: fixup I2C clock source
ARM: shmobile: r8a7790: care EXTAL divider settings
ARM: shmobile: Add r8a7791 clocks for thermal devices
ARM: shmobile: Add r8a7791 thermal platform device
ARM: shmobile: Add r8a7790 clocks for thermal devices
ARM: Rename ARCH_SHMOBILE to ARCH_SHMOBILE_LEGACY
ARM: shmobile: r8a7791: Add DU and LVDS clocks
ARM: shmobile: Select USE_OF on EMEV2
ARM: shmobile: r8a7778: add HSPI clock support for DT
ARM: shmobile: Remove legacy platform devices from EMEV2 SoC code
ARM: shmobile: Remove legacy KZM9D board code
ARM: shmobile: Use ->init_late() in shared EMEV2 case
ARM: shmobile: Add shared EMEV2 code for ->init_machine()
ARM: shmobile: Enable MTU2 on r7s72100
...
Signed-off-by: Kevin Hilman <khilman@linaro.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip
Pull Xen bugfixes from Konrad Rzeszutek Wilk:
- Fix balloon driver for auto-translate guests (PVHVM, ARM) to not use
scratch pages.
- Fix block API header for ARM32 and ARM64 to have proper layout
- On ARM when mapping guests, stick on PTE_SPECIAL
- When using SWIOTLB under ARM, don't call swiotlb functions twice
- When unmapping guests memory and if we fail, don't return pages which
failed to be unmapped.
- Grant driver was using the wrong address on ARM.
* tag 'stable/for-linus-3.13-rc4-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip:
xen/balloon: Seperate the auto-translate logic properly (v2)
xen/block: Correctly define structures in public headers on ARM32 and ARM64
arm: xen: foreign mapping PTEs are special.
xen/arm64: do not call the swiotlb functions twice
xen: privcmd: do not return pages which we have failed to unmap
XEN: Grant table address, xen_hvm_resume_frames, is a phys_addr not a pfn
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This adds the LEDs and triggers used by the Versatile boards to
the default configuration.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This should work just fine on this purely v5 platform, so let's
config it for EABI by default.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Select the GPIOLIB and PL061 in the Versatile defconfig, as this
is present on all boards, and so we get compile and test coverage
for this.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This updates the Versatile defconfig to the thing saved by
savedefconfig so we don't get confusing diffs when trying to
modify other options.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Move GPIO2 and GPIO3 to be registered from the core as this is
certainly available on Versatile AB as well, not just the PB.
GPIO2 is used for reading board status and GPIO3 is unused,
but it does not hurt to register it anyway.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This isolates the custom S3C64xx GPIO definition table to
<linux/platform_data/gpio-samsung-s3x64xx.h> as this is
used in a few different places in the kernel, removing the
need to depend on the implicit inclusion of <mach/gpio.h>
from <linux/gpio.h> and thus getting rid of a few nasty
cross-dependencies.
Also delete the CONFIG_SAMSUNG_GPIO_EXTRA stuff. Instead
roof the number of GPIOs for this platform:
First sum up all the GPIO banks from A to Q: 187 GPIOs.
Add the 16 "board GPIOs" and the roof for SAMSUNG_GPIO_EXTRA,
128, so in total maximum 187+16+128 = 331 GPIOs, so let's
take the same roof as for S3C24XX: 512. This way we can do
away with the GPIO calculation macros for GPIO_BOARD_START,
BOARD_NR_GPIOS and the definition of ARCH_NR_GPIOS.
Cc: Mark Brown <broonie@kernel.org>
[on Mini6410 board]
Tested-by: Tomasz Figa <t.figa@samsung.com>
[for changes in mach-s3c64xx]
Acked-by: Tomasz Figa <t.figa@samsung.com>
Tested-by: Mark Brown <broonie@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This isolates the custom S3C24xx GPIO definition table to
<linux/platform_data/gpio-samsung-s3x24xx.h> as this is
used in a few different places in the kernel, removing the
need to depend on the implicit inclusion of <mach/gpio.h>
from <linux/gpio.h> and thus getting rid of a few nasty
cross-dependencies.
We also delete the nifty CONFIG_S3C24XX_GPIO_EXTRA stuff.
The biggest this can ever be for the S3C24XX is
CONFIG_S3C24XX_GPIO_EXTRA = 128, and then for CPU_S3C2443 or
CPU_S3C2416 32*12 GPIOs are added, so 32*12+128 = 512
is the absolute roof value on this platform. So we set
the size of ARCH_NR_GPIO to this and the GPIOs array will
fit any S3C24XX platform, as per pattern from other archs.
ChangeLog v2->v3:
- Move the movement of the S3C64XX gpio.h file out of
this patch and into the follow-up patch where it belongs.
ChangeLog v1->v2:
- Added an #ifdef ARCH_S3C24XX around the header inclusion
in drivers/gpio/gpio-samsung.c as we would otherwise
have colliding definitions when compiling S3C64XX.
- Rename inclusion guard in the header file.
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Sylwester Nawrocki <sylvester.nawrocki@gmail.com>
Cc: Ben Dooks <ben-linux@fluff.org>
Cc: linux-samsung-soc@vger.kernel.org
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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From Santosh Shilimkar:
* keystone/soc:
ARM: keystone: defconfig: enable USB support
ARM: keystone: Avoid calling of_clk_init() twice
ARM: keystone: Make PM bus ready before populating platform devices
ARM: keystone: enable DMA zone for LPAE
ARM: keystone: enable big endian support
Signed-off-by: Kevin Hilman <khilman@linaro.org>
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