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2013-12-31ARM: imx: use __initconst for const init definitionShawn Guo
0-DAY kernel build testing backend reports the following. scripts/checkpatch.pl 0001-ARM-imx-add-support-code-for-IMX50-based-machines.patch # many are suggestions rather than must-fix ERROR: Use of const init definition must use __initconst #80: arch/arm/mach-imx/mach-imx50.c:26: +static const char *imx50_dt_board_compat[] __initdata = { While at it, fix the error globally for IMX platform. Reported-by: Fengguang Wu <fengguang.wu@intel.com> Acked-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-12-31ARM i.MX5: fix obvious typo in ldb_di0_gate clk definitionLothar Waßmann
ldb_di0_gate is registerd with the clk index of IMX5_CLK_LDB_DI1_GATE, thus the DI0 interface will be turned off inadvertently during boot. Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-12-31ARM i.MX5: set CAN peripheral clock to 24 MHz parentMarc Kleine-Budde
This patch sets the parent of CAN peripheral clock (a.k.a. CPI clock) to the lp_apm clock, which has a rate of 24 MHz. In the CAN world a base clock with multiple of 8 MHz is suited best for all CIA recommented bit rates. Without this patch the CAN peripheral clock on i.MX53 has a rate of 66.666 MHz which produces quite large bit rate errors. Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-12-31ARM: imx: pllv1: Fix PLL calculation for i.MX27Alexander Shiyan
MFN bit 9 on i.MX27 has a different meaning than in other SOCs. This is a just sign bit. This patch makes different calculation for i.MX27. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-12-31ARM i.MX5: fix "shift" value for lp_apm_sel on i.MX50 and i.MX53Marc Kleine-Budde
According to the i.MX50 Rev. 1 and i.MX53 Rev. 2.1 datasheet the lp_apm_sel is bit 10 in the CCM_CCSR register not bit 9. On the i.MX51 it's bit 9. This patch fixes this issue. Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-12-31ARM: imx: imx53: Add SATA PHY clockMarek Vasut
Add SATA PHY clock which are derived from the USB PHY1 clock. Note that this patch derives the SATA PHY clock from USB PHY1 clock gate so that the SATA driver can ungate both the SATA PHY clock and USB PHY1 clock for the SATA to work correctly. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Richard Zhu <r65037@freescale.com> Cc: Tejun Heo <tj@kernel.org> Cc: Linux-IDE <linux-ide@vger.kernel.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-12-31ARM: imx_v6_v7_defconfig: Enable STMPE touchscreenMarek Vasut
Enable STMPE touchscreen support as this is used on M53EVK. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-12-31ARM: imx: rename IMX6SL_CLK_CLK_END to IMX6SL_CLK_ENDShawn Guo
The macro name IMX6SL_CLK_CLK_END is a little insane. Rename it to IMX6SL_CLK_END. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-12-31ARM: imx: select PINCTRL at sub-architecure levelShawn Guo
Instead of selecting PINCTRL on individual SoC, let's select it at IMX sub-architecure level. While at it, it also adds the missing PINCTRL_IMX50 selection for SOC_IMX50. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-12-31ARM: imx: clk: correct arm clock usecountAnson Huang
ARM clock is sourcing from pll1_sw, and pll1_sw can be either from pll1_sys or step, so we should enable arm clock during clock initialization instead of pll1_sys, otherwise, arm clock's usecount would be incorrect and PLL1 will never be disabled even it is not used. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-12-31ARM: imx5: introduce DT includes for clock providerLucas Stach
Use clock defines in order to make devicetrees more human readable. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-12-30ARM: dts: exynos5250: Fix MDMA0 clock numberAbhilash Kesavan
Due to incorrect clock specified in MDMA0 node, using MDMA0 controller could cause system failures, due to wrong clock being controlled. This patch fixes this by specifying correct clock. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> [t.figa: Corrected commit message and description.] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2013-12-29ARM: sun4i: dt: Remove chosen nodesMaxime Ripard
The chosen nodes are nowadays pretty useless, since they will be overriden by the bootloader anyway. We can thus safely remove them. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-12-29ARM: sun4i: dt: Move the aliases to the DTSIMaxime Ripard
The aliases are shared across boards are really belong to the DTSI. Move them there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-12-29Merge tag 'renesas-soc2-for-v3.14' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc From Simon Horman: Second Round of Renesas ARM Based SoC Updates for v3.14 * Global - Add select MIGHT_HAVE_PCI for PCI-AHB bridge code * r7s72100 SoC (RZ/A1H) - clks: remove duplicated clock from r7s72100 * R-Car Gen 2: r8a7791 (R-Car M2) and r8a7790 (R-Car H2) * Initialize CCF before clock sources * Do not setup timer in non-secure mode * r8a7791 (R-Car M2) - Conditionally select MICREL_PHY - Add clock index macros for DT sources - Add Ether clock * r8a7790 (R-Car H2) - Add clock index macros for DT sources - Add I2C support * r8a7778 (R-Car M1) - Add USB Func DMAEngine support - camera-rcar header cleanup - Add SSIx DMAEngine support * sh73a0 (SH-Mobile AG5) - Add FSI clock support for DT * tag 'renesas-soc2-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: arm: shmobile: clks: remove duplicated clock from r7s72100 ARM: shmobile: koelsch: Conditionally select MICREL_PHY ARM: shmobile: rcar-gen2: Initialize CCF before clock sources ARM: shmobile: r8a7791: Add clock index macros for DT sources ARM: shmobile: r8a7790: Add clock index macros for DT sources ARM: shmobile: Add select MIGHT_HAVE_PCI for PCI-AHB bridge code ARM: shmobile: r8a7778: add USB Func DMAEngine support ARM: rcar-gen2: Do not setup timer in non-secure mode ARM: shmobile: r8a7791: add Ether clock ARM: shmobile: r8a7778: camera-rcar header cleanup ARM: shmobile: sh73a0: add FSI clock support for DT ARM: shmobile: r8a7790: add I2C support ARM: shmobile: r8a7778: add SSIx DMAEngine support Signed-off-by: Olof Johansson <olof@lixom.net>
2013-12-29Merge tag 'sunxi-clk-3.14-for-maxime' of ↵Maxime Ripard
https://bitbucket.org/emiliolopez/linux into sunxi/dt-for-3.14 Allwinner sunXi SoCs DT changes for clocks This contains the DT parts of the "[PATCH v3 00/13] clk: sunxi: add PLL5 and PLL6 support" series. It adds DT nodes for PLL4/5/6 and mod0 clocks on most sunxi platforms.
2013-12-29Merge tag 'renesas-defconfig2-for-v3.14' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/boards From Simon Horman: Second Round of Renesas ARM Based SoC Defconfig Updates for v3.14 * r7s72100 SoC (RZ/A1H) based Genmai Board - Fixup I2C device on defconfig - Add gpio regulator support on defconfig * r8a7791 (R-Car M2) based Koelsch board - Do not disable CONFIG_{INOTIFY_USER,UNIX} in defconfig - Enable CONFIG_PACKET in defconfig - Enable Ether in defconfig * r8a7740 (R-Mobile A1) based Armadillo board - Enable backlight control in defconfig * r8a7740 (R-Mobile A1) based Armadillo board - Rename ARCH_SHMOBILE to ARCH_SHMOBILE_LEGACY * tag 'renesas-defconfig2-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: koelsch: Do not disable CONFIG_{INOTIFY_USER,UNIX} in defconfig ARM: shmobile: koelsch: Enable CONFIG_PACKET in defconfig ARM: shmobile: armadillo800eva: Enable backlight control in defconfig ARM: shmobile: Koelsch: enable Ether in defconfig ARM: shmobile: genmai: Rename ARCH_SHMOBILE to ARCH_SHMOBILE_LEGACY ARM: shmobile: lager: fixup I2C device on defconfig ARM: shmobile: lager: add gpio regulator support on defconfig Signed-off-by: Olof Johansson <olof@lixom.net>
2013-12-29Merge tag 'renesas-dt2-for-v3.14' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt From Simon Horman: Second Round of Renesas ARM Based SoC DT Updates for v3.13 * r8a7791 (R-Car M2) based Koelsch board - Add GPIO keys * sh73a0 (SH-Mobile AG5) based kzm9g board - Add FSI support * tag 'renesas-dt2-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: koelsch: dts: Add gpio-keys device ARM: shmobile: kzm9g: add FSI support for DTS ARM: shmobile: sh73a0: add FSI support via DTSI Signed-off-by: Olof Johansson <olof@lixom.net>
2013-12-29Merge tag 'renesas-cleanup2-for-v3.14' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/cleanup From Simon Horman: Second Round of Renesas ARM based SoC cleanups for v3.14 * r8a7779 SoC (R-Car H1) - Remove unnecessary platform device from header file * tag 'renesas-cleanup2-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: remove unnecessary platform_device as header cleanup Signed-off-by: Olof Johansson <olof@lixom.net>
2013-12-29Merge tag 'renesas-boards-for-v3.14' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/boards From Simon Horman: Renesas ARM based SoC board updates for v3.14 * Global - Kconfig: Mention Renesas ARM SoCs instead of SH-Mobile * r7s72100 SoC (RZ/A1H) based Genmai Board - Add Multiplatform support - Add Reference DT * r8a7791 (R-Car M2) based Koelsch board - Add pinctrl_register_mappings() for Koelsch - Hook up SW30-SW36 on Koelsch - Mark GPIO keys as wake-up sources - Use ->init_late() - Add Multiplatform support - Set .debounce_interval for GPIO keys - Add SW2 to GPIO keys - Add Led 6, 7 and 8 support - Add reference DT - Enable PFC/GPIO * r8a7790 (R-Car H2) based Lager board - Add gpio/fixed regulator for SDHI - Add SPI FLASH support on QSPI - Mark GPIO keys as wake-up sources - Use ->init_late() - Set .debounce_interval for GPIO keys * r8a7778 (R-Car M1) based Bock-W board - bockw: remove unused RSND_SSI_CLK_FROM_ADG - Set .debounce_interval for GPIO keys - Correct FPGA ioremap area - Use regulator for MMCIF * r8a7740 (R-Mobile A1) based Armadillo board - Correct FSI address size * sh7374 (SH-Mobile AP4) based Mackerel board - Use pinconf API to configure pin pull-down - clk_round_rate() can return a zero to indicate an error * tag 'renesas-boards-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (75 commits) ARM: shmobile: lager: add gpio/fixed regulator for SDHI ARM: shmobile: bockw: remove unused RSND_SSI_CLK_FROM_ADG ARM: shmobile: armadillo: fixup FSI address size ARM: Kconfig: Mention Renesas ARM SoCs instead of SH-Mobile ARM: shmobile: mackerel: Use pinconf API to configure pin pull-down ARM: shmobile: Lager:add SPI FLASH support on QSPI ARM: shmobile: mackerel: clk_round_rate() can return a zero to indicate an error ARM: shmobile: Add pinctrl_register_mappings() for Koelsch ARM: shmobile: Use ->init_late() on Lager ARM: shmobile: Hook up SW30-SW36 on Koelsch ARM: shmobile: koelsch: mark GPIO keys as wake-up sources ARM: shmobile: Use ->init_late() on Koelsch ARM: shmobile: lager: mark GPIO keys as wake-up sources ARM: shmobile: r7s72100 Genmai Multiplatform ARM: shmobile: r7s72100 Genmai DT reference C bits ARM: shmobile: r7s72100 Genmai DT reference DTS bits ARM: shmobile: Initial r8a7791 and Koelsch multiplatform support ARM: shmobile: koelsch: set .debounce_interval ARM: shmobile: lager: set .debounce_interval ARM: shmobile: bockw: add pin pull-up setting for SDHI ... Signed-off-by: Olof Johansson <olof@lixom.net>
2013-12-29ARM: 7932/1: bcm: Add DEBUG_LL console supportChristian Daudt
This patch adds low level debug uart support to Broadcom mobile based SOCs. Signed-off-by: Christian Daudt <bcm@fixthebug.org> Tested-by: Markus Mayer <markus.mayer@linaro.org> Acked-by: Olof Johansson <olof@lixom.net> Tested-by: Matt Porter <mporter@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-12-29ARM: 7929/1: Remove duplicate SCHED_HRTICK config optionAxel Lin
There are two SCHED_HRTICK config entries in Kconfig. This looks like a merge mistake. Fix it. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-12-29ARM: 7928/1: kconfig: select HAVE_EFFICIENT_UNALIGNED_ACCESS for CPUv6+ && MMUWill Deacon
Modern ARM CPUs can perform efficient unaligned memory accesses in hardware and this feature is relied up on by code such as the dcache word-at-a-time name hashing. This patch selects HAVE_EFFICIENT_UNALIGNED_ACCESS for these cores and reworks the kconfig select logic for DCACHE_WORD_ACCESS to use the new symbol. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-12-29ARM: 7927/1: dcache: select DCACHE_WORD_ACCESS for big-endian CPUsWill Deacon
With commit 11ec50caedb5 ("word-at-a-time: provide generic big-endian zero_bytemask implementation"), the asm-generic word-at-a-time code now provides a zero_bytemask implementation, allowing us to make use of DCACHE_WORD_ACCESS on big-endian CPUs, providing our load_unaligned_zeropad function is endianness-clean. This patch reworks the load_unaligned_zeropad fixup code to work for both big- and little-endian CPUs, then removes the !CPU_BIG_ENDIAN check when selecting DCACHE_WORD_ACCESS. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-12-29ARM: 7926/1: mm: flesh out and fix the comments in the ASID allocatorWill Deacon
The ASID allocator has to deal with some pretty horrible behaviours by the CPU, so expand on some of the comments in there so I remember why we can never allocate ASID zero to a userspace task. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-12-29ARM: 7925/1: mm: keep track of last ASID allocation to improve bitmap searchingWill Deacon
Since we only clear entries in the ASID bitmap on a rollover event, the bitmap tends to consist of a block of consecutive set bits followed by a block of consecutive clear bits. The exception to this rule is for ASIDs which have been carried over from a previous generation, but these are bound by the number of CPUs. This patch optimises our bitmap searching strategy, so that we search from the last successful allocation, rather than search from index 1 each time we allocate a new ASID. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-12-29ARM: 7924/1: mm: don't bother with reserved ttbr0 when running with LPAEWill Deacon
With the new ASID allocation algorithm, active ASIDs at the time of a rollover event will be marked as reserved, so active mm_structs can continue to operate with the same ASID as before. This in turn means that we don't need to worry about allocating a new ASID to an mm that is currently active (installed in TTBR0). Since updating the pgd and ASID is atomic on LPAE systems (by virtue of the two being fields in the same hardware register), we can dispose of the reserved TTBR0 and rely on whatever tables we currently have live. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-12-29ARM: 7931/1: Correct virt_addr_validLaura Abbott
The definition of virt_addr_valid is that virt_addr_valid should return true if and only if virt_to_page returns a valid pointer. The current definition of virt_addr_valid only checks against the virtual address range. There's no guarantee that just because a virtual address falls bewteen PAGE_OFFSET and high_memory the associated physical memory has a valid backing struct page. Follow the example of other architectures and convert to pfn_valid to verify that the virtual address is actually valid. The check for an address between PAGE_OFFSET and high_memory is still necessary as vmalloc/highmem addresses are not valid with virt_to_page. Cc: Will Deacon <will.deacon@arm.com> Cc: Nicolas Pitre <nico@linaro.org> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Laura Abbott <lauraa@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-12-29ARM: 7923/1: mm: fix dcache flush logic for compound high pagesSteven Capper
When given a compound high page, __flush_dcache_page will only flush the first page of the compound page repeatedly rather than the entire set of constituent pages. This error was introduced by: 0b19f93 ARM: mm: Add support for flushing HugeTLB pages. This patch corrects the logic such that all constituent pages are now flushed. Cc: stable@vger.kernel.org # 3.10+ Signed-off-by: Steve Capper <steve.capper@linaro.org> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-12-29ARM: PCI: add legacy IDE IRQ implementationRussell King
The IDE code used to specify the IDE IRQs for chipsets operating in legacy mode. This appears to no longer work, and this information must be provided by the arch. Do so. This partially fixes CY82C693 (and probably others) on Footbridge platforms. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-12-29ARM: fix footbridge clockevent deviceRussell King
The clockevents code was being told that the footbridge clock event device ticks at 16x the rate which it actually does. This leads to timekeeping problems since it allows the clocksource to wrap before the kernel notices. Fix this by using the correct clock. Fixes: 4e8d76373c9fd ("ARM: footbridge: convert to clockevents/clocksource") Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Cc: <stable@vger.kernel.org>
2013-12-29ARM: footbridge: cleanup LEDs codeRussell King
Cleanup the LEDs code to use ioremap()/writeb() to access the register. This allows us to move the definitions out of a header file directly into the ebsa285 support code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-12-29ARM: pgd allocation: retry on failureRussell King
Make pgd allocation retry on failure; we really need this to succeed otherwise fork() can trigger OOMs. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-12-29ARM: footbridge: add one-shot mode for DC21285 timerRussell King
Add a one-shot mode for the DC21285 timer. This allows us to use the NO_HZ modes on this platform. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-12-29ARM: footbridge: add sched_clock implementationRussell King
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-12-29ARM: 7922/1: l2x0: add Marvell Tauros3 supportSebastian Hesselbarth
This adds support for the Marvell Tauros3 cache controller which is compatible with pl310 cache controller but broadcasts L1 cache operations to L2 cache. While updating the binding documentation, clean up the list of possible compatibles. Also reorder driver compatibles to allow non-ARM derivated to be compatible to ARM cache controller compatibles. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-12-29ARM: 7877/1: use built-in byte swap functionKim Phillips
Enable the compiler intrinsic for byte swapping on arch ARM. This allows the compiler to detect and be able to optimize out byte swappings, and has a very modest benefit on vmlinux size (Linaro gcc 4.8): text data bss dec hex filename 2840310 123932 61960 3026202 2e2d1a vmlinux-lart #orig 2840152 123932 61960 3026044 2e2c7c vmlinux-lart #builtin-bswap 6473120 314840 5616016 12403976 bd4508 vmlinux-mxs #orig 6472586 314848 5616016 12403450 bd42fa vmlinux-mxs #builtin-bswap 7419872 318372 379556 8117800 7bde28 vmlinux-imx_v6_v7 #orig 7419170 318364 379556 8117090 7bdb62 vmlinux-imx_v6_v7 #builtin-bswap Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Reviewed-by: Nicolas Pitre <nico@linaro.org> Acked-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-12-29ARM: 7921/1: mcpm: remove redundant dsb instructions prior to sevWill Deacon
sync_cache_w already includes a dsb, so we can just use sev() directly then following a cache-sync. Acked-by: Dave Martin <Dave.Martin@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-12-29ARM: 7920/1: topology: Staticise non-exported symbolsMark Brown
These symbols are only referenced in this source file so can be made static, and the efficiency table is constant data so can be declared as such. This avoids polluting the global namespace and fixes warnings from sparse. The function arch_scale_freq_power() is still not prototyped or static, this is a separate issue as this is overriding a weak symbol from the scheduler which neglects to provide a prototype. Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-12-29ARM: fix csum_tcpudp_magic() miscompilationRussell King
There is a miscompilation of csum_tcpudp_magic() due to the way we pass the asm() operands in. Fortunately, this doesn't affect the IP code, but can affect anyone who passes ntohs(udp->len) as the length argument, or protocols with more than 8 bits. The problem stems from passing 16-bit operands into an asm() - GCC makes no guarantees about what may be in the high 16-bits of such a register passed into assembly which is in the "HI" machine mode. Address this by changing the way we handle the 16-bit arguments - since accumulating the protocol and length can never overflow, we can delegate this to the compiler to perform, and then accumulate it into the checksum inside the asm(), taking account of the endian-ness via an appropriate 32-bit rotation. While we are here, also realise that there's a chance to optimise this a little: several callers from IP code pass a constant zero as the initial sum. This is wasteful - if we detect this condition, we can optimise away one instruction. Tested-by: Maxime Bizon <mbizon@freebox.fr> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-12-29ARM: 7919/1: mm: refactor v7 cache cleaning ops to use way/index sequenceLorenzo Pieralisi
Set-associative caches on all v7 implementations map the index bits to physical addresses LSBs and tag bits to MSBs. As the last level of cache on current and upcoming ARM systems grows in size, this means that under normal DRAM controller configurations, the current v7 cache flush routine using set/way operations triggers a DRAM memory controller precharge/activate for every cache line writeback since the cache routine cleans lines by first fixing the index and then looping through ways (index bits are mapped to lower physical addresses on all v7 cache implementations; this means that, with last level cache sizes in the order of MBytes, lines belonging to the same set but different ways map to different DRAM pages). Given the random content of cache tags, swapping the order between indexes and ways loops do not prevent DRAM pages precharge and activate cycles but at least, on average, improves the chances that either multiple lines hit the same page or multiple lines belong to different DRAM banks, improving throughput significantly. This patch swaps the inner loops in the v7 cache flushing routine to carry out the clean operations first on all sets belonging to a given way (looping through sets) and then decrementing the way. Benchmarks showed that by swapping the ordering in which sets and ways are decremented in the v7 cache flushing routine, that uses set/way operations, time required to flush caches is reduced significantly, owing to improved writebacks throughput to the DRAM controller. Benchmarks results vary and depend heavily on the last level of cache tag RAM content when cache is cleaned and invalidated, ranging from 2x throughput when all tag RAM entries contain dirty lines mapping to sequential pages of RAM to 1x (ie no improvement) when all tag RAM accesses trigger a DRAM precharge/activate cycle, as the current code implies on most DRAM controller configurations. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reviewed-by: Dave Martin <Dave.Martin@arm.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-12-29ARM: 7918/1: clean up cache handling in core codeNicolas Pitre
We have a handy macro to replace open coded __cpuc_flush_dcache_area(() and outer_clean_range() sequences. Let's use it. No functional change. Signed-off-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-12-29ARM: 7911/2: Clean up setup printks a bitOlof Johansson
Clean up the setup ARM printks a bit. Add printk level to a few that were missing (CPU: <...> ones, in particular), and switch from printk(KERN_* ..) to pr_*(). Finally, un-wrap some long lines since it makes it harder to grep the sources from where an error came from and tweak some cases of indentation. Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-12-29ARM: 7905/1: etm: Remove unnecessary amba_set_drvdata()Michal Simek
Driver core clears the driver data to NULL after device_release or on probe failure, so just remove it from here. Driver core change: "device-core: Ensure drvdata = NULL when no driver is bound" (sha1: 0998d0631001288a5974afc0b2a5f568bcdecb4d) Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-12-29ARM: 7890/1: v7-M: drop using mach/entry-macro.SUwe Kleine-König
The only v7-M platform only has some unused stubs in its mach/entry-macro.S file. So don't include it which allows efm32 to drop the file. Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-12-29ARM: make kernel oops easier to readRussell King
We don't need the offset for the first function name in each backtrace entry; this needlessly consumes screen space. This is virtually always the first or second instruction in the called function. Also, recognise stmfd instructions which include r10 as a valid stack saving instruction, and when dumping the registers, dump six registers per line rather than five, and fix the wrapping. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-12-29ARM: 7896/1: rename ioremap_cached to ioremap_cacheRob Herring
ioremap_cache is more aligned with other architectures. There are only 2 users of this in the kernel: pxa2xx-flash and Xen. This fixes Xen build failures on arm64 caused by commit c04e8e2fe5 (arm64: allow ioremap_cache() to use existing RAM mappings) drivers/tty/hvc/hvc_xen.c:233:2: error: implicit declaration of function 'ioremap_cached' [-Werror=implicit-function-declaration] drivers/xen/grant-table.c:1174:3: error: implicit declaration of function 'ioremap_cached' [-Werror=implicit-function-declaration] drivers/xen/xenbus/xenbus_probe.c:778:4: error: implicit declaration of function 'ioremap_cached' [-Werror=implicit-function-declaration] Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-12-28Merge tag 'v3.13-rc5' into next/boardsOlof Johansson
Need a newer base version to get a regulator fix for Samsung platforms that they enable building in a defconfig. Linux 3.13-rc5
2013-12-28Merge tag 'omap-for-v3.13/intc-ldp-fix' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes From Tony Lindgren: Fix a regression for wrong interrupt numbers for some devices after the sparse IRQ conversion, fix DRA7 console output for earlyprintk, and fix the LDP LCD backlight when DSS is built into the kernel and not as a loadable module. * tag 'omap-for-v3.13/intc-ldp-fix' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP2+: Fix LCD panel backlight regression for LDP legacy booting ARM: OMAP2+: hwmod_data: fix missing OMAP_INTC_START in irq data ARM: DRA7: hwmod: Fix boot crash with DEBUG_LL + v3.13-rc5 Signed-off-by: Olof Johansson <olof@lixom.net>
2013-12-28Merge tag 'renesas-fixes2-for-v3.13' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into fixes From Simon Horman: Second Round of Renesas ARM based SoC Fixes for v3.13 * r8a7790 (R-Car H2) based Lager board - Correct SHDI resource sizes This bug has been present since sdhi resources were added to the r8a7790 by 8c9b1aa41853272a ("ARM: shmobile: r8a7790: add MMCIF and SDHI DT templates") in v3.11-rc2. * r8a7778 (R-Car M1) based Bock-W board - Correct DMA mask This resolves a regression introduced by 4dcfa60071b3d23f ("ARM: DMA-API: better handing of DMA masks for coherent allocations") in v3.12-rc1. * r8a7740 (R-Mobile A1) based Armadillo board - Add PWM backlight power supply This resolves a regression introduced by 22ceeee16eb8f0d0 ("pwm-backlight: Add power supply support") in v3.12. * tag 'renesas-fixes2-for-v3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: r8a7790: fix shdi resource sizes ARM: shmobile: bockw: fixup DMA mask ARM: shmobile: armadillo: Add PWM backlight power supply Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Olof Johansson <olof@lixom.net>
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