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This tries to clear up the confusion between integers and iomem pointers
in the marvell pxa platform. MMIO addresses are supposed to be __iomem*
values, in order to let the Linux type checking work correctly. This
patch moves the cast to __iomem as far back as possible, to the place
where the MMIO virtual address windows are defined.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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The sharpsl code selects the max1111 spi driver, so it must also
ensure that SPI itself is enabled. The platform does not work
without max1111.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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The two platforms are part of the palm27x family and use the same
code. Select the palm27x symbol to make sure they can be built
standalone.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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Reported-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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The raumfeld platform code calls power_supply_set_battery_charged
which is part of the power supply layer, so that always has
to be enabled.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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We cannot support ARMv5 and ARMv7 based boards in a single kernel,
so introduce a new option in mach-pxa to select between the two.
The PJ4 (ARMv7) based boards are now only visible when
CONFIG_ARCH_PXA_V7 is set, the other boards are only visible
when it's not set.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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The pxa specific cpufreq code is based on the cpu_freq_table
module, so we have to select that.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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saarb uses pxa3xx_map_io and pxa3xx_handle_irq, which are part
of the pxa3xx code. This makes sure the necessary header and
implementation is used when building the board file.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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There are two variants of the palmtreo machine, the 680 and the
centro, and Kconfig allows selecting one or both of them.
This changes the board file so that it's actually possible
to build all configurations that are allowed.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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The pxa3xx_u2d_start_hc/pxa3xx_u2d_stop_hc symbols are used by the
ohci-pxa27x driver, which can be a module.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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When support for zylonite is disabled, the zylonite_pxa300_init
and zylonite_pxa320_init functions are not there, but the declaration
is still kept around if any other boards for the same soc are
enabled. This changes the declaration to be conditional on the
same symbol as the code.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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Cc: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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ARMv6 cores do not implement the DBGOSLAR register, so we don't need to
try and clear it on boot. Furthermore, the VCR is zeroed out of reset,
so we don't need to zero it explicitly when a CPU comes online.
Tested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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* pm-qos:
PM / QoS: Update Documentation for the pm_qos and dev_pm_qos frameworks
PM / QoS: Add function dev_pm_qos_read_value() (v3)
PM QoS: Add global notification mechanism for device constraints
PM QoS: Implement per-device PM QoS constraints
PM QoS: Generalize and export constraints management code
PM QoS: Reorganize data structs
PM QoS: Code reorganization
PM QoS: Minor clean-ups
PM QoS: Move and rename the implementation files
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* pm-domains:
PM / Domains: Split device PM domain data into base and need_restore
ARM: mach-shmobile: sh7372 sleep warning fixes
ARM: mach-shmobile: sh7372 A3SM support
ARM: mach-shmobile: sh7372 generic suspend/resume support
PM / Domains: Preliminary support for devices with power.irq_safe set
PM: Move clock-related definitions and headers to separate file
PM / Domains: Use power.sybsys_data to reduce overhead
PM: Reference counting of power.subsys_data
PM: Introduce struct pm_subsys_data
ARM / shmobile: Make A3RV be a subdomain of A4LC on SH7372
PM / Domains: Rename argument of pm_genpd_add_subdomain()
PM / Domains: Rename GPD_STATE_WAIT_PARENT to GPD_STATE_WAIT_MASTER
PM / Domains: Allow generic PM domains to have multiple masters
PM / Domains: Add "wait for parent" status for generic PM domains
PM / Domains: Make pm_genpd_poweron() always survive parent removal
PM / Domains: Do not take parent locks to modify subdomain counters
PM / Domains: Implement subdomain counters as atomic fields
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Based on the documents that I have here, there doesn't appear to be an
equivalent to erratum i443 for OMAP3630, so restrict this one to OMAP34xx
chips.
Also, explicitly restrict this erratum to EMU and HS devices.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
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The way that we detect which OMAP3 chips support I/O wakeup and
software I/O chain clock control is broken.
Currently, I/O wakeup is marked as present for all OMAP3 SoCs other
than the AM3505/3517. The TI81xx family of SoCs are at present
considered to be OMAP3 SoCs, but don't support I/O wakeup. To resolve
this, convert the existing blacklist approach to an explicit,
whitelist support, in which only SoCs which are known to support I/O
wakeup are listed. (At present, this only includes OMAP34xx,
OMAP3503, OMAP3515, OMAP3525, OMAP3530, and OMAP36xx.)
Also, the current code incorrectly detects the presence of a
software-controllable I/O chain clock on several chips that don't
support it. This results in writes to reserved bitfields, unnecessary
delays, and console messages on kernels running on those chips:
http://www.spinics.net/lists/linux-omap/msg58735.html
Convert this test to a feature test with a chip-by-chip whitelist.
Thanks to Dave Hylands <dhylands@gmail.com> for reporting this problem
and doing some testing to help isolate the cause. Thanks to Steve
Sakoman <sakoman@gmail.com> for catching a bug in the first version of
this patch. Thanks to Russell King <linux@arm.linux.org.uk> for
comments.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Dave Hylands <dhylands@gmail.com>
Cc: Steve Sakoman <sakoman@gmail.com>
Tested-by: Steve Sakoman <sakoman@gmail.com>
Cc: Russell King - ARM Linux <linux@arm.linux.org.uk>
Signed-off-by: Kevin Hilman <khilman@ti.com>
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The context lost count is modified in omap_sram_idle() path when
pwrdm_post_transition() is called. But pwrdm_post_transition() is called
only after omap_gpio_resume_after_idle() is called. Correct this so that
context lost count is modified before calling omap_gpio_resume_after_idle().
This would be useful when OMAP GPIO save/restore context is called by
the OMAP GPIO driver itself.
Signed-off-by: Charulatha V <charu@ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
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into next/devel
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This helps resolve the conflicts between the imx cleanups and the
new code that has gone into the imx tree.
Conflict resolution was originally done by Sascha Hauer.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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While suspending, we're enabling a clock in ->suspend() but we're in atomic
context, leading to this :
[30803.667305] PM: late suspend of devices complete after 1.237 msecs
[30803.667449] BUG: sleeping function called from invalid context at kernel/mutex.c:271
[30803.667464] in_atomic(): 0, irqs_disabled(): 128, pid: 4941, name: pm-suspend
[30803.667474] INFO: lockdep is turned off.
[30803.667483] irq event stamp: 0
[30803.667489] hardirqs last enabled at (0): [< (null)>] (null)
[30803.667503] hardirqs last disabled at (0): [<c001e4a8>] copy_process.part.48+0x1e0/0xa7c
[30803.667543] softirqs last enabled at (0): [<c001e4a8>] copy_process.part.48+0x1e0/0xa7c
[30803.667562] softirqs last disabled at (0): [< (null)>] (null)
[30803.667574] Backtrace:
[30803.667611] [<c0010e00>] (dump_backtrace+0x0/0x110) from [<c0424c00>] (dump_stack+0x18/0x1c)
[30803.667624] r6:00000000 r5:00000000 r4:d9648000 r3:d9648000
[30803.667652] [<c0424be8>] (dump_stack+0x0/0x1c) from [<c0424eec>] (__might_sleep.part.101+0x90/0xa8)
[30803.667673] [<c0424e5c>] (__might_sleep.part.101+0x0/0xa8) from [<c001a5c4>] (__might_sleep+0x80/0x94)
[30803.667686] r4:c05d58c0
[30803.667705] [<c001a544>] (__might_sleep+0x0/0x94) from [<c043230c>] (mutex_lock_nested+0x2c/0x30c)
[30803.667735] [<c04322e0>] (mutex_lock_nested+0x0/0x30c) from [<c0017834>] (clk_enable+0x28/0x50)
[30803.667747] r8:c0438464 r7:00000003 r6:00000000 r5:00000000 r4:c05d2e98
[30803.667780] [<c001780c>] (clk_enable+0x0/0x50) from [<c0017260>] (mx5_suspend_enter+0x1c/0x98)
[30803.667792] r4:00000003 r3:c060dfe0
[30803.667821] [<c0017244>] (mx5_suspend_enter+0x0/0x98) from [<c0059b48>] (suspend_enter+0xec/0x15c)
[30803.667833] r4:00000003 r3:c0017244
[30803.667856] [<c0059a5c>] (suspend_enter+0x0/0x15c) from [<c0059c4c>] (suspend_devices_and_enter+0x94/0x130)
[30803.667868] r6:00000000 r5:00000003 r4:c0c0af00 r3:00002710
[30803.667897] [<c0059bb8>] (suspend_devices_and_enter+0x0/0x130) from [<c0059db0>] (enter_state+0xc8/0x130)
[30803.667909] r6:00000000 r5:00000003 r4:c05286e4
[30803.667934] [<c0059ce8>] (enter_state+0x0/0x130) from [<c00592d4>] (state_store+0xac/0xc0)
[30803.667945] r6:00000003 r5:00000003 r4:df39d000 r3:00000003
[30803.667978] [<c0059228>] (state_store+0x0/0xc0) from [<c01b0100>] (kobj_attr_store+0x1c/0x28)
[30803.668009] [<c01b00e4>] (kobj_attr_store+0x0/0x28) from [<c00e435c>] (sysfs_write_file+0x88/0xbc)
[30803.668032] [<c00e42d4>] (sysfs_write_file+0x0/0xbc) from [<c0091fa0>] (vfs_write+0xbc/0x138)
[30803.668051] [<c0091ee4>] (vfs_write+0x0/0x138) from [<c0092204>] (sys_write+0x44/0x70)
[30803.668062] r8:00000000 r7:00000004 r6:00000003 r5:002694d0 r4:d966acc0
[30803.668094] [<c00921c0>] (sys_write+0x0/0x70) from [<c000db00>] (ret_fast_syscall+0x0/0x3c)
[30803.668106] r9:d9648000 r8:c000dcc4 r6:00000001 r5:002694d0 r4:00000003
[30803.669927] PM: early resume of devices complete after 0.972 msecs
Just move the clk_enable/disable in ->prepare() and ->finish()
Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
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Defconfig file for at91sam9g45 SoC family:
at91sam9g45, at91sam9g46, at91sam9m10, at91sam9m11.
The Atmel Evaluation Kit for this family is the at91sam9m10g45ek.
It is so useful for automatic compile tests...
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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This applies ARM errata fix 754322 for all ux500 platforms.
Cc: stable@kernel.org
Signed-off-by: srinidhi kasagar <srinidhi.kasagar@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Signed-off-by: Richard Zhu <richard.zhu@linaro.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Richard Zhu <richard.zhu@linaro.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Richard Zhu <richard.zhu@linaro.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Richard Zhu <richard.zhu@linaro.org>
Tested-by: Hector Oron Martinez <hector.oron@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Removing modules iva, sr1_hwmod, sr2_hwmod, mailbox from
the base omap3xxx_hwmods list, so that they can be excluded
for am35x. This removes quite a few warnings on boot for AM35x.
Signed-off-by: Abhilash K V <abhilash.kv@ti.com>
[paul@pwsan.com: dropped 'mailbox class' comments; updated changelog]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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Fix the shift and mask macros for DSIx_PPID fields in CONTROL_DSIPHY. The
OMAP4430 Public TRM vV has these fields mentioned correctly.
Signed-off-by: Archit Taneja <archit@ti.com>
Acked-by: Benoit Cousson <b-cousson@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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The OMAP36xx and OMAP4xxx DPLLs have a different internal reference
clock frequency (fint) operating range than OMAP3430. Update the
dpll_test_fint() function to check for the correct frequency ranges
for OMAP36xx and OMAP4xxx.
For OMAP36xx and OMAP4xxx devices, DPLLs fint range is 0.5MHz to
2.5MHz for j-type DPLLs and otherwise it is 32KHz to 52MHz for all
other DPLLs.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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The parent clock of the OCP_ABE_ICLK is the AESS_FCLK and the
parent clock of the AESS_FCLK is the ABE_FCLK...
ABE_FCLK --> AESS_FCLK --> OCP_ABE_ICLK
The AESS_FCLK and OCP_ABE_ICLK clocks both have dividers which
determine their operational frequency. However, the dividers for
the AESS_FCLK and OCP_ABE_ICLK are controlled via a single bit,
which is the CM1_ABE_AESS_CLKCTRL[24] bit. When this bit is set to
0, the AESS_FCLK divider is 1 and the OCP_ABE_ICLK divider is 2.
Similarly, when this bit is set to 1, the AESS_FCLK divider is 2
and the OCP_ABE_ICLK is 1.
The above relationship between the AESS_FCLK and OCP_ABE_ICLK
dividers ensure that the OCP_ABE_ICLK clock is always half the
frequency of the ABE_CLK...
OCP_ABE_ICLK = ABE_FCLK/2
The divider for the OCP_ABE_ICLK is currently missing so add a
divider that will ensure the OCP_ABE_ICLK frequency is always half
the ABE_FCLK frequency.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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OMAP4460 specific clocks are not getting added as the
cpu_is_omap44xx is choosing only OMAP4430 specific clock nodes.
Changing it to add to OMAP4460 specific clocks also.
This is clocks are required of temperature sensor.
Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Cc: paul@pwsan.com
[paul@pwsan.com: updated to apply]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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This is a continuation of Mike Turquette's patch "OMAP3+: use
DPLL's round_rate when setting rate".
omap3_noncore_dpll_set_rate() and omap3_noncore_dpll_enable() call
omap2_get_dpll_rate() explicitly. It may be necessary for some
DPLLs to use a different function and so use the DPLLs recalc()
function pointer instead.
An example is the DPLL_ABE on OMAP4 which can have a 4X multiplier
in addition to the usual MN multipler and dividers and therefore
uses a different round_rate and recalc function.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Cc: Mike Turquette <mturquette@ti.com>
Cc: Misael Lopez Cruz <misael.lopez@ti.com>
[paul@pwsan.com: merged this patch with Mike's "use clock's recalc in DPLL
handling" patch; also reported by Misael]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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The rounded rate can differ from target rate, so to better reflect
reality set clk->rate equal to the rounded rate when setting DPLL frequency.
This avoids issues where the DPLL frequency is slightly different than what
debugfs clock tree reports using the old target rate.
An example of a clock that requires this is DPLL_ABE on OMAP4 which
can have a 4x multiplier on top of the usual MN dividers depending on
register settings. This requires a special round_rate function that
might yield a rate different from the initial target.
Signed-off-by: Mike Turquette <mturquette@ti.com>
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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omap3_noncore_dpll_set_rate uses omap2_dpll_round_rate explicitly. Instead
use the struct clk pointer's round_rate function to allow for DPLL's with
special needs.
An example of a clock that requires this is DPLL_ABE on OMAP4 which
can have a 4x multiplier on top of the usual MN dividers depending on
register settings. This requires a special round_rate function that
might yield a rate different from the initial target.
Signed-off-by: Mike Turquette <mturquette@ti.com>
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
[paul@pwsan.com: split rate assignment portion into a separate patch]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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OMAP4 DPLL_ABE can enable a 4X multipler on top of the normal MN multipler
and divider. This is achieved by setting CM_CLKMODE_DPLL_ABE.DPLL_REGM4XEN
bit in CKGEN module of CM1. From the OMAP4 TRM:
Fdpll = Fref x 2 x (4 x M/(N+1)) in case REGM4XEN bit field is set (only
applicable to DPLL_ABE).
Add new round_rate() and recalc() functions for OMAP4, that check the
setting of REGM4XEN bit and handle this appropriately. The new functions
are a simple wrapper on top of the existing omap2_dpll_round_rate() and
omap2_dpll_get_rate() functions to handle the REGM4XEN bit.
The REGM4XEN bit is only implemented for the ABE DPLL on OMAP4 and so
only dpll_abe_ck uses omap4_dpll_regm4xen_round_rate() and
omap4_dpll_regm4xen_recalc() functions.
Signed-off-by: Mike Turquette <mturquette@ti.com>
Tested-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
[paul@pwsan.com: fixed attempt to return a negative from a fn returning
unsigned; pass along errors from omap2_dpll_round_rate();
added documentation; added Jon's S-o-b]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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Cc: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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There's no file named "drivers/char/bcmring/Kconfig". It seems it has
never been part of the mainline kernel tree. So there's nothing to be
sourced here.
Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
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With LPAE, the physical address mask is 40-bit while the page table
entry is 64-bit. This patch introduces PHYS_MASK for the 2-level page
table format, defined as ~0UL.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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This patch defines the (pte|pmd)val_t as u32 and changes the page table
types to be based on these. The PMD bits are converted to the
corresponding type using the _AT macro.
The flush_pmd_entry/clean_pmd_entry argument was changed to (void *) to
allow them to be used with both PGD and PMD pointers and avoid code
duplication.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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This patch moves page table definitions from asm/page.h, asm/pgtable.h
and asm/ptgable-hwdef.h into corresponding *-2level* files.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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This patch cleans up the Samsung resources in plat-samsung/devs.c
by using defined helpers at <linux/ioport.h>.
Cc: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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This patch merges each dev files to one devs.c file in
plat-samsung directory and this help to keep it more
easily to reduce plat- directories such as plat-s3c24xx
and plat-s5p.
Cc: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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This patch moves regarding s5p dev files to one devs.c file
in plat-samsung directory and this help to keep it more
easily.
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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This patch moves regarding s3c64xx dev files to one devs.c
file in plat-samsung directory and this help to keep it more
easily.
Cc: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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