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2012-05-09OMAPDSS: DSI: implement generic DSI pin configTomi Valkeinen
In preparation for device tree, this patch changes how the DSI pins are configured. The current configuration method is only doable with board files and the configuration data is OMAP specific. This patch moves the configuration data to the panel's platform data, and the data can easily be given via DT in the future. The configuration data format is also changed to a generic one which should be suitable for all platforms. The new format is an array of pin numbers, where the array items start from clock + and -, then data1 + and -, and so on. For example: { 0, // pin num for clock lane + 1, // pin num for clock lane - 2, // pin num for data1 lane + 3, // pin num for data1 lane - ... } The pin numbers are translated by the DSI driver and used to configure the hardware appropriately. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
2012-05-09OMAPDSS: Taal: move reset gpio handling to taal driverTomi Valkeinen
The reset GPIO for Taal panel driver is currently requested in the 4430sdp board file. This patch moves the gpio request/free into the Taal driver, where it should be. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
2012-05-09OMAPDSS: TFP410: rename dvi files to tfp410Tomi Valkeinen
Now that the tfp410 driver has been renamed in the code, this patch finishes the renaming by renaming the files. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
2012-05-09OMAPDSS: TFP410: rename dvi -> tfp410Tomi Valkeinen
The driver for the TFP410 DPI-to-DVI chip was named quite badly as "DVI panel driver". This patch renames the code to use tfp410 name for the driver. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
2012-05-09OMAP: board-files: remove custom PD GPIO handling for DVI outputTomi Valkeinen
Now that the panel-dvi driver handles the PD (power-down) GPIO, we can remove the custom PD handling from the board files. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
2012-05-09ARM i.MX: remove now unused clock filesSascha Hauer
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2012-05-09ARM: i.MX6: implement clocks using common clock frameworkShawn Guo
Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2012-05-09ARM i.MX35: implement clocks using common clock frameworkSascha Hauer
This patch also adds the SPDIF baud clock mux and dividers. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2012-05-09ARM i.MX5: implement clocks using common clock frameworkSascha Hauer
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2012-05-08ARM: OMAP4: hsmmc: check for null pointerBalaji T K
platform_device pdev can be NULL if CONFIG_MMC_OMAP_HS is not set. Add check for NULL pointer. while at it move the duplicated functions to omap4-common.c Fixes the following boot crash seen with omap4sdp and omap4panda when MMC is disabled. Unable to handle kernel NULL pointer dereference at virtual address 0000008c pgd = c0004000 [0000008c] *pgd=00000000 Internal error: Oops: 5 [#1] SMP ARM Modules linked in: CPU: 0 Not tainted (3.4.0-rc1-05971-ga4dfa82 #4) PC is at omap_4430sdp_init+0x184/0x410 LR is at device_add+0x1a0/0x664 Signed-off-by: Balaji T K <balajitk@ti.com> Reported-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2012-05-08ARM: OMAP1: fix compilation issue in board-sx1.cArtem Bityutskiy
SX1 board requirese i2c, so select it in Kconfig, otherwise I have the following build error: arch/arm/mach-omap1/board-sx1.c: In function 'sx1_i2c_write_byte': arch/arm/mach-omap1/board-sx1.c:58:2: error: implicit declaration of function 'i2c_get_adapter' [-Werror=implicit-function-declaration] arch/arm/mach-omap1/board-sx1.c:58:7: warning: assignment makes pointer from integer without a cast [enabled by default] arch/arm/mach-omap1/board-sx1.c:67:2: error: implicit declaration of function 'i2c_transfer' [-Werror=implicit-function-declaration] arch/arm/mach-omap1/board-sx1.c:68:2: error: implicit declaration of function 'i2c_put_adapter' [-Werror=implicit-function-declaration] arch/arm/mach-omap1/board-sx1.c: In function 'sx1_i2c_read_byte': arch/arm/mach-omap1/board-sx1.c:82:7: warning: assignment makes pointer from integer without a cast [enabled by default] cc1: some warnings being treated as errors make[1]: *** [arch/arm/mach-omap1/board-sx1.o] Error 1 make: *** [arch/arm/mach-omap1] Error 2 make: *** Waiting for unfinished jobs.... Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2012-05-08OMAP4: devices: Do not create mcpdm device if the dtb has been providedPeter Ujfalusi
If dtb is provided the needed device will be created dynamically. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2012-05-08OMAP4: devices: Do not create dmic device if the dtb has been providedPeter Ujfalusi
If dtb is provided the needed device will be created dynamically. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2012-05-08ARM: Kirkwood: Replace clock gatingAndrew Lunn
Add a varient of the basic clk-gate code. This variant calls a function before gating the clock off. This function is used to disable the SATA or PCIe PHY. Now that all the drivers prepare and enable there clk as needed, there is no need for the common code to keep track of which clocks need gating on. Let the common clock framework turn off clocks which are not used. Buy using the added clk varient, when the clk framework turns off SATA or PCIe clocks, we also disabled SATA and PCIe PHYs which were not needed. The function kirkwood_pcie_id() can now be called outside of __init code, so remove this property for it, and functions it calls. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Jamie Lentin <jm@lentin.co.uk> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-05-08ARM: Orion: Audio: Add clk/clkdev supportAndrew Lunn
Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Jamie Lentin <jm@lentin.co.uk> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-05-08ARM: Orion: PCIE: Add support for clkAndrew Lunn
Prepare and enable the clocks when the board indicates the pcie buses will be used. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Jamie Lentin <jm@lentin.co.uk> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-05-08ARM: Orion: XOR: Add support for clkAndrew Lunn
Some orion platforms can gate the XOR driver clock. If the clock exisits, unable/disable it as appropriate. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Jamie Lentin <jm@lentin.co.uk> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-05-08ARM: Orion: CESA: Add support for clkAndrew Lunn
Some orion platforms support gating of the clock. If the clock exists enable/disbale it as appropriate. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Jamie Lentin <jm@lentin.co.uk> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-05-08ARM: Orion: SDIO: Add support for clk.Andrew Lunn
Some orion devices can gate the SDIO clock. If the clock exists, enable/disable it as appropriate. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Jamie Lentin <jm@lentin.co.uk> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-05-08ARM: Orion: NAND: Add support for clk, if there is one.Andrew Lunn
Not all orion platforms can gate the clock, but if it does exist, enable/disable it as appropriate. v2: Fix the name of the clkdev entry. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Jamie Lentin <jm@lentin.co.uk> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-05-08ARM: Orion: EHCI: Add support for enabling clocksAndrew Lunn
Not all platforms support gating the clock, so it is not an error if the clock does not exist. However, if it does exist, we should enable/disable it as appropriate. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Jamie Lentin <jm@lentin.co.uk> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-05-08ARM: Orion: SATA: Add per channel clk/clkdev support.Andrew Lunn
The Orion kirkwood chips have a gatable clock per SATA channel. Add code to get and enable this clk if it exists. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Jamie Lentin <jm@lentin.co.uk> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-05-08ARM: Orion: UART: Get the clock rate via clk_get_rate().Andrew Lunn
Let the machine pass to the platform which clock is used by the uart. Enable the clock and use clk_get_rate() to determine its rate. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Jamie Lentin <jm@lentin.co.uk> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-05-08ARM: Orion: WDT: Add clk/clkdev supportAndrew Lunn
Remove tclk from platform data. This makes the platform data structure empty, so remove it. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Jamie Lentin <jm@lentin.co.uk> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-05-08ARM: Orion: Eth: Add clk/clkdev support.Andrew Lunn
The t_clk is moved from the shared part of the ethernet driver into the per port section. Each port can have its own gated clock, which it needs to enable/disable, as oppossed to there being one clock shared by all ports. In practice, only kirkwood supports this at the moment. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Jamie Lentin <jm@lentin.co.uk> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-05-08ARM: Orion: SPI: Add clk/clkdev support.Andrew Lunn
Remove now redundant tclk from SPI platform data. This makes the platform data empty, so remove it. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Jamie Lentin <jm@lentin.co.uk> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-05-08ARM: Orion: Add clocks using the generic clk infrastructure.Andrew Lunn
Add tclk as a fixed rate clock for all platforms. In addition, on kirkwood, add a gated clock for most of the clocks which can be gated. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Jamie Lentin <jm@lentin.co.uk> [mturquette@linaro.org: removed redundant CLKDEV_LOOKUP from Kconfig] [mturquette@linaro.org: removed redundant clk.h from mach-dove/common.c] Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-05-08ARM: OMAP2+: WDTIMER integration: fix !PM boot crash, disarm timer after ↵Kevin Hilman
hwmod reset Without runtime PM enabled, hwmod needs to leave all IP blocks in an enabled state by default so any driver access to the HW will succeed. This is accomplished by seting the postsetup_state to enabled for all hwmods during init when runtime PM is disabled. Currently, we have a special case for WDT in that its postsetup_state is always set to disabled. This is done so that the WDT is disabled and the timer is disarmed at boot in case there is no WDT driver. This also means that when runtime PM is disabled, if a WDT driver *is* built in the kernel, the kernel will crash on the first access to the WDT hardware. We can't simply leave the WDT module enabled, because the timer is armed by default after reset. That means that if there is no WDT driver initialzed or loaded before the timer expires, the kernel will reboot. To fix this, a custom reset method is added to the watchdog class of omap_hwmod. This method will *always* disarm the timer after hwmod reset. The WDT timer then will only be rearmed when/if the driver is loaded for the WDT. With the timer disarmed by default, we no longer need a special-case for the postsetup_state of WDT during init, so it is removed. Any platforms wishing to ensure the watchdog remains armed across the entire boot boot can simply disable the reset-on-init feature of the watchdog hwmod using omap_hwmod_no_setup_reset(). Tested on 3530/Overo, 4430/Panda. NOTE: on 4430, the hwmod OCP reset does not seem to rearm the timer as documented in the TRM (and what happens on OMAP3.) I noticed this because testing the HWMOD_INIT_NO_RESET feature with no driver loaded, I expected a reboot part way through the boot, but did not see a reboot. Adding some debug to read the counter, I verified that right after OCP softreset, the counter is not firing. After writing the magic start sequence, the timer starts counting. This means that the timer disarm sequence added here does not seem to be needed for 4430, but is technically the correct way to ensure the timer is disarmed, so it is left in for OMAP4. Special thanks to Paul Walmsley for helping brainstorm ideas to fix this problem. Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Kevin Hilman <khilman@ti.com> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> [paul@pwsan.com: updated the omap2_wd_timer_reset() function in the wake of commit 3c55c1baffa5f719eb2ae9729088bc867f972f53 ("ARM: OMAP2+: hwmod: Revert "ARM: OMAP2+: hwmod: Make omap_hwmod_softreset wait for reset status""); added kerneldoc; rolled in warning fix from Kevin] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-05-08ARM: OMAP2/3: hwmod data: Add 32k-sync timer data to hwmod databaseVaibhav Hiremath
Add 32k-sync timer hwmod-data and add ocp_if details to omap2 & 3 hwmod table. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Benoit Cousson <b-cousson@ti.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-05-08ARM: OMAP4: hwmod_data: Name the common irq for McBSP portsPeter Ujfalusi
Use 'common' as name for the common irq number in hwmod data for the McBSP ports. The same name already in use for OMAP2430, and OMAP3. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-05-08ARM: OMAP4: hwmod data: I2C: add flag for context restoreShubhrajyoti D
Restore of context is not done for OMAP4. This patch adds the OMAP_I2C_FLAG_RESET_REGS_POSTIDLE in the OMAP4 hwmod data which activates the restore for OMAP4. Currently the OMAP4 does not hit device off still the driver may have support for it. Cc: Benoit Cousson <b-cousson@ti.com> Cc: Paul Wamsley <paul@pwsan.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-05-08ARM: OMAP3: hwmod_data: Rename the common irq for McBSP portsPeter Ujfalusi
Use 'common' as name for the common irq number in hwmod data for the McBSP ports. The same name already in use for OMAP2430, and the OMAP4 hwmod data will be using the same name. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-05-08ARM: OMAP2xxx: hwmod data: add HDQ/1-wire hwmodPaul Walmsley
Add the HDQ1W hwmod for all OMAP2xxx devices. Assume that OMAP2xxx chips have the same HDQ idle handling bug as OMAP3: http://www.spinics.net/lists/linux-omap/msg63576.html and set the OCPIF_SWSUP_IDLE flag accordingly on the HDQ's OCP interface. Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-05-08ARM: OMAP3: hwmod data: add HDQ/1-wire hwmodPaul Walmsley
Add the HDQ1W hwmod for OMAP34xx, OMAP36xx, and AM3505/3517 devices. According to the respective TRMs, it doesn't appear to be available for the 816x/814x or the AM335x. The OCPIF_SWSUP_IDLE flag is added to work around an apparent hardware bug: the hardware is not taking the CM_FCLKEN*_CORE.EN_HDQ bit into account when considering whether to go idle: http://www.spinics.net/lists/linux-omap/msg63576.html This causes HDQ transfers to fail or become corrupt. Thanks to NeilBrown for his help diagnosing and testing fixes for this problem. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: NeilBrown <neilb@suse.de> Tested-by: NeilBrown <neilb@suse.de>
2012-05-08ARM: OMAP2+: hwmod data: add HDQ/1-wire hwmod shared dataPaul Walmsley
Much of the HDQ1W integration data is common between multiple generations of OMAP SoCs, so rather than make several copies, we add it once into files which are compiled for multiple SoCs. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: NeilBrown <neilb@suse.de> Tested-by: NeilBrown <neilb@suse.de>
2012-05-08ARM: OMAP2+: HDQ1W: add custom reset functionPaul Walmsley
Implement a custom reset function for the HDQ1W IP block. This is because the HDQ1W IP block, like I2C, has an internal clock gating bit that needs to be toggled after setting the SOFTRESET bit to allow the reset to propagate. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: NeilBrown <neilb@suse.de> Cc: Avinash.H.M <avinashhm@ti.com> Tested-by: NeilBrown <neilb@suse.de>
2012-05-08ARM: OMAP2420: hwmod data: Add MMC hwmod data for 2420Tony Lindgren
Add MMC for 2420 so we can pass the DMA request lines the same way as we already do on omap2430 and later. Cc: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> [paul@pwsan.com: updated to apply on top of the 3.5 hwmod cleanup; changed mmc hwmod name/class to "msdi" as documented in the 2420 TRM Rev X; added sysconfig register information; added 16 bit register width flag; added MSDI custom reset code] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-05-08ARM: tegra: Add SMMU enabler in AHBHiroshi DOYU
Add extern func, "tegra_ahb_enable_smmu()" to inform AHB that SMMU is ready. Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Cc: Felipe Balbi <balbi@ti.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-05-08ARM: tegra: Add Tegra AHB driverHiroshi DOYU
Tegra AHB Bus conforms to the AMBA Specification (Rev 2.0) Advanced High-performance Bus (AHB) architecture. The AHB Arbiter controls AHB bus master arbitration. This effectively forms a second level of arbitration for access to the memory controller through the AHB Slave Memory device. The AHB pre-fetch logic can be configured to enhance performance for devices doing sequential access. Each AHB master is assigned to either the high or low priority bin. Both Tegra20/30 have this AHB bus. Some of configuration params could be passed from DT too if needed. Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Cc: Felipe Balbi <balbi@ti.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-05-08ARM: orion5x: Fix GPIO enable bits for MPP9Ben Hutchings
Commit 554cdaefd1cf7bb54b209c4e68c7cec87ce442a9 ('ARM: orion5x: Refactor mpp code to use common orion platform mpp.') seems to have accidentally inverted the GPIO valid bits for MPP9 (only). For the mv2120 platform which uses MPP9 as a GPIO LED device, this results in the error: [ 12.711476] leds-gpio: probe of leds-gpio failed with error -22 Reported-by: Henry von Tresckow <hvontres@gmail.com> References: http://bugs.debian.org/667446 Signed-off-by: Ben Hutchings <ben@decadent.org.uk> Cc: stable@vger.kernel.org [v3.0+] Tested-by: Hans Henry von Tresckow <hvontres@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2012-05-08Merge tag 'omap-devel-b-for-3.5' of ↵Tony Lindgren
git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into devel-prcm Some OMAP PRCM updates for 3.5. Includes some clock, clockdomain, powerdomain, PRM, and CM changes.
2012-05-08ARM: kirkwood: add missing kexec.h includeIan Campbell
Fixes the following build error when CONFIG_KEXEC is enabled: CC arch/arm/mach-kirkwood/board-dt.o arch/arm/mach-kirkwood/board-dt.c: In function 'kirkwood_dt_init': arch/arm/mach-kirkwood/board-dt.c:52:2: error: 'kexec_reinit' undeclared (first use in this function) arch/arm/mach-kirkwood/board-dt.c:52:2: note: each undeclared identifier is reported only once for each function it appears in Signed-off-by: Ian Campbell <ijc@hellion.org.uk> [v4, rebase onto recent Linus for repost] [v3, speak actual English in the commit message, thanks Sergei Shtylyov] [v2, using linux/kexec.h not asm/kexec.h] Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2012-05-08Merge branch 'devel-hwmod' into cleanupTony Lindgren
2012-05-08Merge branch 'for_3.5/omap_misc_cleanup' of ↵Tony Lindgren
git://gitorious.org/omap-sw-develoment/linux-omap-dev into cleanup-soc
2012-05-09ARM: mxs: remove now unused timer_clk argument from mxs_timer_initShawn Guo
With old mxs clock support removed, the timer_clk argument of mxs_timer_init is unused now, so remove it. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2012-05-09ARM: mxs: remove old clock supportShawn Guo
The mxs clock has been switched to common clock framework, so the old clock support can be removed now. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2012-05-09ARM: mxs: switch to common clk frameworkShawn Guo
It switches mxs clock support to common clk framework based drivers. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2012-05-09ARM: mxs: change the lookup name for fec phy clockShawn Guo
Change the fec phy clock lookup name to be more accurate. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2012-05-09ARM: mxs: request clock for timerShawn Guo
When mxs_timer_init() does not have a timer_clk passed in, it should try to request clock from clkdev system. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2012-05-08ARM: imx: eukrea_mbimxsd rename to eukrea_mbimxsd51Eric Bénard
this makes the mbimxsd51 board naming consistant with others Signed-off-by: Eric Bénard <eric@eukrea.com> Cc: Sascha Hauer <kernel@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>