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2014-05-21MIPS: math-emu: Move all debug fs code to a separate file.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-05-21MIPS: math-emu: Remove fine example of cargo cult programming.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-05-21MIPS: math-emu: Header file weeding.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-05-21MIPS: math-emu: Use helpers to manipulate CAUSEF_BD flag.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-05-21MIPS: math-emu: Get rid of typedefs.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-05-21MIPS: math-emu: Use English spelling of `constant' rather than Danish.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-05-21MIPS: math-emu: Mark exception handling functions as __cold.Ralf Baechle
Optimizes the code flow and shaves of half a percent of the math-emu code size. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-05-21MIPS: math-emu: Use __BITFIELD_FIELD to eleminate redundant definitions.Ralf Baechle
Union _ieee754sp was even duplicated even though there are no endian dependencies in it all. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31Merge branch '3.14-fixes' into mips-for-linux-nextRalf Baechle
2014-03-26MIPS: Clear upper bits of FP registers on emulator writesPaul Burton
The upper bits of an FP register are architecturally defined as unpredictable following an instructions which only writes the lower bits. The prior behaviour of the kernel is to leave them unmodified. This patch modifies that to clear the upper bits to zero. This is what the MSA architecture reference manual specifies should happen for its wider registers and is still permissible for scalar FP instructions given the bits unpredictability there. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: sergei.shtylyov@cogentembedded.com Patchwork: https://patchwork.linux-mips.org/patch/6435/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26MIPS: Move & rename fpu_emulator_{save,restore}_contextPaul Burton
These functions aren't directly related to the FPU emulator at all, they simply copy between a thread's saved context & a sigcontext. Thus move them to the appropriate signal files & rename them accordingly. This makes it clearer that the functions don't require the FPU emulator in any way. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6422/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26MIPS: Simplify FP context accessPaul Burton
This patch replaces the fpureg_t typedef with a "union fpureg" enabling easier access to 32 & 64 bit values. This allows the access macros used in cp1emu.c to be simplified somewhat. It will also make it easier to expand the width of the FP registers as will be done in a future patch in order to support the 128 bit registers introduced with MSA. No behavioural change is intended by this patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6532/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-11MIPS: math-emu: Fix prefx detection and COP1X function field definitionDeng-Cheng Zhu
When running applications which contain the instruction "prefx" on FPU-less CPUs, a message "Illegal instruction" will be seen. This instruction is supposed to be ignored by the FPU emulator. However, its current detection and function field encoding are incorrect. This patch fix the issue. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Reviewed-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Acked-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: Steven.Hill@imgtec.com Patchwork: https://patchwork.linux-mips.org/patch/6608/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-13MIPS: Support for 64-bit FP with O32 binariesPaul Burton
CPUs implementing MIPS32 R2 may include a 64-bit FPU, just as MIPS64 CPUs do. In order to preserve backwards compatibility a 64-bit FPU will act like a 32-bit FPU (by accessing doubles from the least significant 32 bits of an even-odd pair of FP registers) when the Status.FR bit is zero, again just like a mips64 CPU. The standard O32 ABI is defined expecting a 32-bit FPU, however recent toolchains support use of a 64-bit FPU from an O32 MIPS32 executable. When an ELF executable is built to use a 64-bit FPU a new flag (EF_MIPS_FP64) is set in the ELF header. With this patch the kernel will check the EF_MIPS_FP64 flag when executing an O32 binary, and set Status.FR accordingly. The addition of O32 64-bit FP support lessens the opportunity for optimisation in the FPU emulator, so a CONFIG_MIPS_O32_FP64_SUPPORT Kconfig option is introduced to allow this support to be disabled for those that don't require it. Inspired by an earlier patch by Leonid Yegoshin, but implemented more cleanly & correctly. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Paul Burton <paul.burton@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/6154/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-13MIPS: microMIPS: mfhc1 & mthc1 support for the FPU emulatorSteven J. Hill
This patch adds support for microMIPS encodings of the mfhc1 & mthc1 instructions introduced in release 2 of the mips32 & mips64 architectures, converting them to their mips32 equivalents for the FPU emulator. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6110/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-13MIPS: math-emu: Add mfhc1 & mthc1 support.Leonid Yegoshin
This patch adds support for the mfhc1 & mthc1 instructions to the FPU emulator. These instructions were introduced in release 2 of the MIPS32 & MIPS64 architectures and allow access to the most significant 32 bits of a 64-bit FP register. [ralf@linux-mips.org: Fix ifdef hell added by original patch.] Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6112/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-08-26MIPS: Remove unreachable break statements from cp1emu.cDavid Daney
There were many cases of: return something; break; All those break statements are unreachable and thus redundant. Signed-off-by: David Daney <david.daney@cavium.com> Reviewed-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5727/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-08-20MIPS: Handle OCTEON BBIT instructions in FPU emulator.David Daney
The branch emulation needs to handle the OCTEON BBIT instructions, otherwise we get SIGILL instead of emulation. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5726/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-01MIPS: Don't try to decode microMIPS branch instructions where they cannot exist.David Daney
In mm_isBranchInstr() we can short circuit the entire function if !cpu_has_mmips. Signed-off-by: David Daney <david.daney@cavium.com> Acked-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5326/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-09MIPS: microMIPS: Floating point support.Leonid Yegoshin
Add logic needed to do floating point emulation in microMIPS mode. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Steven J. Hill <Steven. Hill@imgtec.com>
2013-02-01MIPS: Whitespace cleanup.Ralf Baechle
Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-02-01MIPS: Nuke empty lines at end of files.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-12-13MIPS: Fix for warning from FPU emulation codeRalf Baechle
The default implementation of 'cpu_has_fpu' macro calls smp_processor_id() which causes this warning to be printed when preemption is enabled: [ 4.664000] Algorithmics/MIPS FPU Emulator v1.5 [ 4.676000] BUG: using smp_processor_id() in preemptible [00000000] code: ini [ 4.700000] caller is fpu_emulator_cop1Handler+0x434/0x27b8 This problem got introduced in November 2009 by af1d2af877ef6c36990671bc86a5b9c5bb50b1da (lmo) [MIPS: Fix emulation of 64-bit FPU on 64-bit CPUs.] rsp. da0bac33413b2888d3623dad3ad19ce76b688f07 (kernel.org) [MIPS: Fix emulation of 64-bit FPU on FPU-less 64-bit CPUs.] in 2.6.32. Fixed by rewriting cop1_64bit() to return a constant whenever possible but most importantly avoid the use pf cpu_has_fpu entirely. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Reported-by: Jayachandran C <jchandra@broadcom.com> Initial-patch-by: Jayachandran C <jchandra@broadcom.com> Patchwork: https://patchwork.linux-mips.org/patch/4225/
2012-03-28Disintegrate asm/system.h for MIPSDavid Howells
Disintegrate asm/system.h for MIPS. Signed-off-by: David Howells <dhowells@redhat.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> cc: linux-mips@linux-mips.org
2011-12-07MIPS Kprobes: Refactor branch emulationManeesh Soni
This patch refactors MIPS branch emulation code so as to allow skipping delay slot instruction in case of branch likely instructions when branch is not taken. This is useful for keeping the code common for use cases like kprobes where one would like to handle the branch instructions keeping the delay slot instuction also in picture for branch likely instructions. Also allow emulation when instruction to be decoded is not at pt_regs->cp0_epc as in case of kprobes where pt_regs->cp0_epc points to the breakpoint instruction. The patch also exports the function for modules. Signed-off-by: Maneesh Soni <manesoni@cisco.com> Signed-off-by: Victor Kamensky <kamensky@cisco.com> Cc: David Daney <david.daney@cavium.com> Cc: ananth@in.ibm.com Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2913/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-07-01perf: Remove the nmi parameter from the swevent and overflow interfacePeter Zijlstra
The nmi parameter indicated if we could do wakeups from the current context, if not, we would set some state and self-IPI and let the resulting interrupt do the wakeup. For the various event classes: - hardware: nmi=0; PMI is in fact an NMI or we run irq_work_run from the PMI-tail (ARM etc.) - tracepoint: nmi=0; since tracepoint could be from NMI context. - software: nmi=[0,1]; some, like the schedule thing cannot perform wakeups, and hence need 0. As one can see, there is very little nmi=1 usage, and the down-side of not using it is that on some platforms some software events can have a jiffy delay in wakeup (when arch_irq_work_raise isn't implemented). The up-side however is that we can remove the nmi parameter and save a bunch of conditionals in fast paths. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Michael Cree <mcree@orcon.net.nz> Cc: Will Deacon <will.deacon@arm.com> Cc: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> Cc: Anton Blanchard <anton@samba.org> Cc: Eric B Munson <emunson@mgebm.net> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: Paul Mundt <lethal@linux-sh.org> Cc: David S. Miller <davem@davemloft.net> Cc: Frederic Weisbecker <fweisbec@gmail.com> Cc: Jason Wessel <jason.wessel@windriver.com> Cc: Don Zickus <dzickus@redhat.com> Link: http://lkml.kernel.org/n/tip-agjev8eu666tvknpb3iaj0fg@git.kernel.org Signed-off-by: Ingo Molnar <mingo@elte.hu>
2011-03-31Fix common misspellingsLucas De Marchi
Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
2011-03-14MIPS: Fix GCC-4.6 'set but not used' warning in ieee754int.hDavid Daney
GCC-4.6 can find more unused code than previous versions could. In the case of arch/mips/math-emu/ieee754int.h, the COMPXSP and COMPXDP macros are used in several places, but a couple of them leave xs unused. The easiest thing to do is mark it as __maybe_unused to quiet the warning. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2032/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-12-16MIPS: Send proper signal and siginfo on FP emulator faults.David Daney
We were unconditionally sending SIGBUS with an empty siginfo on FP emulator faults. This differs from what happens when real floating point hardware would get a fault. For most faults we need to send SIGSEGV with the faulting address filled in in the struct siginfo. Reported-by: Camm Maguire <camm@maguirefamily.org> Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Cc: Camm Maguire <camm@maguirefamily.org> Patchwork: https://patchwork.linux-mips.org/patch/1727/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29MIPS: add support for software performance eventsDeng-Cheng Zhu
Software events are required as part of the measurable stuff by the Linux performance counter subsystem. Here is the list of events added by this patch: PERF_COUNT_SW_PAGE_FAULTS PERF_COUNT_SW_PAGE_FAULTS_MIN PERF_COUNT_SW_PAGE_FAULTS_MAJ PERF_COUNT_SW_ALIGNMENT_FAULTS PERF_COUNT_SW_EMULATION_FAULTS Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> To: linux-mips@linux-mips.org Cc: a.p.zijlstra@chello.nl Cc: paulus@samba.org Cc: mingo@elte.hu Cc: acme@redhat.com Cc: jamie.iles@picochip.com Acked-by: David Daney <ddaney@caviumnetworks.com> Reviewed-by: Matt Fleming <matt@console-pimps.org> Patchwork: https://patchwork.linux-mips.org/patch/1686/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-18Update broken web addresses in arch directory.Justin P. Mattock
The patch below updates broken web addresses in the arch directory. Signed-off-by: Justin P. Mattock <justinmattock@gmail.com> Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: Finn Thain <fthain@telegraphics.com.au> Cc: Randy Dunlap <rdunlap@xenotime.net> Reviewed-by: Finn Thain <fthain@telegraphics.com.au> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2010-08-05MIPS: Add -Werror to arch/mips/KbuildSam Ravnborg
Adding subdirs-ccflags-y := -Werror to arch/mips/Kbuild let us in one go cover all files with -Werror. In addition this allows us to remove the individual -Werror definition in various Makefile. Adding the definition to Kbuild as a recursive option help us not to forget to do so. With this change we now compile arch/mips/kernel/cpufreq with -Werror One drawback: When specifying a subdirectory covered by the Kbuild file like this: make arch/mips/kernel/ then kbuild fails to pick up the -Werror definition. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> To: linux-mips <linux-mips@linux-mips.org> To: Wu Zhangjin <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/1301/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-08-05MIPS: math-emu: Checkpatch cleanupAndrea Gelmini
arch/mips/math-emu/sp_tlong.c:75: ERROR: else should follow close brace '}' Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1276/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-08-05MIPS: math-emu: Checkpatch cleanupAndrea Gelmini
arch/mips/math-emu/sp_tint.c:76: ERROR: else should follow close brace '}' Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1275/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-08-05MIPS: math-emu: Checkpatch cleanupAndrea Gelmini
arch/mips/math-emu/sp_modf.c:32: ERROR: "foo * bar" should be "foo *bar" Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1273/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-08-05MIPS: math-emu: Checkpatch cleanupAndrea Gelmini
arch/mips/math-emu/dp_tlong.c:75: ERROR: else should follow close brace '}' Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1272/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-08-05MIPS: math-emu: Checkpatch cleanupAndrea Gelmini
arch/mips/math-emu/dp_tint.c:73: ERROR: else should follow close brace '}' Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1271/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-08-05MIPS: math-emu: Checkpatch cleanupAndrea Gelmini
arch/mips/math-emu/dp_modf.c:32: ERROR: "foo * bar" should be "foo *bar" Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1269/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-07-05MIPS: Restore signalling NaN behaviour for abs.[sd]Chris Dearman
Atsushi Nemoto <anemo@mba.ocn.ne.jp> spotted that this had been incorrectly removed in a previous patch Signed-off-by: Chris Dearman <chris@mips.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1213/ Tested-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-05-21MIPS: Coding style cleanups of access of FCSR rounding mode bitsShane McDonald
Replaces references to the magic number 0x3 with constants and macros indicating the real purpose of those bits. They are the rounding mode bits of the FCSR register. Signed-off-by: Shane McDonald <mcdonald.shane@gmail.com> To: anemo@mba.ocn.ne.jp To: kevink@paralogos.com To: linux-mips@linux-mips.org To: sshtylyov@mvista.com Patchwork: http://patchwork.linux-mips.org/patch/1206/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-05-15 MIPS FPU emulator: allow Cause bits of FCSR to be writeable by ctc1Shane McDonald
In the FPU emulator code of the MIPS, the Cause bits of the FCSR register are not currently writeable by the ctc1 instruction. In odd corner cases, this can cause problems. For example, a case existed where a divide-by-zero exception was generated by the FPU, and the signal handler attempted to restore the FPU registers to their state before the exception occurred. In this particular setup, writing the old value to the FCSR register would cause another divide-by-zero exception to occur immediately. The solution is to change the ctc1 instruction emulator code to allow the Cause bits of the FCSR register to be writeable. This is the behaviour of the hardware that the code is emulating. This problem was found by Shane McDonald, but the credit for the fix goes to Kevin Kissell. In Kevin's words: I submit that the bug is indeed in that ctc_op: case of the emulator. The Cause bits (17:12) are supposed to be writable by that instruction, but the CTC1 emulation won't let them be updated by the instruction. I think that actually if you just completely removed lines 387-388 [...] things would work a good deal better. At least, it would be a more accurate emulation of the architecturally defined FPU. If I wanted to be really, really pedantic (which I sometimes do), I'd also protect the reserved bits that aren't necessarily writable. Signed-off-by: Shane McDonald <mcdonald.shane@gmail.com> To: anemo@mba.ocn.ne.jp To: kevink@paralogos.com To: sshtylyov@mvista.com Patchwork: http://patchwork.linux-mips.org/patch/1205/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2010-02-27MIPS: Nuke trailing blank linesRalf Baechle
Recent git versions now warn about those and they've always been a bit of an annoyance. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27MIPS: Cleanup switches with cases that can be mergedRoel Kluin
Signed-off-by: Roel Kluin <roel.kluin@gmail.com> To: linux-mips@linux-mips.org To: Andrew Morton <akpm@linux-foundation.org> To: LKML <linux-kernel@vger.kernel.org> Patchwork: http://patchwork.linux-mips.org/patch/860/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-12-17MIPS: Collect FPU emulator statistics per-CPU.David Daney
On SMP systems, the collection of statistics can cause cache line bouncing in the lines associated with the counters. Also there are races incrementing the counters on multiple CPUs. To fix both problems, we collect the statistics in per-CPU variables, and add them up in the debugfs read operation. As a test I ran the LTP float_bessel test on a 12 CPU Octeon system. Without CONFIG_DEBUG_FS : 2602 seconds. With CONFIG_DEBUG_FS: 2640 seconds. With non-cpu-local atomic statistics: 14569 seconds. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Cc: linux-mips@linux-mips.org Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-12-07Merge branch 'for-next' into for-linusJiri Kosina
Conflicts: kernel/irq/chip.c
2009-12-04tree-wide: fix assorted typos all over the placeAndré Goddard Rosa
That is "success", "unknown", "through", "performance", "[re|un]mapping" , "access", "default", "reasonable", "[con]currently", "temperature" , "channel", "[un]used", "application", "example","hierarchy", "therefore" , "[over|under]flow", "contiguous", "threshold", "enough" and others. Signed-off-by: André Goddard Rosa <andre.goddard@gmail.com> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2009-11-13MIPS: Fix emulation of 64-bit FPU on FPU-less 64-bit CPUs.David Daney
Running a 64-bit kernel on a 64-bit CPU without an FPU would cause the emulator to run in 32-bit mode. The c0_Status.FR bit is wired to zero on systems without an FPU, so using that bit to decide how the emulator behaves doesn't allow for proper emulation on 64-bit FPU-less processors. Instead, we need to select the emulator mode based on the user-space ABI. Since the thread flag TIF_32BIT_REGS is used to set c0_Status.FR, we can just use it to decide if the emulator should be in 32-bit or 64-bit mode. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: Fix abs.[sd] and neg.[sd] emulation for NaN operandsNigel Stephens
This patch ensures that the sign bit is always updated for NaN operands. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-10-30MIPS: Switch FPU emulator trap to BREAK instruction.Ralf Baechle
Arguably using the address error handler has always been ugly. But with processors that handle unaligned loads and stores in hardware the current mechanism ceases to work so switch it to a BREAK instruction and allocate break code 514 to the FPU emulator. Yoichi Yuasa provided a build fix for CONFIG_BUG=n. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
2008-10-27MIPS: Fix debugfs_create_*'s error checking method for arch/mips/math-emu/Zhaolei
debugfs_create_*() returns NULL on error. Make its caller debugfs_fpuemu return -ENODEV on error. Signed-off-by: Zhao Lei <zhaolei@cn.fujitsu.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>