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Author
2008-04-28
[MIPS] Reimplement clear_page/copy_page
Thiemo Seufer
2008-02-01
[MIPS] Split the micro-assembler from tlbex.c.
Thiemo Seufer
2007-10-11
[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.
Ralf Baechle
2007-07-31
[MIPS] Use -Werror on subdirectories which build cleanly.
Ralf Baechle
2007-07-10
[MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2
Fuxin Zhang
2007-02-26
[MIPS] Kill redundant EXTRA_AFLAGS
Atsushi Nemoto
2007-02-13
[MIPS] Unify dma-{coherent,noncoherent.ip27,ip32}
Ralf Baechle
2006-06-29
[MIPS] MIPS32/MIPS64 secondary cache management
Chris Dearman
2006-03-21
[MIPS] Kill tlb-andes.c.
Thiemo Seufer
2005-10-29
Fixup a few lose ends in explicit support for MIPS R1/R2.
Ralf Baechle
2005-10-29
Use R4000 TLB routines for SB1 also.
Ralf Baechle
2005-10-29
Rename CONFIG_CPU_MIPS{32,64} to CONFIG_CPU_MIPS{32|64}_R1.
Ralf Baechle
2005-09-05
[PATCH] mips: clean up 32/64-bit configuration
Ralf Baechle
2005-04-16
Linux-2.6.12-rc2
v2.6.12-rc2
Linus Torvalds
