| Age | Commit message (Expand) | Author |
|---|
| 2005-10-29 | [PATCH] mm: init_mm without ptlock | Hugh Dickins |
| 2005-10-29 | SB1 cache exception handling. | Andrew Isaacson |
| 2005-10-29 | Add support for SB1A CPU. | Andrew Isaacson |
| 2005-10-29 | Fix zero length sys_cacheflush | Atsushi Nemoto |
| 2005-10-29 | Rename page argument of flush_cache_page to something more descriptive. | Ralf Baechle |
| 2005-10-29 | Fix wrong comment. | Ralf Baechle |
| 2005-10-29 | Fixup a few lose ends in explicit support for MIPS R1/R2. | Ralf Baechle |
| 2005-10-29 | Don't copy SB1 cache error handler to uncached memory. | Ralf Baechle |
| 2005-10-29 | Fix stale comment in c-sb1.c. | Andrew Isaacson |
| 2005-10-29 | Cleanup the mess in cpu_cache_init. | Ralf Baechle |
| 2005-10-29 | Use R4000 TLB routines for SB1 also. | Ralf Baechle |
| 2005-10-29 | Sync c-tx39.c with c-r4k.c. | Atsushi Nemoto |
| 2005-10-29 | Add/Fix missing bit of R4600 hit cacheop workaround. | Thiemo Seufer |
| 2005-10-29 | Minor code cleanup. | Thiemo Seufer |
| 2005-10-29 | R4600 v2.0 needs a nop before tlbp. | Thiemo Seufer |
| 2005-10-29 | Don't set up a sg dma address if we have no page address for some reason. | Thiemo Seufer |
| 2005-10-29 | More .set push/pop. | Thiemo Seufer |
| 2005-10-29 | Let r4600 PRID detection match only legacy CPUs, cleanups. | Thiemo Seufer |
| 2005-10-29 | Handle mtc0 - tlb write hazard for VR5432. | Ralf Baechle |
| 2005-10-29 | Avoid SMP cacheflushes. This is a minor optimization of startup but | Ralf Baechle |
| 2005-10-29 | Philips PNX8550 support: MIPS32-like core with 2 Trimedias on it. | Pete Popov |
| 2005-10-29 | More AP / SP bits for the 34K, the Malta bits and things. Still wants | Ralf Baechle |
| 2005-10-29 | Mark a few variables __read_mostly. | Ralf Baechle |
| 2005-10-29 | MIPS R2 instruction hazard handling. | Ralf Baechle |
| 2005-10-29 | Detect the 34K. | Ralf Baechle |
| 2005-10-29 | Define kmap_atomic_pfn() for MIPS. | Ralf Baechle |
| 2005-10-29 | Date: Fri Jul 8 20:10:17 2005 +0000 | Ralf Baechle |
| 2005-10-29 | Rename CONFIG_CPU_MIPS{32,64} to CONFIG_CPU_MIPS{32|64}_R1. | Ralf Baechle |
| 2005-10-29 | Avoid tlbw* hazards for the R4600/R4700/R5000. | Maciej W. Rozycki |
| 2005-10-29 | Inline ioremap() calls for constant addresses that map to KSEG1. | Maciej W. Rozycki |
| 2005-10-29 | Fix the diagnostic dump for the XTLB refill handler. | Maciej W. Rozycki |
| 2005-10-29 | Fix a diagnostic message. | Maciej W. Rozycki |
| 2005-10-29 | Use macros for the RM7k cp0.config bits instead of magic numbers. | Maciej W. Rozycki |
| 2005-10-29 | Optimize R3k TLB Load/Store/Modified handlers, by scheduling | Maciej W. Rozycki |
| 2005-10-29 | Fill R3k load delay slots properly. | Maciej W. Rozycki |
| 2005-10-29 | Only dump instructions actually emitted. | Maciej W. Rozycki |
| 2005-10-29 | Handle _PAGE_DIRTY correctly for CONFIG_64BIT_PHYS_ADDR on 32bit CPUs. | Thiemo Seufer |
| 2005-10-29 | Better interface to run uncached cache setup code. | Thiemo Seufer |
| 2005-10-29 | Arrested for multiple offences of header file inclusion. | Ralf Baechle |
| 2005-10-29 | Fix race conditions for read_c0_entryhi. Remove broken ASID masks in | Thiemo Seufer |
| 2005-10-29 | Remove useless casts. Fix formatting. | Maciej W. Rozycki |
| 2005-10-29 | Fix 64bit SMP TLB handler and stack frame handling, optimize 32bit SMP | Thiemo Seufer |
| 2005-10-29 | R4300 delay slot. | Ralf Baechle |
| 2005-10-29 | Reformat; cosmetic cleanups. | Ralf Baechle |
| 2005-10-29 | Export shm_align_mask and flush_data_cache_page. | Ralf Baechle |
| 2005-10-29 | Gcc 4.0 fixes. | Ralf Baechle |
| 2005-10-29 | Sparseify MIPS. | Ralf Baechle |
| 2005-10-29 | Base Au1200 2.6 support. | Pete Popov |
| 2005-10-29 | Fix initialization. Unbreak the wait-for-completion loops. Code cleanup. | Thiemo Seufer |
| 2005-10-29 | Switch SiByte drivers back to __raw_*() functions. | Maciej W. Rozycki |
