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AgeCommit message (Expand)Author
2005-10-29Rename page argument of flush_cache_page to something more descriptive.Ralf Baechle
2005-10-29Fix wrong comment.Ralf Baechle
2005-10-29Fixup a few lose ends in explicit support for MIPS R1/R2.Ralf Baechle
2005-10-29Don't copy SB1 cache error handler to uncached memory.Ralf Baechle
2005-10-29Fix stale comment in c-sb1.c.Andrew Isaacson
2005-10-29Cleanup the mess in cpu_cache_init.Ralf Baechle
2005-10-29Use R4000 TLB routines for SB1 also.Ralf Baechle
2005-10-29Sync c-tx39.c with c-r4k.c.Atsushi Nemoto
2005-10-29Add/Fix missing bit of R4600 hit cacheop workaround.Thiemo Seufer
2005-10-29Minor code cleanup.Thiemo Seufer
2005-10-29R4600 v2.0 needs a nop before tlbp.Thiemo Seufer
2005-10-29Don't set up a sg dma address if we have no page address for some reason.Thiemo Seufer
2005-10-29More .set push/pop.Thiemo Seufer
2005-10-29Let r4600 PRID detection match only legacy CPUs, cleanups.Thiemo Seufer
2005-10-29Handle mtc0 - tlb write hazard for VR5432.Ralf Baechle
2005-10-29Avoid SMP cacheflushes. This is a minor optimization of startup butRalf Baechle
2005-10-29Philips PNX8550 support: MIPS32-like core with 2 Trimedias on it.Pete Popov
2005-10-29More AP / SP bits for the 34K, the Malta bits and things. Still wantsRalf Baechle
2005-10-29Mark a few variables __read_mostly.Ralf Baechle
2005-10-29MIPS R2 instruction hazard handling.Ralf Baechle
2005-10-29Detect the 34K.Ralf Baechle
2005-10-29Define kmap_atomic_pfn() for MIPS.Ralf Baechle
2005-10-29Date: Fri Jul 8 20:10:17 2005 +0000Ralf Baechle
2005-10-29Rename CONFIG_CPU_MIPS{32,64} to CONFIG_CPU_MIPS{32|64}_R1.Ralf Baechle
2005-10-29Avoid tlbw* hazards for the R4600/R4700/R5000.Maciej W. Rozycki
2005-10-29Inline ioremap() calls for constant addresses that map to KSEG1.Maciej W. Rozycki
2005-10-29Fix the diagnostic dump for the XTLB refill handler.Maciej W. Rozycki
2005-10-29Fix a diagnostic message.Maciej W. Rozycki
2005-10-29Use macros for the RM7k cp0.config bits instead of magic numbers.Maciej W. Rozycki
2005-10-29Optimize R3k TLB Load/Store/Modified handlers, by schedulingMaciej W. Rozycki
2005-10-29Fill R3k load delay slots properly.Maciej W. Rozycki
2005-10-29Only dump instructions actually emitted.Maciej W. Rozycki
2005-10-29Handle _PAGE_DIRTY correctly for CONFIG_64BIT_PHYS_ADDR on 32bit CPUs.Thiemo Seufer
2005-10-29Better interface to run uncached cache setup code.Thiemo Seufer
2005-10-29Arrested for multiple offences of header file inclusion.Ralf Baechle
2005-10-29Fix race conditions for read_c0_entryhi. Remove broken ASID masks inThiemo Seufer
2005-10-29Remove useless casts. Fix formatting.Maciej W. Rozycki
2005-10-29Fix 64bit SMP TLB handler and stack frame handling, optimize 32bit SMPThiemo Seufer
2005-10-29R4300 delay slot.Ralf Baechle
2005-10-29Reformat; cosmetic cleanups.Ralf Baechle
2005-10-29Export shm_align_mask and flush_data_cache_page.Ralf Baechle
2005-10-29Gcc 4.0 fixes.Ralf Baechle
2005-10-29Sparseify MIPS.Ralf Baechle
2005-10-29Base Au1200 2.6 support.Pete Popov
2005-10-29Fix initialization. Unbreak the wait-for-completion loops. Code cleanup.Thiemo Seufer
2005-10-29Switch SiByte drivers back to __raw_*() functions.Maciej W. Rozycki
2005-10-29Handle addresses beyond VMALLOC_END correctly.Thiemo Seufer
2005-10-29Use intermediate variable.Thiemo Seufer
2005-10-29Moves a test which determines if we actually need to perform aRalf Baechle
2005-10-29Update MIPS to use the 4-level pagetable code thereby getting rid ofRalf Baechle
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