summaryrefslogtreecommitdiffstats
path: root/arch/mips
AgeCommit message (Collapse)Author
2013-02-17MIPS: PCI: Multi-node PCI support for Netlogic XLPJayachandran C
On a multi-chip XLP board, each node can have 4 PCIe links. Update XLP PCI code to initialize PCIe on all the nodes. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4803/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: Netlogic: Fix for quad-XLP bootJayachandran C
On multi-chip boards, the first core on slave SoCs may take much more time to wakeup. Add code to wait for the core to come up before proceeding with the rest of the boot up. Update xlp_wakeup_core to also skip the boot node and the boot CPU initialization which is already complete. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4783/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: Netlogic: use preset loops per jiffyJayachandran C
Doing calibrate delay on a hardware thread will be inaccurate since it depends on the load on other threads in the core. It will also slow down the boot process when done for 128 hardware threads. Switch to a pre-computed loops per jiffy based on the core frequency. The value is computed based on the core frequency and roughly matches the value calculated by calibrate_delay(). Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4791/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: Netlogic: No hazards needed for XLR/XLSJayachandran C
TLB and COP0 hazards are handled in hardware for Netlogic XLR/XLS SoCs. Update hazards.h to pick more optimal set of definitions when compiling for XLR/XLS. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4788/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: PCI: Prevent hang on XLP reg readJayachandran C
Reading PCI extended register at 0x255 on a bridge will hang if there is no device connected on the link. Make PCI read routine skip this register. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4789/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: Netlogic: Use PIC timer as a clocksourceJayachandran C
The XLR/XLS/XLP PIC has a 8 countdown timers which run at the PIC frequencey. One of these can be used as a clocksource to provide timestamps that is common across cores. This can be used in place of the count/compare clocksource which is per-CPU. On XLR/XLS PIC registers are 32-bit, so we just use the lower 32-bits of the PIC counter. On XLP, the whole 64-bit can be used. Provide common macros and functions for PIC timer registers on XLR/XLS and XLP, and use them to register a PIC clocksource. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4786/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: Netlogic: Split XLP L1 i-cache among threadsJayachandran C
Since we now use r4k cache code for Netlogic XLP, it is better to split L1 icache among the active threads, so that threads won't step on each other while flushing icache. The L1 dcache is already split among the threads in the core. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4787/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: PCI: Byteswap not needed in little-endian modeJayachandran C
Rename function xlp_enable_pci_bswap() to xlp_config_pci_bswap(), which is a better description for its functionality. When compiled in big-endian mode, xlp_config_pci_bswap() will configure the PCIe links to byteswap. In little-endian mode, no swap configuration is needed for the PCIe controller, and the function is empty. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4802/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: Netlogic: Optimize EIMR/EIRR accesses in 32-bitJayachandran C
Provide functions ack_c0_eirr(), set_c0_eimr(), clear_c0_eimr() and read_c0_eirr_and_eimr() that do the EIMR and EIRR operations and update the interrupt handling code to use these functions. Also, use the EIMR register functions to mask interrupts in the irq code. The 64-bit interrupt request and mask registers (EIRR and EIMR) are accessed when the interrupts are off, and the common operations are to set or clear a bit in these registers. Using the 64-bit c0 access functions for these operations is not optimal in 32-bit, because it will disable/restore interrupts and split/join the 64-bit value during each register access. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4790/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: Netlogic: add XLS6xx to FMN configJayachandran C
Add support for XLS6xx CPUs to the Fast Message Network (FMN) configuration. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4785/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17MIPS: lantiq: rework external irq codeJohn Crispin
This code makes the irqs used by the EIU loadable from the DT. Additionally we add a helper that allows the pinctrl layer to map external irqs to real irq numbers. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4818/
2013-02-17MIPS: lantiq: improve pci reset gpio handlingJohn Crispin
We need to make sure that the reset gpio is available and also set a sane default state. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4817/
2013-02-17MIPS: lantiq: add GPHY clock gate bitsJohn Crispin
Explicitly enable the clock gate of the internal GPHYs found on xrx200. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4816/
2013-02-17MIPS: lantiq: adds static clock for PP32John Crispin
The Lantiq DSL SoCs have an internal networking processor. Add code to read the static clock rate. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4815/
2013-02-17MIPS: lantiq: trivial typo fixJohn Crispin
"nodes" is written with a single "s" Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4814/
2013-02-17MIPS: show correct cpu name for 24KEcJohn Crispin
Make sure 24KEc is properly identified inside /proc/cpuinfo Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15MIPS: Cleanup break and trap codes.Ralf Baechle
Very ancient out-of-tree KDB versions were using BRK_KDB code but it's unused in modern kernels since a long time. Delete it. The microMIPS encoding only reserves 4 bits for a trap code so it's time for further weedkilling. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-02-15MIPS: Redefine value of BRK_BUG.Steven J. Hill
The BRK_BUG value is used in the BUG and __BUG_ON inline macros. For standard MIPS cores the code in the 'tne' instruction is 10-bits long. In microMIPS, the 'tne' instruction is recoded and the code can only be 4-bits long. We change the value to 12 instead of 512 so that both classic and microMIPS kernels build. [ralf@linux-mips.org: Many of the break codes starting from 0 are used across many MIPS UNIX variants. Codes starting from 512 are operating system specific additions. 1023 again is also used by other operating systems] Signed-off-by: Steven J. Hill <sjhill@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-02-15MIPS: Add printing of ISA version in cpuinfo.Steven J. Hill
Display the MIPS ISA version release in the /proc/cpuinfo file. [ralf@linux-mips.org: Add support for MIPS I ... IV legacy architecture revisions. Also differenciate between MIPS32 and MIPS64 versions instead of lumping them together as just r1 and r2. Note to application programmers: this indicates the CPU's ISA level It does not imply the current execution environment does support it. For example an O32 application seeing "mips64r2" would still be restricted by by the execution environment to 32-bit - but the kernel could run mips64r2 code. The same for a 32-bit kernel running on a 64-bit processor. This field doesn't include ASEs or optional architecture modules nor other detailed flags such as the availability of an FPU.] Signed-off-by: Steven J. Hill <sjhill@mips.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/4714/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-02-15MIPS: Octeon: Adding driver to measure interrupt latency on Octeon.Venkat Subbiah
Signed-off-by: Venkat Subbiah <venkat.subbiah@cavium.com> [Rewrote timeing calculations] Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4660/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-02-15MIPS: Loongson2: Use clk API instead of direct dereferencesJulia Lawall
A struct clk value is intended to be an abstract pointer, so it should be manipulated using the various API functions. clk_put is additionally added on the failure paths. The semantic match that finds the first problem is as follows: (http://coccinelle.lip6.fr/) // <smpl> @@ expression e,e1; identifier i; @@ *e = clk_get(...) ... when != e = e1 when any *e->i // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Cc: kernel-janitors@vger.kernel.org Cc: linux-mips@linux-mips.org, Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/4751/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-02-15MIPS: BCM47XX: use fallback sprom var for board_{rev,type}Hauke Mehrtens
An SoC normally do not define path variables for board_rev and board_type and the Broadcom SDK also uses the nvram values without a prefix in such cases. Do the same to fill these sprom attributes from nvram and do not leave them empty, because brcmsmac do not like this. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4679/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15MIPS: BCM47XX: select NO_EXCEPT_FILLHauke Mehrtens
The kernel is loaded to 0x80001000 so there is some space left for the exception handlers and the kernel do not have to reserve some extra space for them. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4747/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15MIPS: BCM47XX: select BOOT_RAWHauke Mehrtens
All the boot loaders I have seen are booting the kernel in raw mode by default. CFE seems to support elf kernel images too, but the default case is raw for the devices I know of. Select this option to make the kernel boot on most of the devices with the default options. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4746/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15MIPS: BCM47XX: trim the nvram values for parsingHauke Mehrtens
Some nvram values on some devices have a newline character at the end of the value, that caused read errors. Trim the string before reading the number. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4745/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15MIPS: BCM47XX: add bcm47xx prefix in front of nvram function namesHauke Mehrtens
The nvram functions are exported and used by some normal drivers. To prevent name clashes with ofter parts of the kernel code add a bcm47xx_ prefix in front of the function names and the header file name. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4744/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15MIPS: BCM47XX: handle different nvram sizesHauke Mehrtens
The old code just worked for nvram with a size of 0x8000 bytes. This patch adds support for reading nvram from partitions of 0xF000 and 0x10000 bytes. There is just 32KB space for the nvram, but most devices do not use the full size and this code reads the first 32KB in that case and prints a warning. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4743/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15MIPS: BCM47XX: rename early_nvram_init to nvram_initHauke Mehrtens
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4742/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15MIPS: BCM47XX: nvram add nand flash supportHauke Mehrtens
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4741/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15MIPS: BCM47XX: return error when init of nvram failedHauke Mehrtens
This makes it possible to handle the case of not being able to read the nvram ram. This could happen when the code searching for the specific flash chip have not run jet. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4740/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15MIPS: BCM47XX: use common error codes in nvram readsHauke Mehrtens
Instead of using our own error codes use some common codes. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4739/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15MIPS: bcm47xx: separate functions finding flash window addrRafał Miłecki
Also check if parallel flash is present at all before accessing it and add support for serial flash on BCMA bus. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Acked-by: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: http://patchwork.linux-mips.org/patch/4738/ Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-14burying unused conditionalsAl Viro
__ARCH_WANT_SYS_RT_SIGACTION, __ARCH_WANT_SYS_RT_SIGSUSPEND, __ARCH_WANT_COMPAT_SYS_RT_SIGSUSPEND, __ARCH_WANT_COMPAT_SYS_SCHED_RR_GET_INTERVAL - not used anymore CONFIG_GENERIC_{SIGALTSTACK,COMPAT_RT_SIG{ACTION,QUEUEINFO,PENDING,PROCMASK}} - can be assumed always set.
2013-02-08Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/netDavid S. Miller
Synchronize with 'net' in order to sort out some l2tp, wireless, and ipv6 GRE fixes that will be built on top of in 'net-next'. Signed-off-by: David S. Miller <davem@davemloft.net>
2013-02-04arch Kconfig: Remove references to IRQ_PER_CPUJames Hogan
The IRQ_PER_CPU Kconfig symbol was removed in the following commit: Commit 6a58fb3bad099076f36f0f30f44507bc3275cdb6 ("genirq: Remove CONFIG_IRQ_PER_CPU") merged in v2.6.39-rc1. But IRQ_PER_CPU wasn't removed from any of the architecture Kconfig files where it was defined or selected. It's completely unused so remove the remaining references. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: <uclinux-dist-devel@blackfin.uclinux.org> Cc: <linux-mips@linux-mips.org> Cc: <linuxppc-dev@lists.ozlabs.org> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Fenghua Yu <fenghua.yu@intel.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: James E.J. Bottomley <jejb@parisc-linux.org> Cc: Helge Deller <deller@gmx.de> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Acked-by: Paul Mundt <lethal@linux-sh.org> Acked-by: Tony Luck <tony.luck@intel.com> Acked-by: Richard Kuo <rkuo@codeaurora.org> Link: http://lkml.kernel.org/r/1359972583-17134-1-git-send-email-james.hogan@imgtec.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2013-02-03mips: switch to generic sys_fork() and sys_clone()Al Viro
we still need the wrappers to store callee-saved registers in pt_regs, but once that done we can jump to kernel/fork.c variants. Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2013-02-03mips: take the "zero newsp means inherit the parent's one" to copy_thread()Al Viro
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2013-02-03mips: no magic arguments for sysm_pipe()Al Viro
current_pt_regs() works just fine Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2013-02-03mips: don't bother with compat_sys_futex() wrappersAl Viro
... it's COMPAT_SYSCALL_DEFINE now Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2013-02-03mips: switch to generic compat rt_sigaction()Al Viro
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2013-02-03mips: switch to generic compat sched_rr_get_interval()Al Viro
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2013-02-03mips: sigsuspend() is essentially the same as rt_sigsuspend() hereAl Viro
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2013-02-03mips: switch to generic compat rt_sigqueueinfo()Al Viro
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2013-02-03mips: switch to generic compat rt_sigpending()Al Viro
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2013-02-03mips: switch to generic compat rt_sigprocmask()Al Viro
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2013-02-03switch mips to generic rt_sigsuspend(), make it unconditionalAl Viro
mips was the last architecture not using the generic variant. Both native and compat variants switched to generic, which is made unconditional now. Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2013-02-03mips: switch to compat_sys_waitid()Al Viro
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2013-02-03mips: switch to generic sigaltstackAl Viro
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2013-02-03Merge commit '12890d0f61fc' into arch-mipsAl Viro
2013-02-03mips: use sane prototype for sys_rt_sigsuspend()Al Viro
we want to do that before branchpoint for arch-* to be able to consolidate sys_rt_sigsuspend() declarations. Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-03-17 07:13:08 +0000