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The device_type property is deprecated for the flattened device tree and
the value "ethernet-phy" has never been defined as having a useful
meaning. Neither the kernel nor u-boot depend on it. It should never
have appeared in PHY bindings. This patch removes all references to
"ethernet-phy" as a device_type value from the documentation and the
.dts files.
This patch was generated mechanically with the following command and
then verified by looking at the diff.
sed -i '/"ethernet-phy"/d' `git grep -l '"ethernet-phy"'`
Signed-off-by: Grant Likely <grant.likely@linaro.org>
Acked-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Add thermal monitor support to following boards:
P1022DS, MPC8536DS, P2041RDB, P3041DS, P4080DS, P5020DS, P5040DS
Signed-off-by: Jia Hongtao <B38951@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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In SGMII riser card different PHY chip are used with different external
IRQ from eTSEC. To support PHY link state auto detect in SGMII mode we
should add another group of PHY nodes for SGMII mode.
For MPC8572DS IRQ6 is used for PHY0~PHY1, IRQ7 is used for PHY2~PHY3.
For MPC8544DS and MPC8536DS IRQ6 is used for PHY0~PHY1.
For P2020DS IRQ5 is used for PHY1~PHY2.
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Jia Hongtao <B38951@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Add partitions for NOR and NAND Flash.
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Utilize new split between board & SoC, and new SoC device trees split
into pre & post utilizing 'template' includes for SoC IP blocks.
Other changes include:
* Moved to specifying interrupt-parent for mpic at root
* Moved to 4-cell mpic interrupt cells to support MPIC timers
* Added localbus node, but no chipselect details at this point
* Reworked PCIe nodes to allow supportin IRQs for controller (errors)
* and moved
PCI device IRQs down to virtual bridge level
* Moved mdio nodes up one level instead of under tsec nodes
* Added GPIO controller node to MPC8536 SoC template
[ marked as MPC8572 compatiable to get errata handling that applies ]
* Added missing cache-line-size & cache-size properties missing from
L2-cache node
* Added IP level IEEE 1588 / ptp timer node
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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