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The on-board NMI switch is routed through and mangled by the FPGA prior
to its delivery to the NMI pin, so add some glue for the various
configuration options. The default is to unmask it and enable all input
sources.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This ties in the 2KiB of FPGA SRAM in to the generic SRAM pool.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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The sdk7786 FPGA supports a number of user settable input switches that
are otherwise unused. This wires up a dummy gpio chip for the switch bank
to simply expose them to userspace.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This moves out the FPGA IRQ controller setup code to its own file, in
preparation for switching off of IRL mode and having it provide its own
irq_chip.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This does a bit of refactoring of the FPGA management code. The primary
FPGA initialization is moved out to its own file in preparation for
implementing some of the more complex capabilities, a complete set of
register definitions is provided, and all of the existing users in the
board code are moved over to use the new interface instead of setting up
overlapping mappings. This also corrects the FPGA size, which previously
was chomped off at the SDIF control register.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This stubs in some preliminary board support for the RTE SDK7786.
This is quite stunted at the moment, and primarily builds on top of the
system FPGA. FPGA IRQs are handled via CPU IRL masking for simplicity,
with initial peripheral support restricted to the debug ethernet.
Signed-off-by: Matt Fleming <matt@console-pimps.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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