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Follow the conversions as per the other subtypes.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This was accidentally dropped in the multiple vectors per irq conversion.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Update intc tables and platform data to use one linux irq
per maskable interrupt source instead of keeping the one-to-one
mapping between vectors and linux irqs.
This fixes potential irq masking issues for sh7763 hardware
blocks such as RTC/SCIF/DMAC/GETHER/PCIC5/MMCIF/SIM/GPIO/USBF.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This adds preliminary support for the SH7786-based Urquell board.
Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This adds preliminary support for the SH7786 CPU subtype.
While this is a dual-core CPU, only UP is supported for now. L2 cache
support is likewise not yet implemented.
More information on this particular CPU subtype is available at:
http://www.renesas.com/fmwk.jsp?cnt=sh7786_root.jsp&fp=/products/mpumcu/superh_family/sh7780_series/sh7786_group/
Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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With the recent entry.S refactoring, the SH-X3 path had a mov.l for a
register to register copy, resulting in:
AS arch/sh/kernel/cpu/sh4/../sh3/entry.o
arch/sh/kernel/cpu/sh4/../sh3/entry.S: Assembler messages:
arch/sh/kernel/cpu/sh4/../sh3/entry.S:366: Error: invalid operands for opcode
make[3]: *** [arch/sh/kernel/cpu/sh4/../sh3/entry.o] Error 1
Switch it over to a mov to fix it up.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Update intc tables and platform data to use one linux irq
per maskable interrupt source instead of keeping the one-to-one
mapping between vectors and linux irqs.
This fixes potential irq masking issues for sh7785 hardware
blocks such as SCIF/DMAC/PCIC5/MMCIF/GDTA/FLCTL/GPIO
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Tested-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Update intc tables and platform data to use one linux irq
per maskable interrupt source instead of keeping the one-to-one
mapping between vectors and linux irqs.
This fixes potential irq masking issues for sh7780 hardware
blocks such as SCIF/RTC/DMAC/PCIC5/MMCIF/FLCTL/GPIO
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Update intc tables and platform data to use one linux irq
per maskable interrupt source instead of keeping the one-to-one
mapping between vectors and linux irqs.
This fixes potential irq masking issues for sh775x hardware
blocks such as SCI/SCIF/RTC/DMAC/TMU2/REF.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Instead of keeping the single vector -> single linux irq mapping
we extend the intc code to support merging of vectors to a single
linux irq. This helps processors such as sh7750, sh7780 and sh7785
which have more vectors than masking ability. With this patch in
place we can modify the intc tables to use one irq per maskable
irq source. Please note the following:
- If multiple vectors share the same enum then only the
first vector will be available as a linux irq.
- Drivers may need to be rewritten to get pending irq
source from the hardware block instead of irq number.
This patch together with the sh7785 specific intc tables solves
DMA controller irq issues related to buggy interrupt masking.
Reported-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Fix iounmap() of pass-through P4 addresses. Without this patch
iounmap() on the sh7780 rtc area results in a warning message.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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The SH-3 does not support 'pref'-based prefetching, only SH-2A and SH-4A
parts do. Remove SH-3 from the list.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Prefetch early exception data. There is unused space in our
exception handler cache line anyway, so this is almost free.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Remove EXPEVT vector from the stack, lookup_exception_vector()
for sh3/sh4/sh4a is already using k2 to get the vector.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This patch reworks the sh3/sh4/sh4a register restore code in
the following ways:
- break out restore_regs() from restore_all()
- the register saving order is unchanged
- use restore_regs() in sh_bios_handler and restore_all
- document the function
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This patch reworks the sh3/sh4/sh4a register saving code in
the following ways:
- break out prepare_stack_save_dsp() from handle_exception()
- break out save_regs() from handle_exception()
- the register saving order is unchanged
- align new functions to fit in cache lines
- separate exception code from interrupt code
- keep main code flow in a single cache line per exception vector
- use bsr/rts for regular functions (save pr first)
- keep data in one shared cache line (exception_data)
- document the functions
- tie in the hp6xx code
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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The C99 specification states in section 6.11.5:
The placement of a storage-class specifier other than at the
beginning of the declaration specifiers in a declaration is an
obsolescent feature.
Signed-off-by: Tobias Klauser <tklauser@distanz.ch>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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None of the other platforms use this, and need individual porting.
Restrict it back to the supported set of CPU subtypes.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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GENERIC_TIME still depends on the clocksource bits being there, which is
presently not supported. This allows the CMT clockevent driver to be used
alongside alternate system timers that do not yet provide a clocksource
of their own (MTU2 and so on in the case of SH-2A).
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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CMT platform data for SuperH Mobile sh7723/sh7722/sh7343/sh7366.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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SuperH CMT clockevent driver.
Both 16-bit and 32-bit CMT versions are supported, but only 32-bit
is tested. This driver contains support for both clockevents and
clocksources, but no unregistration is supported at this point.
Works fine as clock source and/or event in periodic or oneshot mode.
Tested on sh7722 and sh7723, but should work with any cpu/architecture.
This version is lacking clocksource and early platform driver support
for now - this to minimize the amount of dependencies.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Handle the case with a sys_timer set to NULL.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Add TMU disable support so we can use other clockevents.
Also, setup the clockevent rating.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Rework and simplify the sched_clock and clocksource code. Instead
of registering the clocksource in a shared file we move it into the
tmu driver. Also, add code to handle sched_clock in the case of no
clocksource.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Fix macros start_thread and user_stack_pointer.
When these macros aren't called with a variable named regs as second
argument, this will result in a build failure.
Signed-off-by: Roel Kluin <roel.kluin@gmail.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Now that atomic_t is a generic opaque type for all architectures, it is
unwise to use intimate knowledge of its internals when manipulating it.
Instead of relying on the "counter" member being at offset 0 from the
beginning of an atomic_t, explicitly reference the member. This guards
us from any changes to the layout of the beginning of the atomic_t type.
Signed-off-by: Matt Fleming <matt@console-pimps.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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When dereferencing the memory address contained in a register and
modifying the value at that memory address, the register should not be
listed in the inline asm outputs. The value at the memory address is an
output (which is taken care of with the "memory" clobber), not the register.
Signed-off-by: Matt Fleming <matt@console-pimps.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This corrects a deadlock encountered on ap325 in the cases where the
mutex is contended and the slow-path needs to be fallen back upon.
Signed-off-by: Takashi YOSHII <yoshii.takashi@renesas.com>
Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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The T-bit manipulation for syscall error checking had the side effect of
spuriously returning ERESTART* errno values over EINTR. So, we simplify
the error checking a bit and leave the T-bit alone.
Reported-by: Kaz Kojima <kkojima@rr.iij4u.or.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This fixes a bug in the FPU exception handler for the FCNVDS instruction.
To get the register number the instruction is shifted right by 9,
though it should be shifted right by 8.
More information at ST Linux bugzilla:
https://bugzilla.stlinux.com/show_bug.cgi?id=4892
Signed-off-by: Giuseppe Di Giore <giuseppe.di-giore@st.com>
Signed-off-by: Carmelo Amoroso <carmelo.amoroso@st.com>
Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Signed-off-by: Chris Smith <chris.smith@st.com>
Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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In rare circumstances csum_partial() can be called with data which is
not 16 or 32 bit aligned. This is been observed with RPC calls for NFS
file systems for example. Add support for handling this without resorting
to the misaligned fixup code (which is why this hasn't been seen as a
problem). This mimics the i386 version, which has had this support for
some time.
Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This patch updates the ap325 defconfig to include
ov772x camera driver.
Old camera is still supported.
Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This patch add ov772x camera settings to ap325,
Old camera is still supported. And it will be 2nd camera
if you select ov772x and soc_camera_platform in same time.
Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This patch updates the Migo-R defconfig to include
ov772x camera and tw9910 video driver
Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Fix up the build for mach-highlander and mach-rsk. These operated on the
assumption that GENERIC_GPIO support with an optional GPIOLIB was
possible. This used to be true, but has not been the case since commit-id
d56cc8bc661ac1ceded8d45ba2d53bb134fee17d ("sh: use gpiolib"), where the
GENERIC_GPIO implementation was rewritten to use GPIOLIB directly.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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CPUs define pinmux tables through the optional interface, while boards
that require demux of their own require it explicitly. Roll the Makefile
rules back to depend on GENERIC_GPIO, which covers both cases.
Fixes a link error with an undefined reference to register_pinmux() on
optional platforms.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This patch updates the SuperH gpio code to make use of gpiolib. The
gpiolib callbacks get() and set() are lockless, but we use our own
spinlock for the other operations to make sure hardware register
bitfield accesses stay atomic.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This patch optimizes the gpio data register handling for gpio_set_value().
Instead of using the good old spinlock-plus-read-modify-write strategy
we now use a shadow register and atomic operations.
This improves the bitbanging mmc performance on Migo-R from 26 Kbytes/s
to 40 Kbytes/s.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This patch separates the register read and write functions to
allow lockless gpio_get_value().
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This patch modifies the table based SuperH gpio implementation to
make use of direct table lookups. With this change the functions
gpio_get_value() and gpio_set_value() are O(1).
Tested on Migo-R using bitbanging mmc. Performance is improved from
11 KBytes/s to 26 Kbytes/s.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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* 'i2c-for-linus' of git://jdelvare.pck.nerim.net/jdelvare-2.6:
i2c: Warn on deprecated binding model use
eeprom: More consistent symbol names
eeprom: Move 93cx6 eeprom driver to /drivers/misc/eeprom
spi: Move at25 (for SPI eeproms) to /drivers/misc/eeprom
i2c: Move old eeprom driver to /drivers/misc/eeprom
i2c: Move at24 to drivers/misc/eeprom
i2c: Quilt tree has moved
i2c: Delete many unused adapter IDs
i2c: Delete 10 unused driver IDs
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