| Age | Commit message (Expand) | Author |
|---|---|---|
| 2011-02-10 | x86: Adjust section placement in AMD northbridge related code | Jan Beulich |
| 2011-02-07 | x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUs | Hans Rosenfeld |
| 2011-01-26 | x86, amd: Extend AMD northbridge caching code to support "Link Control" devices | Hans Rosenfeld |
| 2011-01-26 | x86, amd: Enable L3 cache index disable on family 0x15 | Hans Rosenfeld |
| 2011-01-11 | x86: Use PCI method for enabling AMD extended config space before MSR method | Jan Beulich |
| 2010-11-18 | x86, cacheinfo: Cleanup L3 cache index disable support | Hans Rosenfeld |
| 2010-11-18 | x86, amd-nb: Cleanup AMD northbridge caching code | Hans Rosenfeld |
| 2010-11-18 | x86, amd-nb: Complete the rename of AMD NB and related code | Hans Rosenfeld |
| 2010-10-01 | x86, amd_nb: Enable GART support for AMD family 0x15 CPUs | Andreas Herrmann |
| 2010-09-20 | x86, k8: Rename k8.[ch] to amd_nb.[ch] and CONFIG_K8_NB to CONFIG_AMD_NB | Andreas Herrmann |
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