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2009-09-16m68knommu: clean up ColdFire 532x CPU timer setupGreg Ungerer
The newer ColdFire 532x family of CPU's uses the old timer, but has a newer interrupt controller. It doesn't need the special timer setup that was required when using the older interrupt controller. Remove the dead timer irq and level setting code, and define the hard coded vector. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-09-16m68knommu: simplify ColdFire "timers" clock initializationGreg Ungerer
The ColdFire "timers" clock setup can be simplified. There is really no need for the flexible per-platform setup code. The clock interrupt can be hard defined per CPU platform (in CPU include files). This makes the actual timer code simpler. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-09-16m68knommu: support code to mask external interrupts on old ColdFire CPU'sGreg Ungerer
The external interrupts used on the old Coldfire parts with the old style interrupt controller can be properly mask/unmasked in the interrupt handling code. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-09-16m68knommu: merge old ColdFire interrupt controller masking macrosGreg Ungerer
Currently the code that supports setting the old style ColdFire interrupt controller mask registers is macros in the include files of each of the CPU types. Merge all these into a set of real masking functions in the old Coldfire interrupt controller code proper. All the macros are basically the same (excepting a register size difference on really early parts). Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-09-16m68knommu: remove duplicate ColdFire mcf_autovector() codeGreg Ungerer
Each of the ColdFire CPU platform code that used the old style interrupt controller had its own copy of the mcf_autovector() function. They are all the same, remove them all and create a single function in the common coldfire/intc.c code. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-09-16m68knommu: move ColdFire INTC definitions to new include fileGreg Ungerer
Create an mcfintc.h include file with the definitions for the old style ColdFire interrupt controller. They are only needed on CPU's that use this old controller - so isolate them on their own. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-09-16m68knommu: mask off all interrupts in ColdFire intc-simr controllerGreg Ungerer
The ColdFire intc-simr interrupt controller should mask off all interrupt sources at init time. Doing it here instead of separately in each platform setup. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-09-16m68knommu: remove timer device interrupt setup for ColdFire 532xGreg Ungerer
With fully implemented interrupt controller code we don't need to do the custom interrupt setup for the timer device of the ColdFire 532x. Remove that code. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-09-16m68knommu: remove interrupt masking from ColdFire pit timerGreg Ungerer
With proper interrupt controller code in place there is no need for devices like the timers to have custom interrupt masking code. Remove it (and the defines that go along with it). Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-09-16m68knommu: remove unecessary interrupt level setting in ColdFire 520x setupGreg Ungerer
The new code for the interrupt controller in the ColdFire 520x takes care of all the interrupt controller setup. No manual config of the level registers (ICR) is required by the platform device setup code. So remove it. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-09-16m68knommu: remove the common interrupt controller structureGreg Ungerer
Each different m68knommu CPU interrupt controller type has its own interrupt controller data structures now. Remove the old, and now not used, common irq structs and init code from here. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-09-16m68knommu: complete interrupt controller code for the 68360 CPUGreg Ungerer
Define the interrupt controller structures along with the interrupt controller code for the 68360 CPU. This brings the interrupt setup and control into one place for this CPU family. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-09-16m68knommu: complete interrupt controller code for the 68328 CPU'sGreg Ungerer
Define the interrupt controller structures along with the interrupt controller code for the 68328 CPU family. This brings the interrupt setup and control into one place for this CPU family. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-09-16m68knommu: use common interrupt controller code for older ColdFire CPU'sGreg Ungerer
The old ColdFire CPU's (5206, 5307, 5407, 5249 etc) use a simple interrupt controller. Use common setup code for them. This addition means that all ColdFire CPU's now have some specific type of interrupt controller code. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-09-16m68knommu: clean up ColdFire 532x interrupt setupGreg Ungerer
With the common intc-simr interrupt controller code in place the ColdFire 532x family startup code can be greatly simplified. Remove all the interrupt masking code, and the per-device interrupt config here. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-09-16m68knommu: general interrupt controller for ColdFire 532x partsGreg Ungerer
The ColdFire 532x family of parts uses 2 of the same INTC interrupt controlers used in the ColdFire 520x family. So modify the code to support both parts. The extra code for the second INTC controler in the case of the 520x is easily optimized away to nothing. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-09-16m68knommu: clean up ColdFire 523x interrupt setupGreg Ungerer
With the common intc-2 interrupt controller code in place the ColdFire 523x family startup code can be greatly simplified. Remove all the interrupt masking code, and the per-device interrupt config here. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-09-16m68knommu: clean up ColdFire 528x interrupt setupGreg Ungerer
With the common intc-2 interrupt controller code in place the ColdFire 528x family startup code can be greatly simplified. Remove all the interrupt masking code, and the per-device interrupt config here. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-09-16m68knommu: clean up ColdFire 527x interrupt setupGreg Ungerer
With the common intc-2 interrupt controller code in place the ColdFire 527x family startup code can be greatly simplified. Remove all the interrupt masking code, and the per-device interrupt config here. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-09-16m68knommu: general interrupt controller for ColdFire many 52xx partsGreg Ungerer
Create general interrupt controller code for the many ColdFire version 2 cores that use the two region INTC interrupt controller. This includes the 523x family, 5270, 5271, 5274, 5275, and the 528x families. This code does proper masking and unmasking of interrupts. With this in place some of the driver hacks in place to support ColdFire interrupts can finally go away. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-09-16m68knommu: remove per device interrupt mask setting for ColdFire 520xGreg Ungerer
With general interrupt controller code in place we don't need specific unmasking code for the internal ColdFire 520x UARTs or ethernet (FEC). Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-09-16m68knommu: use general interrupt controller for ColdFire 520x familyGreg Ungerer
Create general interrupt controller code for the ColdFire 520x family, that does proper masking and unmasking of interrupts. With this in place some of the driver hacks in place to support ColdFire interrupts can finally go away. Within the ColdFire family there is a variety of different interrupt controllers in use. Some are used on multiple parts, some on only one. There is quite some differences in some varients, so much so that common code for all ColdFire parts would be impossible. This commit introduces code to support one of the newer interrupt controllers in the ColdFire 5208 and 5207 parts. It has very simple mask and unmask operations, so is one of the easiest to support. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-09-16m68k: clean up comment delimiters in dma.hGreg Ungerer
Change C99 style comments to traditional K&R style. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-09-16m68k: merge mmu and non-mmu versions of dma.hGreg Ungerer
The non-mmu version of dma.h contains a lot of ColdFire specific DMA support, but also all of the base m68k support. So use the non-mmu version of dma.h for all. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-09-16m68k: merge the mmu and non-mmu versions of checksum.hGreg Ungerer
The mmu and non-mmu versions of checksum.h are mostly the same, merge them. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-09-16m68k: merge mmu and non-mmu versions of irq.hGreg Ungerer
It is reasonably strait forward to merge the mmu and non-mmu versions of irq.h. Most of the defines and structs are not needed on non-mmu. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-09-16m68k: merge mmu and non-mmu versions of processor.hGreg Ungerer
The mmu and non-mmu versions of processor.h have a lot of common code. This is a strait forward merge. start_thread() could be improved, but that is not quite as strait forward, leaving for a follow on change. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-09-16m68knommu: convert to asm-generic/hardirq.hChristoph Hellwig
Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-09-16m68k: remove unused elia.h include fileGreg Ungerer
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-09-16arch/m68knommu/kernel/time.c: Remove unnecessary semicolonsJoe Perches
Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2009-09-15ARM: 5698/1: MMCI pass capabilities in platform dataLinus Walleij
This makes it possible to pass down the host controller capabilities for the MMCI driver using the platform data. It also provides the capabilties for the U300 implementation as an example, and makes sure the 4bit wide mode is set if this is requested by the ios() now that we can actually set that capability for a platform. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-09-15ARM: 5580/2: ARM TCM (Tightly-Coupled Memory) support v3Linus Walleij
This adds the TCM interface to Linux, when active, it will detect and report TCM memories and sizes early in boot if present, introduce generic TCM memory handling, provide a generic TCM memory pool and select TCM memory for the U300 platform. See the Documentation/arm/tcm.txt for documentation. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-09-15ARM: 5701/1: ARM: copy_page.S: take into account the size of the cache lineKirill A. Shutemov
Optimized version of copy_page() was written with assumption that cache line size is 32 bytes. On Cortex-A8 cache line size is 64 bytes. This patch tries to generalize copy_page() to work with any cache line size if cache line size is multiple of 16 and page size is multiple of two cache line size. After this optimization we've got ~25% speedup on OMAP3(tested in userspace). There is test for kernelspace which trigger copy-on-write after fork(): #include <stdlib.h> #include <string.h> #include <unistd.h> #define BUF_SIZE (10000*4096) #define NFORK 200 int main(int argc, char **argv) { char *buf = malloc(BUF_SIZE); int i; memset(buf, 0, BUF_SIZE); for(i = 0; i < NFORK; i++) { if (fork()) { wait(NULL); } else { int j; for(j = 0; j < BUF_SIZE; j+= 4096) buf[j] = (j & 0xFF) + 1; break; } } free(buf); return 0; } Before optimization this test takes ~66 seconds, after optimization takes ~56 seconds. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@nokia.com> Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-09-15ARM: 5700/1: ARM: Introduce ARM_L1_CACHE_SHIFT to define cache line sizeKirill A. Shutemov
Currently kernel believes that all ARM CPUs have L1_CACHE_SHIFT == 5. It's not true at least for CPUs based on Cortex-A8. List of CPUs with cache line size != 32 should be expanded later. Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-09-15ARM: 5696/1: Include device.h in VIC driverLinus Walleij
Currently build with the next head fails on archs using PL190 VIC because when we include amba/bus.h we need to include device.h first. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-09-15SFI: remove unneeded includesFeng Tang
Signed-off-by: Feng Tang <feng.tang@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
2009-09-15sfi: Remove unused codeThomas Gleixner
Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Feng Tang <feng.tang@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
2009-09-15[IA64] Clean up linker script using standard macros.Nelson Elhage
Aside from using fewer output sections and moving some data around, the main side effect of this change is changing the alignment of some sections. In particular: * cachline-aligned and read_mostly data are now aligned to SMP_CACHE_BYTES. (Previously, they were laid out consecutively after a PAGE_SIZE alignment) * .init.ramfs is now page-aligned, per the INIT_RAM_FS macro. (Previously it had no explicit alignment). Signed-off-by: Nelson Elhage <nelhage@ksplice.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
2009-09-15Merge branch 'next' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc * 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (134 commits) powerpc/nvram: Enable use Generic NVRAM driver for different size chips powerpc/iseries: Fix oops reading from /proc/iSeries/mf/*/cmdline powerpc/ps3: Workaround for flash memory I/O error powerpc/booke: Don't set DABR on 64-bit BookE, use DAC1 instead powerpc/perf_counters: Reduce stack usage of power_check_constraints powerpc: Fix bug where perf_counters breaks oprofile powerpc/85xx: Fix SMP compile error and allow NULL for smp_ops powerpc/irq: Improve nanodoc powerpc: Fix some late PowerMac G5 with PCIe ATI graphics powerpc/fsl-booke: Use HW PTE format if CONFIG_PTE_64BIT powerpc/book3e: Add missing page sizes powerpc/pseries: Fix to handle slb resize across migration powerpc/powermac: Thermal control turns system off too eagerly powerpc/pci: Merge ppc32 and ppc64 versions of phb_scan() powerpc/405ex: support cuImage via included dtb powerpc/405ex: provide necessary fixup function to support cuImage powerpc/40x: Add support for the ESTeem 195E (PPC405EP) SBC powerpc/44x: Add Eiger AMCC (AppliedMicro) PPC460SX evaluation board support. powerpc/44x: Update Arches defconfig powerpc/44x: Update Arches dts ... Fix up conflicts in drivers/char/agp/uninorth-agp.c
2009-09-15[IA64] Use standard macros for page-aligned data.Nelson Elhage
Signed-off-by: Nelson Elhage <nelhage@ksplice.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
2009-09-15Merge branch 'for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tj/percpu * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/percpu: (46 commits) powerpc64: convert to dynamic percpu allocator sparc64: use embedding percpu first chunk allocator percpu: kill lpage first chunk allocator x86,percpu: use embedding for 64bit NUMA and page for 32bit NUMA percpu: update embedding first chunk allocator to handle sparse units percpu: use group information to allocate vmap areas sparsely vmalloc: implement pcpu_get_vm_areas() vmalloc: separate out insert_vmalloc_vm() percpu: add chunk->base_addr percpu: add pcpu_unit_offsets[] percpu: introduce pcpu_alloc_info and pcpu_group_info percpu: move pcpu_lpage_build_unit_map() and pcpul_lpage_dump_cfg() upward percpu: add @align to pcpu_fc_alloc_fn_t percpu: make @dyn_size mandatory for pcpu_setup_first_chunk() percpu: drop @static_size from first chunk allocators percpu: generalize first chunk allocator selection percpu: build first chunk allocators selectively percpu: rename 4k first chunk allocator to page percpu: improve boot messages percpu: fix pcpu_reclaim() locking ... Fix trivial conflict as by Tejun Heo in kernel/sched.c
2009-09-15Nicolas Pitre has a new email addressNicolas Pitre
Due to problems at cam.org, my nico@cam.org email address is no longer valid. FRom now on, nico@fluxnic.net should be used instead. Signed-off-by: Nicolas Pitre <nico@fluxnic.net> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-09-15[IA64] Use .ref.text, not .text.init for start_ap.Tim Abbott
It seems that start_ap doesn't need to be in a special location in the kernel, but it references some init code so it should be in .ref.text. Since this is the only thing in the .text.head section, eliminate .text.head from the linker script. Signed-off-by: Tim Abbott <tabbott@ksplice.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
2009-09-15Merge branch 'x86-pat-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'x86-pat-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86, pat: Fix cacheflush address in change_page_attr_set_clr() mm: remove !NUMA condition from PAGEFLAGS_EXTENDED condition set x86: Fix earlyprintk=dbgp for machines without NX x86, pat: Sanity check remap_pfn_range for RAM region x86, pat: Lookup the protection from memtype list on vm_insert_pfn() x86, pat: Add lookup_memtype to get the current memtype of a paddr x86, pat: Use page flags to track memtypes of RAM pages x86, pat: Generalize the use of page flag PG_uncached x86, pat: Add rbtree to do quick lookup in memtype tracking x86, pat: Add PAT reserve free to io_mapping* APIs x86, pat: New i/f for driver to request memtype for IO regions x86, pat: ioremap to follow same PAT restrictions as other PAT users x86, pat: Keep identity maps consistent with mmaps even when pat_disabled x86, mtrr: make mtrr_aps_delayed_init static bool x86, pat/mtrr: Rendezvous all the cpus for MTRR/PAT init generic-ipi: Allow cpus not yet online to call smp_call_function with irqs disabled x86: Fix an incorrect argument of reserve_bootmem() x86: Fix system crash when loading with "reservetop" parameter
2009-09-15Merge branch 'x86-txt-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'x86-txt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86, intel_txt: clean up the impact on generic code, unbreak non-x86 x86, intel_txt: Handle ACPI_SLEEP without X86_TRAMPOLINE x86, intel_txt: Fix typos in Kconfig help x86, intel_txt: Factor out the code for S3 setup x86, intel_txt: tboot.c needs <asm/fixmap.h> intel_txt: Force IOMMU on for Intel TXT launch x86, intel_txt: Intel TXT Sx shutdown support x86, intel_txt: Intel TXT reboot/halt shutdown support x86, intel_txt: Intel TXT boot support
2009-09-15Merge branch 'agp-next' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/airlied/agp-2.6 * 'agp-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/agp-2.6: agp/intel: remove restore in resume agp: fix uninorth build intel-agp: Set dma mask for i915 agp: kill phys_to_gart() and gart_to_phys() intel-agp: fix sglist allocation to avoid vmalloc() intel-agp: Move repeated sglist free into separate function agp: Switch agp_{un,}map_page() to take struct page * argument agp: tidy up handling of scratch pages w.r.t. DMA API intel_agp: Use PCI DMA API correctly on chipsets new enough to have IOMMU agp: Add generic support for graphics dma remapping agp: Switch mask_memory() method to take address argument again, not page
2009-09-15[IA64] pci_br, fix infinite loop in find_free_ate()Jiri Slaby
When * there is almost out of ates * one asks for more than one ate * there are some available at the end of ate array then the inner for loop will end without incrementing 'index'. This means the outer loop will start at the same point finding it's available and runs the inner loop again from the same index. This repeats forever. Hence make sure we check we were at the end of ate array and return an error in such case. Signed-off-by: Jiri Slaby <jirislaby@gmail.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Found-by: Jeff Mahoney <jeffm@novell.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
2009-09-15x86: sched: Provide arch implementations using aperf/mperfPeter Zijlstra
APERF/MPERF support for cpu_power. APERF/MPERF is arch defined to be a relative scale of work capacity per logical cpu, this is assumed to include SMT and Turbo mode. APERF/MPERF are specified to both reset to 0 when either counter wraps, which is highly inconvenient, since that'll give a blimp when that happens. The manual specifies writing 0 to the counters after each read, but that's 1) too expensive, and 2) destroys the possibility of sharing these counters with other users, so we live with the blimp - the other existing user does too. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <new-submission> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-09-15x86: Add generic aperf/mperf codePeter Zijlstra
Move some of the aperf/mperf code out from the cpufreq driver thingy so that other people can enjoy it too. Cc: H. Peter Anvin <hpa@zytor.com> Cc: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Cc: Yanmin <yanmin_zhang@linux.intel.com> Cc: Dave Jones <davej@redhat.com> Cc: Len Brown <len.brown@intel.com> Cc: Yinghai Lu <yhlu.kernel@gmail.com> Cc: cpufreq@vger.kernel.org Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <new-submission> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-09-15x86: Move APERF/MPERF into a X86_FEATUREPeter Zijlstra
Move the APERFMPERF capacility into a X86_FEATURE flag so that it can be used outside of the acpi cpufreq driver. Cc: H. Peter Anvin <hpa@zytor.com> Cc: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Cc: Yanmin <yanmin_zhang@linux.intel.com> Cc: Dave Jones <davej@redhat.com> Cc: Len Brown <len.brown@intel.com> Cc: Yinghai Lu <yhlu.kernel@gmail.com> Cc: cpufreq@vger.kernel.org Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <new-submission> Signed-off-by: Ingo Molnar <mingo@elte.hu>