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2010-10-27ptrace: cleanup arch_ptrace() on avr32Namhyung Kim
use new 'datap' variable type of void pointer in order to remove unnecessary castings. Signed-off-by: Namhyung Kim <namhyung@gmail.com> Acked-by: Haavard Skinnemoen <hskinnemoen@atmel.com> Cc: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-10-27ptrace: cleanup arch_ptrace() on ARMNamhyung Kim
use new 'datap' variable in order to remove unnecessary castings. Signed-off-by: Namhyung Kim <namhyung@gmail.com> Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-10-27ptrace: cleanup arch_ptrace() on x86Namhyung Kim
Remove checking @addr less than 0 because @addr is now unsigned and use new udescp variable in order to remove unnecessary castings. [akpm@linux-foundation.org: fix unused variable 'udescp'] Signed-off-by: Namhyung Kim <namhyung@gmail.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-10-27ptrace: change signature of arch_ptrace()Namhyung Kim
Fix up the arguments to arch_ptrace() to take account of the fact that @addr and @data are now unsigned long rather than long as of a preceding patch in this series. Signed-off-by: Namhyung Kim <namhyung@gmail.com> Cc: <linux-arch@vger.kernel.org> Acked-by: Roland McGrath <roland@redhat.com> Acked-by: David Howells <dhowells@redhat.com> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-10-27fbmem: fix fb_read, fb_write unaligned accessesJames Hogan
fb_{read,write} access the framebuffer using lots of fb_{read,write}l's but don't check that the file position is aligned which can cause problems on some architectures which do not support unaligned accesses. Since the operations are essentially memcpy_{from,to}io, new fb_memcpy_{from,to}fb macros have been defined and these are used instead. For Sparc, fb_{read,write} macros use sbus_{read,write}, so this defines new sbus_memcpy_{from,to}io functions the same as memcpy_{from,to}io but using sbus_{read,write}b instead of {read,write}b. Signed-off-by: James Hogan <james@albanarts.com> Acked-by: David S. Miller <davem@davemloft.net> Acked-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-10-27tile: enable ARCH_DMA_ADDR_T_64BITFUJITA Tomonori
Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Acked-by: Chris Metcalf <cmetcalf@tilera.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-10-27mm: fix race in kunmap_atomic()Peter Zijlstra
Christoph reported a nice splat which illustrated a race in the new stack based kmap_atomic implementation. The problem is that we pop our stack slot before we're completely done resetting its state -- in particular clearing the PTE (sometimes that's CONFIG_DEBUG_HIGHMEM). If an interrupt happens before we actually clear the PTE used for the last slot, that interrupt can reuse the slot in a dirty state, which triggers a BUG in kmap_atomic(). Fix this by introducing kmap_atomic_idx() which reports the current slot index without actually releasing it and use that to find the PTE and delay the _pop() until after we're completely done. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Reported-by: Christoph Hellwig <hch@infradead.org> Acked-by: Rik van Riel <riel@redhat.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-10-27msm: timer: Decrease shift on timer clocksourceJeff Ohlstein
The shift of 24 causes the shift and multiply operation to sometimes overflow, resulting in incorrect timer values and poor performance. Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-10-27arm: mach-msm: fix error handling in msm_iommu_probe()Vasiliy Kulikov
msm_iommu_probe() didn't free mem_region and mapped IO. Also if request_mem_region() failed then error handling code dereferenced NULL pointer. Signed-off-by: Vasiliy Kulikov <segooon@gmail.com> Acked-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-10-27msm: fix Kconfig target board selectionDaniel Walker
This prevents build failures since it's currently possible to select 8x50, 7x30, or 7x00 without selecting a specific board. These changes just force a target selection, which is currently defaulting to the most common one (7x30 only has one). Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-10-27msm: fix compile failure on struct membank node memberDaniel Walker
In commit be370302742ff9948f2a42b15cb2ba174d97b930 "ARM: Remove DISCONTIGMEM support", it removed this "node" member which cased the following compile failure in mach-msm, linux/arch/arm/mach-msm/board-halibut.c: In function 'halibut_fixup': linux/arch/arm/mach-msm/board-halibut.c:86: error: 'struct membank' has no member named 'node' linux/arch/arm/mach-msm/board-halibut.c:86: error: implicit declaration of function 'PHYS_TO_NID' I've removed the access to the node member which corrects the compile failure. Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-10-27ARM: fix memblock breakageRussell King
Will says: | Commit e63075a3 removed the explicit MEMBLOCK_REAL_LIMIT #define | and introduced the requirement that arch code calls | memblock_set_current_limit to ensure that the __va macro can | be used on physical addresses returned from memblock_alloc. Unfortunately, ARM was missed out of this change. Fix this. Reported-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-10-27ARM: 6465/1: Fix data abort accessing proc_info from __lookup_processor_typeTony Lindgren
Commit 5085f3ff458521045f7e43da62b8c30ea7df2e82 added better support for CONFIG_HOTPLUG_CPU by keeping proc_info around. However, depending on the Kconfig options selected, this can make the booting fail mysteriously early on. Turns out a data abort can happen in __lookup_processor in ldmia r5 {r3, r4}. When it happens the address loaded to r5 is not aligned. Fix the problem by aligning proc_info. Reported-by: Anand Gadiyar <gadiyar@ti.com> Tested-by: Anand Gadiyar <gadiyar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-10-27ARM: 6460/1: ixp2000: fix type of ixp2000_timer_interruptUwe Kleine-König
This fixes a build warning existing since at least 2.6.30: arch/arm/mach-ixp2000/core.c:217: warning: initialization from incompatible pointer type Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-10-27ARM: 6449/1: Fix for compiler warning of uninitialized variable.Marcelo Roberto Jimenez
ARM: mach-sa1100: Fix for compiler warning of uninitialized variable. This is a fix for the compiler warning: 'new_ppcr' may be used uninitialized in this function. Signed-off-by: Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-10-27ARM: 6445/1: fixup TCM memory typesLinus Walleij
After Santosh's fixup of the generic MT_MEMORY and MT_MEMORY_NONCACHED I add this fix to the TCM memory types. The main change is that the ITCM memory is L_PTE_WRITE and DOMAIN_KERNEL which works just fine. The changed to the DTCM is just cosmetic to fit with surrounding code. Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Rickard Andersson <rickard.andersson@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-10-27MN10300: Save frame pointer in thread_info struct rather than global varDavid Howells
Save the current exception frame pointer in the thread_info struct rather than in a global variable as the latter makes SMP tricky, especially when preemption is also enabled. This also replaces __frame with current_frame() and rearranges header file inclusions to make it all compile. Signed-off-by: David Howells <dhowells@redhat.com> Acked-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com>
2010-10-27MN10300: Change "Matsushita" to "Panasonic".Akira Takeuchi
Change externally visible "Matsushita" instances to "Panasonic" throughout the MN10300 arch code. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Create a defconfig for the ASB2364 boardAkira Takeuchi
Create a defconfig for the ASB2364 board. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Update the ASB2303 defconfigAkira Takeuchi
Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: ASB2364: Add support for SMSC911X and SMC911XAkira Takeuchi
Add support for SMSC911X and SMC911X for the ASB2364 unit. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com> cc: steve.glendinning@smsc.com cc: netdev@vger.kernel.org
2010-10-27MN10300: ASB2364: Handle the IRQ multiplexer in the FPGADavid Howells
Handle the IRQ multiplexer in the FPGA by implementing a cascade interrupt driver for it. Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Generic time supportMark Salter
Implement generic time support for MN10300. Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Specify an ELF HWCAP flag for MN10300 Atomic Operations Unit supportMark Salter
Use an ELF HWCAP flag to indicate to the process that the CPU provides LL/SC equivalent atomic operations unit support in addition to BSET/BCLR. Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Map userspace atomic op regs as a vmalloc pageMark Salter
The AM34 processor has an atomic operation that's the equivalent of LL/SC on other architectures. However, rather than being done through a pair of instructions, it's driven by writing to a pair of memory-mapped CPU control registers. One set of these registers (AARU/ADRU/ASRU) is available for use by userspace, but for userspace to access them a PTE must be set up to cover the region. This is done by dedicating the first vmalloc region page to this purpose, setting the permissions on its PTE such that userspace can access the page. glibc is hardcoded to expect the registers to be there. The way atomic ops are done through these registers is straightforward: (1) Write the address of the word you wish to access into AARU. This causes the CPU to go and fetch that word and load it into ADRU. The status bits are also cleared in ASRU. (2) The current data value is read from the ADRU register and modified. (3) To alter the data in RAM, the revised data is written back to the ADRU register, which causes the CPU to attempt to write it back. (4) The ASRU.RW flag (ASRU read watch), ASRU.LW flag (bus lock watch), ASRU.IW (interrupt watch) and the ASRU.BW (bus error watch) flags then must be checked to confirm that the operation wasn't aborted. If any of the watches have been set to true, the operation was aborted. Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: And Panasonic AM34 subarch and implement SMPAkira Takeuchi
Implement the Panasonic MN10300 AM34 CPU subarch and implement SMP support for MN10300. Also implement support for the MN2WS0060 processor and the ASB2364 evaluation board which are AM34 based. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Delete idle_timestamp from irq_cpustat_tAkira Takeuchi
Delete idle_timestamp from irq_cpustat_t as it's an unread relic. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Make various interrupt priority settings configurableAkira Takeuchi
Make the settings of interrupt priorities used by various services configurable at run time. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Optimise do_csum()Akira Takeuchi
Optimise do_csum() to gang up the loads so they're less likely to get interruptions between. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Implement atomic ops using atomic ops unitMark Salter
Implement atomic ops using the atomic ops unit available in the AM34 CPU. This allows the equivalent of the LL/SC instructions to be found on other CPUs. Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Make the FPU operate in non-lazy mode under SMPAkira Takeuchi
Make the FPU operate in non-lazy mode under SMP so that when the process that is currently using the FPU migrates to a different CPU, we don't have to ping its previous CPU to flush the FPU context. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: SMP TLB flushingAkira Takeuchi
Implement global TLB flushing for MN10300. This will be used by the AM34 which is SMP capable. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Use the [ID]PTEL2 registers rather than [ID]PTEL for TLB controlAkira Takeuchi
Use the [ID]PTEL2 registers rather than [ID]PTEL for TLB control as the bits are a more suitable layout. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Make the use of PIDR to mark TLB entries controllableAkira Takeuchi
Make controllable the use of the PIDR register to mark TLB entries as belonging to particular processes. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Rename __flush_tlb*() to local_flush_tlb*()David Howells
Rename __flush_tlb*() to local_flush_tlb*() as it's more appropriate, and ready to differentiate local from global TLB flushes when SMP is introduced. Whilst we're at it, get rid of __flush_tlb_global() and make local_flush_tlb_page() take an mm_struct pointer rather than VMA pointer. Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: AM34 erratum requires MMUCTR read and write on exception entryAkira Takeuchi
An AM34 erratum requires MMUCTR read and write on entry to certain exceptions, prior to EPSW.NMID being cleared to allow NMIs to happen. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Make the boot wrapper able to use writeback cachingAkira Takeuchi
Make the boot wrapper able to use writeback caching, including flushing the cache before jumping to the main kernel. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Cache: Implement SMP global cache flushingAkira Takeuchi
Implement SMP global cache flushing for MN10300. This will be used by the AM34 which is SMP capable. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Allow some cacheflushes to be avoided if cache snooping is availableDavid Howells
The AM34 core is able to do cache snooping, and so can skip some of the cache flushing. Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: AM34: Add cacheflushing by using the AM34 purge registersAkira Takeuchi
The AM34 CPU core provides an automated way of purging the cache rather than manually iterating over all the tags in the cache. Make it possible to use these. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: SMP: Differentiate local cache flushingAkira Takeuchi
Differentiate local cache flushing from global cache flushing so that they can be done differently on SMP systems. Rename the cache functions from: mn10300_[id]cache_*() to: mn10300_[id]_localcache_*() and on a UP system, assign the global labels to the local labels. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Cacheflush functions should take unsigned long addressesAkira Takeuchi
The functions that perform cache flushing should take addresses of unsigned long type, not unsigned int. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: AM34: The current cacheflush routines operate by controlling tag regsDavid Howells
The current cache flush and invalidate routines operate by controlling the cache tag registers. Rename the files and add config items to select them. This makes it easier to support the use of other cache flush methods instead, such as the use of AM34's area purge registers, if available. Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Reorder asm/cacheflush.h to put primitives firstDavid Howells
Reorder asm/cacheflush.h to put arch primitives first, before the main functions so that the main functions can be inline asm rather than #defines when non-trivial. Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Provide a MN10300_CACHE_ENABLED config optionDavid Howells
Provide a MN10300_CACHE_ENABLED config option as inverted logic of MN10300_CACHE_DISABLED to make things simpler. Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Cache: Split cache bits out of arch KconfigDavid Howells
Split the cache bits out of arch/mn10300/Kconfig as they're quite complex. Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Remove monitor/JTAG functionsAkira Takeuchi
Remove the monitor trap function and the set_jtag_stub function as they're not really necessary. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Add CPU register bits for AM34Akira Takeuchi
Add CPU register declarations for the AM34 subarch. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Don't hard code the cacheline size in register defsAkira Takeuchi
Don't hard code the cacheline size in the cache control register definitions. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Move DMA engine control reg defs to MN103E010 processor directoryAkira Takeuchi
Move the DMA engine control register definitions to the MN103E010 processor directory so that the MN2WS0050 processor can have its own. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>