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Introduce a scan treshold for the qdio outbound queues. By setting the
threshold the driver can tell qdio after how much used SBALs qdio
should schedule the outbound tasklet that scans the queue for finished
SBALs. The threshold is specific by the drivers because a
Hipersockets device is much faster in utilizing outbound buffers than a
ZFCP or OSA device.
The default values after how many used SBALs the tasklet should run are:
OSA: > 31 SBALs
Hipersockets: > 7 SBALs
zfcp: > 55 SBALs
Signed-off-by: Jan Glauber <jang@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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Currently the buffer for diagnose data is allocated in the open function
of the debugfs file and is released in the close function. This has the
drawback that a user (root) can pin that memory by not closing the file.
This patch moves the buffer allocation to the read function. The buffer is
automatically released after the buffer is copied to userspace.
Signed-off-by: Michael Holzheu <holzheu@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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Use thread_info lowcore field for current_thread_info(), saves
an unnecessary calculation.
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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Get rid of register/unregister_early_external_interrupt() and clean up
the code while at it.
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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Use an early init call to initialize pfault. That way it is possible to
use the register_external_interrupt() instead of the early variant.
No need to enable pfault any earlier since it has only effect if user
space processes are running.
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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Add support for AP Bus I/O interrupt statistics in /proc/interrupts.
Signed-off-by: Holger Dengler <hd@linux.vnet.ibm.com>
Signed-off-by: Felix Beck <felix.beck@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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Add support for CTC I/O interrupt statistics in /proc/interrupts.
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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Add support for CLAW I/O interrupt statistics in /proc/interrupts.
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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Add support for LCS I/O interrupt statistics in /proc/interrupts.
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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Add support for VMUR I/O interrupt statistics in /proc/interrupts.
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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Add support for ccw based tape I/O interrupt statistics in /proc/interrupts.
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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Add support for 3270 I/O interrupt statistics in /proc/interrupts.
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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Add support for 3215 I/O interrupt statistics in /proc/interrupts.
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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Add support for DASD I/O interrupt statistics in /proc/interrupts.
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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Count traditional qdio interrupts and adapter interrupts for qdio
in the interrupt statistics.
Signed-off-by: Jan Glauber <jang@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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Up to now /proc/interrupts only has statistics for external and i/o
interrupts but doesn't split up them any further.
This patch adds a line for every single interrupt source so that it
is possible to easier tell what the machine is/was doing.
Part of the output now looks like this;
CPU0 CPU2 CPU4
EXT: 3898 4232 2305
I/O: 782 315 245
CLK: 1029 1964 727 [EXT] Clock Comparator
IPI: 2868 2267 1577 [EXT] Signal Processor
TMR: 0 0 0 [EXT] CPU Timer
TAL: 0 0 0 [EXT] Timing Alert
PFL: 0 0 0 [EXT] Pseudo Page Fault
[...]
NMI: 0 1 1 [NMI] Machine Checks
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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Let local_tick_enable/disable() reprogram the clock comparator so the
function names make semantically more sense.
Also that way the functions are more symmetric since normally each
local_tick_enable() call usually would have a subsequent call to
set_clock_comparator() anyway.
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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Move the two functions to timex.h where they make more sense than in
hardirq.h.
No functional change.
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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Add kprobes annotations to get the massive 'probe kernel.function("*") {}'
stress test working.
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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Correct some minor coding style issues.
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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Restructure the kprobe breakpoint handler function. Add comments to
make it more comprehensible and add a sanity check for re-entering
kprobes.
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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Register %r14 and %r15 are already stored in jprobe_saved_regs, no need
to store them a second time in jprobe_saved_r14 / jprobe_saved_r15.
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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The s390 architecture can execute code on kmalloc/vmalloc memory.
No need for the __ARCH_WANT_KPROBES_INSN_SLOT detour.
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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Replace set_current_kprobe/reset_current_kprobe/save_previous_kprobe/
restore_previous_kprobe with a simpler scheme push_kprobe/pop_kprobe.
The mini kprobes stack can store up to two active kprobes.
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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Determine instruction fixup details in resume_execution, no need to do
it beforehand. Remove fixup, ilen and reg from arch_specific_insn.
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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Move the definition of the helper structure ins_replace_args to the
only place where it is used and drop the old member as it is not needed.
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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The saved interrupt mask and the saved control registers are only
relevant while single stepping is set up. A secondary kprobe while
kprobe single stepping is active may not occur. That makes is safe
to remove the save and restore of kprobe_saved_imask / kprobe_save_ctl
from save_previous_kprobe and restore_previous_kprobe.
Move all single step related code to two functions, enable_singlestep
and disable_singlestep.
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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Remove special case of a kprobe on a breakpoint while a relocated
instruction is single stepped. The only instruction that may cause
a fault while kprobe single stepping is active is the relocated
instruction. There is no kprobe on the instruction slot retrieved
with get_insn_slot().
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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Make use of def_bool and def_tristate where possible and add sensible
defaults to the config symbols where applicable. This shortens the
defconfig file by another ~40 lines.
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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Add a sched_clock() implementation to Versatile Express using the new
sched_clock() infrastructure for extending 32bit counters to full
64-bit nanoseconds.
Tested-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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devel-stable
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master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6
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rmobile-latest
Conflicts:
arch/arm/mach-shmobile/Kconfig
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Prepare the ap4evb board for the MIPI DSI driver transition to support
different register layouts.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Now, that the MIPI DSI driver implements runtime PM, we don't need anymore to
configure clocks statically in the platform code. This patch also adds a DSITX1
clock definition for sh7372 and attaches PHY clocks to respective devices.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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sh73a0 has divisor[12] setting as 1/7 on FRQCRA.
Signed-off-by: Takashi YOSHII <takashi.yoshii.zj@renesas.com>
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Add VGA camera support to the Mackerel board
using soc_camera_platform.
The VGA camera module is hooked up using the
8-bit CEU bus, and it is constantly bursting
out frames in fixed video mode setting. The
camera module does not allow any I2C control.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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A definition like:
#define regs_return_value(regs) ((regs)->regs[0])
called with regs_return_value(foo) will be preprocessed to:
((foo)->foo[0])
^^^
So to fix this to ensure the preprocessor compiles such calls correctly.
Signed-off-by: Roel Kluin <roel.kluin@gmail.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Gcc has deprecated the use of the following ColdFire cpu options:
-m5206e, -m528x, -m5307 and -m5407. In there place we should use
the equivilent -mcpu= option and setting.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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Replace 8 spaces, or even 7, by TAB at begin of lines.
Signed-off-by: Philippe De Muyter <phdm@macqel.be>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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Create separate functions to deal with instruction and data cache flushing.
This way we can optimize them for the vairous cache types and arrangements
used across the ColdFire family.
For example the unified caches in the version 3 cores means we don't
need to flush the instruction cache. For the version 2 cores that do
not do data cacheing (or where we choose instruction cache only) we
don't need to do any data flushing.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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The version 3 and version 4 ColdFire cache controllers support both
write-through and copy-back modes on the data cache. Allow for Kconfig
time configuration of this, and set the cache mode appropriately.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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The newer version 2 ColdFire CPU cores support a configurable cache
arrangement. The cache memory can be used as all instruction cache, all
data cache, or split in half for both instruction and data caching.
Support this setup via a Kconfig time menu that allows a kernel builder
to choose the arrangement they want to use.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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Currently the code to push cache lines is only available to version 4
cores. Version 3 cores may also need to use this if we support copy-
back caches on them. Move this code to make it more generic, and
useful for all version ColdFire cores.
With this in place we can now have a single cache_flush_all() code
path that does all the right things on all version cores.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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The cache control code for the ColdFire CPU's is a big ugly mess
of "#ifdef"ery liberally coated with bit constants. Clean it up.
The cache controllers in the various ColdFire parts are actually quite
similar. Just differing in some bit flags and options supported. Using
the header defines now in place it is pretty easy to factor out the
small differences and use common setup and flush/invalidate code.
I have preserved the cache setups as they where in the old code
(except where obviously wrong - like in the case of the 5249). Following
from this it should be easy now to extend the possible setups used on
the CACHE controllers that support split cacheing or copy-back or
write through options.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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Move the inclusion of the version 4 cache controller registers so that
it is with all the other register bit flag definitions. This makes it
consistent with the other version core inclusion points, and means we
don't need "#ifdef"ery in odd-ball places for these definitions.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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All version 3 based ColdFire CPU cores have a similar cache controller.
Merge all the exitsing definitions into a single file, and make them
similar in style and naming to the existing version 2 and version 4
cache controller definitions.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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The version 2 ColdFire CPU based cores all contain a similar cache
controller unit. Create a set of bit flag definitions for the supporting
registers.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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The empty __iounmap() function is not used on m68knommu at all.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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