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2013-08-25ARM: 7822/1: add workaround for ambiguous C99 stdint.h typesArd Biesheuvel
The C99 types uintXX_t that are usually defined in 'stdint.h' are not as unambiguous on ARM as you would expect. For the types below, there is a difference on ARM between GCC built for bare metal ARM, GCC built for glibc and the kernel itself, which results in build errors if you try to build with -ffreestanding and include 'stdint.h' (such as when you include 'arm_neon.h' in order to use NEON intrinsics) As the typedefs for these types in 'stdint.h' are based on builtin defines supplied by GCC, we can tweak these to align with the kernel's idea of those types, so 'linux/types.h' and 'stdint.h' can be safely included from the same source file (provided that -ffreestanding is used). int32_t uint32_t uintptr_t bare metal GCC long unsigned long unsigned int glibc GCC int unsigned int unsigned int kernel int unsigned int unsigned long Acked by: Dave Martin <dave.martin@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-08-25[media] ARM: shmobile: Marzen: enable VIN and ADV7180 in defconfigVladimir Barinov
Add the VIN and ADV7180 drivers to 'marzen_defconfig'. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
2013-08-25[media] ARM: shmobile: Marzen: add VIN and ADV7180 supportVladimir Barinov
Add ADV7180 platform devices on the Marzen board, configure VIN1/3 pins, and register VIN1/3 devices with the ADV7180 specific platform data. [Sergei: removed superfluous tabulation and inserted empty lines in the macro definition, updated the copyrights, annotated VIN platform data as '__initdata'] Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
2013-08-25[media] ARM: shmobile: r8a7779: add VIN supportVladimir Barinov
Add VIN clocks and platform devices for R8A7779 SoC; add function to register the VIN platform devices. [Sergei: added 'id' parameter check to r8a7779_add_vin_device(), used '*pdata' in *sizeof* operator there, renamed some variables, annotated vin[0-3]_resources [] and 'vin[0-3]_info' as '__initdata'.] Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
2013-08-24sh: ecovec24: Remove MMCIF and SDHI .set_pwr() callbacksLaurent Pinchart
The MMCIF and SHDI platform data .set_pwr() callbacks are used to control the vmmc/vqmmc power supplies. As the power supplies already register control GPIOs there's no need to perform the operation manually. Remove the callback functions. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Chris Ball <cjb@laptop.org>
2013-08-24sh: ecovec24: Remove mmcif .down_pwr() callbackLaurent Pinchart
The callback isn't used by the mmcif driver, don't initialize it in board code. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Chris Ball <cjb@laptop.org>
2013-08-24sh: ecovec24: Use MMC/SDHI CD and RO GPIOLaurent Pinchart
Pass the CD and RO GPIO numbers to the MMC SPI and SDHI drivers and remove the custom .get_cd() and .get_ro() callback functions. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Chris Ball <cjb@laptop.org>
2013-08-24ARM: ep93xx: vision_ep9307: Use MMC CD and RO GPIOLaurent Pinchart
Pass the CD and RO GPIO numbers to the MMC SPI driver and remove the custom .get_cd() and .get_ro() callback functions. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2013-08-24ARC: [lib] strchr breakage in Big-endian configurationJoern Rennecke
For a search buffer, 2 byte aligned, strchr() was returning pointer outside of buffer (buf - 1) ------------->8---------------- // Input buffer (default 4 byte aigned) char *buffer = "1AA_"; // actual search start (to mimick 2 byte alignment) char *current_line = &(buffer[2]); // Character to search for char c = 'A'; char *c_pos = strchr(current_line, c); printf("%s\n", c_pos) --> 'AA_' as oppose to 'A_' ------------->8---------------- Reported-by: Anton Kolesov <Anton.Kolesov@synopsys.com> Debugged-by: Anton Kolesov <Anton.Kolesov@synopsys.com> Cc: <stable@vger.kernel.org> # [3.9 and 3.10] Cc: Noam Camus <noamc@ezchip.com> Signed-off-by: Joern Rennecke <joern.rennecke@embecosm.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2013-08-24ARM: mmp: avoid to include head file in mach-mmpHaojian Zhuang
pxa910_set_wake() & mmp2_set_wake() are both declared in head files of arch/arm/mach-mmp/include/mach directory. If we include these head files in irq-mmp driver, it blocks the multiplatform build. So adjust the code. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
2013-08-24irqchip: mmp: support irqchipHaojian Zhuang
Support IRQCHIP & CONFIG_MULTI_IRQ_HANDLER in irq-mmp driver. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com> Reviewed-by: Daniel Drake <dsd@laptop.org>
2013-08-24irqchip: move mmp irq driverHaojian Zhuang
Move irq-mmp driver from mach-mmp directory into irqchip directory. It's used to support multiple platform. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
2013-08-24[media] ARM: shmobile: BOCK-W: enable VIN and ML86V7667 in defconfigVladimir Barinov
Add the VIN and ML86V7667 drivers to 'bockw_defconfig'. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
2013-08-24[media] ARM: shmobile: BOCK-W: add VIN and ML86V7667 supportVladimir Barinov
Add ML86V7667 platform devices on BOCK-W board, configure VIN0/1 pins, and register VIN0/1 devices with the ML86V7667 specific platform data. [Sergei: some macro/comment cleanup; updated the copyrights, removed duplicate 'sh_eth' driver being enabled before registering VIN1 due to a pin conflict, removed superfluous semicolon after iclink[01]_ml86v7667' initializer.] Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
2013-08-24[media] ARM: shmobile: r8a7778: add VIN supportVladimir Barinov
Add VIN clocks and platform devices on R8A7778 SoC; add function to register the VIN platform devices. [Sergei: added 'id' parameter check to r8a7778_add_vin_device(), used '*pdata' in *sizeof* operator, and added an empty line there; renamed some variables, annotated 'vin[01]_info' and vin[01]_resources[] as '__initdata'.] Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
2013-08-23powerpc/85xx: Add C293PCIE board supportMingkai Hu
C293PCIE board is a series of Freescale PCIe add-in cards to perform as public key crypto accelerator or secure key management module. - 512KB platform SRAM in addition to 512K L2 Cache/SRAM - 512MB soldered DDR3 32bit memory - CPLD System Logic - 64MB x16 NOR flash and 4GB x8 NAND flash - 16MB SPI flash Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Po Liu <Po.Liu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2013-08-23powerpc/85xx: Add silicon device tree for C293Mingkai Hu
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Po Liu <Po.Liu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2013-08-23powerpc/85xx: Add SEC6.0 device treeMingkai Hu
Add device tree for SEC 6.0 used on C29x silicon. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Po Liu <Po.Liu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2013-08-23powerpc: add Book E support to 64-bit hibernationWang Dongsheng
Update the 64-bit hibernation code to support Book E CPUs. Some registers and instructions are not defined for Book3e (SDR reg, tlbia instruction). SDR: Storage Description Register. Book3S and Book3E have different address translation mode, we do not need HTABORG & HTABSIZE to translate virtual address to real address. More registers are saved in BookE-64bit.(TCR, SPRG1) Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2013-08-23powerpc/85xx: Add P1023RDB board supportChunhe Lan
P1023RDB Specification: ----------------------- Memory subsystem: 512MB DDR3 (Fixed DDR on board) 64MB NOR flash 128MB NAND flash Ethernet: eTSEC1: Connected to Atheros AR8035 GETH PHY eTSEC2: Connected to Atheros AR8035 GETH PHY PCIe: Three mini-PCIe slots USB: Two USB2.0 Type A ports I2C: AT24C08 8K Board EEPROM (8 bit address) Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2013-08-23powerpc/85xx: Add support for 85xx cpu type detectionHaijun.Zhang
Add this file to help detect cpu type in runtime. These macros will be more favorable for driver to apply errata and workaround to specified cpu type. Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2013-08-24dts: mpc512x: prepare for preprocessor supportGerhard Sittig
prepare C preprocessor support when processing MPC512x DTS files - switch from DTS syntax to CPP syntax for include specs - create a symlink such that DTS processing can reference includes Signed-off-by: Gerhard Sittig <gsi@denx.de> Signed-off-by: Anatolij Gustschin <agust@denx.de>
2013-08-23powerpc: mpc512x: array decl for MCLK registers in CCMGerhard Sittig
reword the clock control module's registers declaration such that the MCLK related registers form an array and get indexed by PSC controller or CAN controller component number this change is in preparation to COMMON_CLK support for the MPC512x platform, the changed declaration remains neutral to existing code since the PSC and MSCAN CCR fields declared here aren't referenced elsewhere Signed-off-by: Gerhard Sittig <gsi@denx.de> Signed-off-by: Anatolij Gustschin <agust@denx.de>
2013-08-23Merge tag 'mxs-soc-3.12' of git://git.linaro.org/people/shawnguo/linux-2.6 ↵Kevin Hilman
into next/soc From Shawn Guo: It contains mxs soc changes for 3.12. - Run savedefconfig on mxs_defconfig to clean it up - Fix on mxs_restart() routine for interrupt context calling - A few other random updates and cleanups * tag 'mxs-soc-3.12' of git://git.linaro.org/people/shawnguo/linux-2.6: ARM: mxs: pm: Include "pm.h" ARM: mxs: Simplify detection of CrystalFontz boards ARM: mach-mxs: Remove "TO" string from revision field ARM: mxs: Fix BUG() when invoking mxs_restart() from interrupt context ARM: mxs: Allow DT clock providers ARM: mxs_defconfig: Cleanup mxs_defconfig
2013-08-23Merge tag 'imx-dt-3.12' of git://git.linaro.org/people/shawnguo/linux-2.6 ↵Kevin Hilman
into next/soc From Shawn Guo: It contains the imx device tree updates for 3.12. - New pinctrl entry additions for various peripherals - Devices enabling for imx6, imx5 and imx27 boards - Add missing device nodes like iim, owire, audmux and sram, etc. - Various updates on boards like phytec, wandboard and sabresd - Consolidate pad macros between imx6q and imx6dl * tag 'imx-dt-3.12' of git://git.linaro.org/people/shawnguo/linux-2.6: (92 commits) ARM: dts: vf610-twr: enable i2c0 device ARM: dts: i.MX51: Add one more I2C2 pinmux entry ARM: dts: i.MX51: Move pins configuration under "iomuxc" label ARM: dtsi: imx6qdl-sabresd: Add USB OTG vbus pin to pinctrl_hog ARM: dtsi: imx6qdl-sabresd: Add USB host 1 VBUS regulator ARM: dts: imx27-phytec-phycore-som: Enable AUDMUX ARM: dts: i.MX27: Disable AUDMUX in the template ARM: dts: wandboard: Add support for SDIO bcm4329 ARM: i.MX5 clocks: Remove optional clock setup (CKIH1) from i.MX51 template ARM: dts: imx53-qsb: Make USBH1 functional ARM i.MX6Q: dts: Enable I2C1 with EEPROM and PMIC on Phytec phyFLEX-i.MX6 Ouad module ARM i.MX6Q: dts: Enable SPI NOR flash on Phytec phyFLEX-i.MX6 Ouad module ARM: dts: imx6qdl-sabresd: Add touchscreen support ARM: imx: add ocram clock for imx53 ARM: dts: imx: ocram size is different between imx6q and imx6dl ARM: dts: imx27-phytec-phycore-som: Fix regulator settings ARM: dts: i.MX27: Remove clock name from CPU node ARM: dts: i.MX27: Increase "clock-latency" value ARM: dts: i.MX27: Add label to CPU node ARM: dts: i.MX27: Remove optional "ptp" clock source for FEC ... Signed-off-by: Kevin Hilman <khilman@linaro.org>
2013-08-23Merge branches 'hwmod_devel_v3.12', 'prcm_devel_v3.12' and ↵Paul Walmsley
'am33xx_devel_v3.12' into prcm_a_for_v3.12
2013-08-23Merge tag 'imx-soc-3.12' of git://git.linaro.org/people/shawnguo/linux-2.6 ↵Kevin Hilman
into next/soc From Shawn Guo: It contains a bunch of imx soc updates for 3.12. - Add more ethernet phy fixups for imx6 boards - Add some missing imx6q clocks into clock driver - Add new clock types fixup mux and div to work around some ugly hardware defect - Consolidate L2 cache initialization function, so that it can be used on more i.MX SoCs - Replace magic numbers in mach-imx6q.c with well defined macros - Small fixes for imx6q and pllv3 clock drivers - Some random updates on imx defconfig files * tag 'imx-soc-3.12' of git://git.linaro.org/people/shawnguo/linux-2.6: (33 commits) phy: micrel: Add definitions for common Micrel PHY registers ARM: imx: Re-select CONFIG_SND_SOC_IMX_MC13783 option ARM: imx: Move anatop related from board file to anatop driver ARM: imx_v6_v7_defconfig: Enable wireless support ARM: imx_v4_v5_defconfig: Cleanup imx_v4_v5_defconfig ARM: imx_v6_v7_defconfig: Add SATA support ARM: imx_v6_v7_defconfig: Cleanup imx_v6_v7_defconfig ARM: mx53: Allow suspend/resume ARM: mach-imx: Select ARM_CPU_SUSPEND at ARCH_MXC level ARM: imx_v6_v7_defconfig: Select CONFIG_TOUCHSCREEN_EGALAX ARM: imx6q: add vdoa gate clock ARM: imx6q: add the missing cko output selection ARM: imx6q: add cko2 clocks ARM: imx6q: add spdif gate clock ARM: imx: clk-pllv3: improve the timeout waiting method ARM: imx6: change some clocks to fixup clocks ARM: imx: add common clock support for fixup mux ARM: imx: add common clock support for fixup div ARM: imx: Select MIGHT_HAVE_CACHE_L2X0 ARM: imx: fix imx_init_l2cache storage class ...
2013-08-23ARM: OMAP: AM33xx: clock: Add RNG clock dataLokesh Vutla
Add clock data for RNG module on AM33xx SoC. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-08-23m68k/atari: ARAnyM - Always use physical addresses in NatFeat callsGeert Uytterhoeven
Pointers passed to ARAnyM NatFeat calls should be physical addresses, not virtual addresses. This worked before because on Atari, physical and virtual kernel addresses are the same, as long as normal kernel memory is concerned. Correct the few remaining places where virtual addresses were used. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2013-08-23m68k: Ignore disabled HSYNC interrupt on Atari for irqs_disabled()Geert Uytterhoeven
When running a multi-platform kernel on Atari, warning messages like the following may be printed: WARNING: at /root/linux-3.10.1/init/main.c:698 do_one_initcall+0x12e/0x13a() initcall param_sysfs_init+0x0/0x1a4 returned with disabled interrupts This is caused by the different definitions of ALLOWINT for Atari and other platforms: #if defined(MACH_ATARI_ONLY) #define ALLOWINT (~0x500) #else #define ALLOWINT (~0x700) #endif On Atari, we want to disable the high-frequency HSYNC interrupt: - On Atari-only kernels, this is handled completely through ALLOWINT, - On multi-platform kernels, this is handled by disabling the HSYNC interrupt from the interrupt handler. However, as in the latter case arch_irqs_disabled_flags() didn't ignore the disabling of the HSYNC interrupt, irqs_disabled() would detect false positives. Ignore the HSYNC interrupt when running on Atari to fix this. For single-platform kernels this test is optimized away by the compiler. Reported-by: Thorsten Glaser <tg@debian.org> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Tested-by: Thorsten Glaser <tg@debian.org>
2013-08-23ARM: OMAP: TI81XX: add always-on powerdomain for TI81XXAida Mynzhasova
This patch adds alwon powerdomain support for TI81XX, which is required for stable functioning of a big number of TI81XX subsystems. Signed-off-by: Aida Mynzhasova <aida.mynzhasova@skitlab.ru> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-08-23ARM: OMAP4: clock: Lock PLLs in the right sequenceRajendra Nayak
On OMAP4 we have clk_set_rate()s being done for a few DPLL clock nodes, as part of the clock init code, since the bootloaders no longer locks these DPLLs. So we have a clk_set_rate() done for a ABE DPLL node (which inturn locks it) followed by a clk_set_rate() for the USB DPLL. With USB DPLL being in bypass, we have this parent->child relationship thats formed while the clocks get registered. dpll_abe_ck | V dpll_abe_x2_ck | V dpll_abe_m3x2_ck | V usb_hs_clk_div_ck | V dpll_usb_ck This is because usb_hs_clk_div_ck is bypass clock for dpll_usb_ck. So with this parent->child relationship in place, a clk_set_rate() on ABE DPLL results eventually in a clk_set_rate() call on USB DPLL, because CCF does a clk_change_rate() (as part of clk_set_rate()) on all downstream clocks resulting from a rate change on the top clock. So its important that we lock USB DPLL before we lock ABE DPLL. Without which we see these error logs at boot. [These error logs will not be seen if using a bootloader that locks USB DPLL] [ 0.000000] clock: dpll_usb_ck failed transition to 'locked' [ 0.000000] Division by zero in kernel. [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7 [ 0.000000] [<c001bfe8>] (unwind_backtrace+0x0/0xf4) from [<c001868c>] (show_stack+0x10/0x14) [ 0.000000] [<c001868c>] (show_stack+0x10/0x14) from [<c02deb28>] (Ldiv0+0x8/0x10) [ 0.000000] [<c02deb28>] (Ldiv0+0x8/0x10) from [<c0477030>] (clk_divider_set_rate+0x10/0x114) [ 0.000000] [<c0477030>] (clk_divider_set_rate+0x10/0x114) from [<c0476ef4>] (clk_change_rate+0x38/0xb8) [ 0.000000] [<c0476ef4>] (clk_change_rate+0x38/0xb8) from [<c0476f5c>] (clk_change_rate+0xa0/0xb8) [ 0.000000] Division by zero in kernel. [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7 [ 0.000000] [<c001bfe8>] (unwind_backtrace+0x0/0xf4) from [<c001868c>] (show_stack+0x10/0x14) [ 0.000000] [<c001868c>] (show_stack+0x10/0x14) from [<c02deb28>] (Ldiv0+0x8/0x10) [ 0.000000] [<c02deb28>] (Ldiv0+0x8/0x10) from [<c0477030>] (clk_divider_set_rate+0x10/0x114) [ 0.000000] [<c0477030>] (clk_divider_set_rate+0x10/0x114) from [<c0476ef4>] (clk_change_rate+0x38/0xb8) [ 0.000000] [<c0476ef4>] (clk_change_rate+0x38/0xb8) from [<c0476f5c>] (clk_change_rate+0xa0/0xb8) [ 0.000000] Division by zero in kernel. [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7 [ 0.000000] [<c001bfe8>] (unwind_backtrace+0x0/0xf4) from [<c001868c>] (show_stack+0x10/0x14) [ 0.000000] [<c001868c>] (show_stack+0x10/0x14) from [<c02deb28>] (Ldiv0+0x8/0x10) [ 0.000000] [<c02deb28>] (Ldiv0+0x8/0x10) from [<c0477030>] (clk_divider_set_rate+0x10/0x114) [ 0.000000] [<c0477030>] (clk_divider_set_rate+0x10/0x114) from [<c0476ef4>] (clk_change_rate+0x38/0xb8) [ 0.000000] [<c0476ef4>] (clk_change_rate+0x38/0xb8) from [<c0476f5c>] (clk_change_rate+0xa0/0xb8) [ 0.000000] Division by zero in kernel. [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7 [ 0.000000] [<c001bfe8>] (unwind_backtrace+0x0/0xf4) from [<c001868c>] (show_stack+0x10/0x14) [ 0.000000] [<c001868c>] (show_stack+0x10/0x14) from [<c02deb28>] (Ldiv0+0x8/0x10) [ 0.000000] [<c02deb28>] (Ldiv0+0x8/0x10) from [<c0477030>] (clk_divider_set_rate+0x10/0x114) [ 0.000000] [<c0477030>] (clk_divider_set_rate+0x10/0x114) from [<c0476ef4>] (clk_change_rate+0x38/0xb8) [ 0.000000] [<c0476ef4>] (clk_change_rate+0x38/0xb8) from [<c0476f5c>] (clk_change_rate+0xa0/0xb8) [ 0.000000] Division by zero in kernel. [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7 [ 0.000000] [<c001bfe8>] (unwind_backtrace+0x0/0xf4) from [<c001868c>] (show_stack+0x10/0x14) [ 0.000000] [<c001868c>] (show_stack+0x10/0x14) from [<c02deb28>] (Ldiv0+0x8/0x10) [ 0.000000] [<c02deb28>] (Ldiv0+0x8/0x10) from [<c0477030>] (clk_divider_set_rate+0x10/0x114) [ 0.000000] [<c0477030>] (clk_divider_set_rate+0x10/0x114) from [<c0476ef4>] (clk_change_rate+0x38/0xb8) [ 0.000000] [<c0476ef4>] (clk_change_rate+0x38/0xb8) from [<c0476f5c>] (clk_change_rate+0xa0/0xb8) [ 0.000000] Division by zero in kernel. [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7 [ 0.000000] [<c001bfe8>] (unwind_backtrace+0x0/0xf4) from [<c001868c>] (show_stack+0x10/0x14) [ 0.000000] [<c001868c>] (show_stack+0x10/0x14) from [<c02deb28>] (Ldiv0+0x8/0x10) [ 0.000000] [<c02deb28>] (Ldiv0+0x8/0x10) from [<c0477030>] (clk_divider_set_rate+0x10/0x114) [ 0.000000] [<c0477030>] (clk_divider_set_rate+0x10/0x114) from [<c0476ef4>] (clk_change_rate+0x38/0xb8) [ 0.000000] [<c0476ef4>] (clk_change_rate+0x38/0xb8) from [<c0476f5c>] (clk_change_rate+0xa0/0xb8) [ 0.000000] clock: trace_clk_div_ck: could not find divisor for target rate 0 for parent pmd_trace_clk_mux_ck [ 0.000000] Division by zero in kernel. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-08-23ARM: OMAP: AM33XX: hwmod: Add hwmod data for debugSSVaibhav Hiremath
In the original hwmod data file, DebugSS entry was disabled, since we didn't (and do not) have SW to control it. This patch enables it back with right data, so that it can be controlled by different ways; and the suggested method it to have modular driver for debugSS as well. Refer to the link for more discussion on handling of debugSS - https://patchwork.kernel.org/patch/2212111/ Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-08-23ARM: OMAP2+: Only write the sysconfig on idle when necessaryJon Hunter
Currently, whenever we idle a device _idle_sysc() is called and writes to the devices SYSCONFIG register to set the idle mode. A lot devices are using the smart-idle mode and so the write to the SYSCONFIG register is programming the same value that is already stored in the register. Writes to the devices SYSCONFIG register can be slow, for example, writing to the DMTIMER SYSCONFIG register takes 3 interface clock cycles and 3 functional clock cycles. If the DMTIMER is using the slow 32kHz functional clock this can take ~100us. Furthermore, during boot on an OMAP4430 panda board, I see that there are 100 calls to _idle_sysc(), however, only 3 out of the 100 calls actually write the SYSCONFIG register with a new value. Therefore, to avoid unnecessary writes to device SYSCONFIG registers when idling the device, only write the value if the value has changed. It should be safe to do this on idle as the context of the register will never be lost while the device is active. Verified that suspend, CORE off and retention states are working with this change on OMAP3430 Beagle board. Signed-off-by: Jon Hunter <jon-hunter@ti.com> [paul@pwsan.com: updated to apply] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-08-23ARM: OMAP: DRA7: Enable PM framework initializationsAmbresh K
Initialise powerdomains, clockdomains, and hwmod frameworks. Signed-off-by: Ambresh K <ambresh@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: updated to apply] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-08-23ARM: OMAP: DRA7: hwmod: Create initial DRA7XX SoC dataAmbresh K
Adding the hwmod data for DRA7XX platforms. Signed-off-by: Ambresh K <ambresh@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-08-23ARM: OMAP: DRA7: Reuse the omap44xx_restart and fix the device instanceRajendra Nayak
The omap44xx_restart used on omap4 and omap5 devices can be reused on dra7 devices as well. The device instance however is different across omap5 and dra7 as compared to omap4. So fix this for omap5 as well as dra7. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-08-23ARM: OMAP: DRA7: powerdomain: Handle missing vc/vpRajendra Nayak
DRA7 belongs to the omap4plus devices which reuse the omap4_pwrdm_operations ops for powerdomain control. DRA7 however has no VC/VP while all the earlier omap4plus devices did. So use the .pwrdm_has_voltdm() ops to pass this info on to the core. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-08-23ARM: OMAP: DRA7: powerdomain: Add DRA7XX data and update headerAmbresh K
Add the data file to describe all power domains inside the DRA7XX SoC. Signed-off-by: Ambresh K <ambresh@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: added generation notation to comments] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-08-23ARM: OMAP: DRA7: clockdomain: Add DRA7XX data and update headerAmbresh K
Add the data file to describe all clock domains inside the DRA7XX SoC Signed-off-by: Ambresh K <ambresh@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: added generation notation to comments] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-08-23ARM: OMAP: DRA7: PRCM: Add DRA7XX local MPU PRCM regsitersAmbresh K
Add the PRCM MPU registers for DRA7XX platforms Signed-off-by: Ambresh K <ambresh@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: added generation notation to comments] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-08-23ARM: OMAP: DRA7: CM: Add minimal regbit shiftsRajendra Nayak
This header contains minimal regbits that are currently used in code. This header has traditionally been autogenerated on OMAP4+ devices but the autogenerated contents are largely (95%) unused and hence to reduce unsued data in the kernel this header has been cut down (from the autogen output) to whatever is currently needed. This is done by running a cleanup script on top of the existing autogen script. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Ambresh K <ambresh@ti.com> [paul@pwsan.com: added generation notation in the comments] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-08-23ARM: OMAP: DRA7: CM: Add DRA7XX register definesAmbresh K
Add the new defines for DRA7XX CM registers. Signed-off-by: Ambresh K <ambresh@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: added generation notation in comments] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-08-23ARM: OMAP: DRA7: PRM: Add DRA7XX register definitionsAmbresh K
Add the new defines for DRA7xx prm module registers. Signed-off-by: Ambresh K <ambresh@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: added generation notation in the comments] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-08-23i2c: move OF helpers into the coreWolfram Sang
I2C of helpers used to live in of_i2c.c but experience (from SPI) shows that it is much cleaner to have this in the core. This also removes a circular dependency between the helpers and the core, and so we can finally register child nodes in the core instead of doing this manually in each driver. So, fix the drivers and documentation, too. Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2013-08-23pinctrl: sirf: add lost atlas6 uart0-no-stream-control pingroupQipan Li
the old codes defined uart0_nostreamctrl_pins, but missed pingroup and padmux definition for it. this patch fixes it. Signed-off-by: Qipan Li <Qipan.Li@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-23ARM: at91/dt: sama5d3xek: reduce the ROM code mapping for pmecc lookup tableJosh Wu
Signed-off-by: Josh Wu <josh.wu@atmel.com>
2013-08-23ARM: at91/dt: sama5d3xek: Enable NFC support in dtsJosh Wu
Signed-off-by: Josh Wu <josh.wu@atmel.com>
2013-08-23ARM: at91/dt: sama5d3xek: remove the useless NFC dt parametersJosh Wu
The NFC driver code doesn't use atmel,has-nfc and atmel,use-nfc-sram. Signed-off-by: Josh Wu <josh.wu@atmel.com>
2013-08-22ARM: highbank: avoid L2 cache smc calls when PL310 is not presentRob Herring
While Midway firmware handles L2 smc calls as nops, the custom smc calls present a problem when running virtualized Midway guest. They aren't needed so just avoid calling them. In the process, cleanup the L2X0 ifdefs and use IS_ENABLED instead. Signed-off-by: Rob Herring <rob.herring@calxeda.com>