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2014-01-10powerpc/85xx: handle the eLBC error interrupt if it exists in dtsShaohui Xie
On P1020, P1021, P1022, and P1023, eLBC event interrupts are routed to internal interrupt 3 while ELBC error interrupts are routed to internal interrupt 0. We need to call request_irq for each. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> [scottwood@freescale.com: reworded commit message and fixed author] Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-01-10powerpc/dts: fix lbc lack of error interruptWang Dongsheng
P1020, P1021, P1022, P1023 when the lbc get error, the error interrupt will be triggered. The corresponding interrupt is internal IRQ0. So system have to process the lbc IRQ0 interrupt. The corresponding lbc general interrupt is internal IRQ3. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> [scottwood@freescale.com: bracketed individual list elements] Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-01-10s390: use device_remove_file_self() instead of device_schedule_callback()Tejun Heo
driver-core now supports synchrnous self-deletion of attributes and the asynchrnous removal mechanism is scheduled for removal. Use it instead of device_schedule_callback(). * Conversions in arch/s390/pci/pci_sysfs.c and drivers/s390/block/dcssblk.c are straightforward. * drivers/s390/cio/ccwgroup.c is a bit more tricky because ccwgroup_notifier() was (ab)using device_schedule_callback() to purely obtain a process context to kick off ungroup operation which may block from a notifier callback. Rename ccwgroup_ungroup_callback() to ccwgroup_ungroup() and make it take ccwgroup_device * instead. The new function is now called directly from ccwgroup_ungroup_store(). ccwgroup_notifier() chain is updated to explicitly bounce through ccwgroup_device->ungroup_work. This also removes possible failure from memory pressure. Only compile-tested. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: linux390@de.ibm.com Cc: linux-s390@vger.kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-01-10Merge branch 'qcom/fixes' into next/fixes-non-criticalKevin Hilman
* qcom/fixes: ARM: dts: msm: Fix gpio interrupt and reg length Signed-off-by: Kevin Hilman <khilman@linaro.org>
2014-01-10ARM: dts: msm: Fix gpio interrupt and reg lengthStephen Boyd
The summary interrupt is #16 in the SPI space. Unfortunately, when this device was translated from board files to DT we forgot to subtract 16 from the interrupt number to translate it into a SPI interrupt. Also, the register space is larger than 4k, increase it appropriately so that the gpio driver doesn't try to access registers outside of its mapping. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@linaro.org>
2014-01-10Merge branch 'pci/resource' into nextBjorn Helgaas
* pci/resource: PCI: Allocate 64-bit BARs above 4G when possible PCI: Enforce bus address limits in resource allocation PCI: Split out bridge window override of minimum allocation address agp/ati: Use PCI_COMMAND instead of hard-coded 4 agp/intel: Use CPU physical address, not bus address, for ioremap() agp/intel: Use pci_bus_address() to get GTTADR bus address agp/intel: Use pci_bus_address() to get MMADR bus address agp/intel: Support 64-bit GMADR agp/intel: Rename gtt_bus_addr to gtt_phys_addr drm/i915: Rename gtt_bus_addr to gtt_phys_addr agp: Use pci_resource_start() to get CPU physical address for BAR agp: Support 64-bit APBASE PCI: Add pci_bus_address() to get bus address of a BAR PCI: Convert pcibios_resource_to_bus() to take a pci_bus, not a pci_dev PCI: Change pci_bus_region addresses to dma_addr_t
2014-01-10Merge branch 'qcom/soc2' into next/socKevin Hilman
* qcom/soc2: ARM: msm_defconfig: Update for multi-platform Signed-off-by: Kevin Hilman <khilman@linaro.org>
2014-01-10ARM: msm_defconfig: Update for multi-platformStephen Boyd
ARCH_MSM is a hidden config option now so this defconfig needs to be updated to select ARCH_MSM_DT instead. While we're here, remove dead symbols (SSBI), drop selected symbols (ZRELADDR, PHYLIB, USB_PHY) and enable the MSM random driver (HW_RANDOM_MSM). Cc: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@linaro.org>
2014-01-10arm64: kernel: restore HW breakpoint registers in cpu_suspendLorenzo Pieralisi
When a CPU resumes from low-power, it restores HW breakpoint and watchpoint slots through a CPU PM notifier. Since we want to enable debugging as early as possible in the resume path, the mdscr content is restored along the general purpose registers in the cpu_suspend API and debug exceptions are reenabled when cpu_suspend returns. Since the CPU PM notifier is run after a CPU has been resumed, we cannot expect HW breakpoint registers to contain sane values till the notifier is run, since the HW breakpoints registers content is unknown at reset; this means that the CPU might run with debug exceptions enabled, mdscr restored but HW breakpoint registers containing junk values that can trigger spurious debug exceptions. This patch fixes current HW breakpoints restore by moving the HW breakpoints registers restoration to the cpu_suspend API, before the debug exceptions are enabled. This way, as soon as the cpu_suspend function returns the kernel can resume debugging with sane values in HW breakpoint registers. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-01-10xen/pvh: Use 'depend' instead of 'select'.Konrad Rzeszutek Wilk
The usage of 'select' means it will enable the CONFIG options without checking their dependencies. That meant we would inadvertently turn on CONFIG_XEN_PVHM while its core dependency (CONFIG_PCI) was turned off. This patch fixes the warnings and compile failures: warning: (XEN_PVH) selects XEN_PVHVM which has unmet direct dependencies (HYPERVISOR_GUEST && XEN && PCI && X86_LOCAL_APIC) Reported-by: Jim Davis <jim.epost@gmail.com> Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
2014-01-10Merge tag 'clk-fixes-for-linus' of ↵Linus Torvalds
git://git.linaro.org/people/mike.turquette/linux Pull clock fixes from Mike Turquette: "Late fixes for clock drivers. All of these fixes are for user-visible regressions, typically boot failures or other unsafe system configuration that causes badness" * tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux: clk: clk-divider: fix divisor > 255 bug clk: exynos: File scope reg_save array should depend on PM_SLEEP clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clock ARM: dts: exynos5250: Fix MDMA0 clock number clk: samsung: exynos5250: Add MDMA0 clocks clk: samsung: exynos5250: Fix ACP gate register offset clk: exynos5250: fix sysmmu_mfc{l,r} gate clocks clk: samsung: exynos4: Correct SRC_MFC register
2014-01-10Merge tag 'fixes-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC fixes from Olof Johansson: "A few fixes for Renesas platforms to fixup DMA masks (this started causing errors once the DMA API added checks for valid masks in 3.13)" * tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: ARM: shmobile: mackerel: Fix coherent DMA mask ARM: shmobile: kzm9g: Fix coherent DMA mask ARM: shmobile: armadillo: Fix coherent DMA mask
2014-01-09powerpc/embedded6xx: Add support for Motorola/Emerson MVME5100Stephen Chivers
Add support for the Motorola/Emerson MVME5100 Single Board Computer. The MVME5100 is a 6U form factor VME64 computer with: - A single MPC7410 or MPC750 CPU - A HAWK Processor Host Bridge (CPU to PCI) and MultiProcessor Interrupt Controller (MPIC) - Up to 500Mb of onboard memory - A M48T37 Real Time Clock (RTC) and Non-Volatile Memory chip - Two 16550 compatible UARTS - Two Intel E100 Fast Ethernets - Two PCI Mezzanine Card (PMC) Slots - PPCBug Firmware The HAWK PHB/MPIC is compatible with the MPC10x devices. There is no onboard disk support. This is usually provided by installing a PMC in first PMC slot. This patch revives the board support, it was present in early 2.6 series kernels. The board support in those days was by Matt Porter of MontaVista Software. CSC Australia has around 31 of these boards in service. The kernel in use for the boards is based on 2.6.31. The boards are operated without disks from a file server. This patch is based on linux-3.13-rc2 and has been boot tested. Only boards with 512 Mb of memory are known to work. Signed-off-by: Stephen Chivers <schivers@csc.com> Tested-by: Alessio Igor Bogani <alessio.bogani@elettra.eu> Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-01-09powerpc/fsl-book3e-64: Use paca for hugetlb TLB1 entry selectionScott Wood
This keeps usage coordinated for hugetlb and indirect entries, which should make entry selection more predictable and probably improve overall performance when mixing the two. Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-01-09powerpc/e6500: TLB miss handler with hardware tablewalk supportScott Wood
There are a few things that make the existing hw tablewalk handlers unsuitable for e6500: - Indirect entries go in TLB1 (though the resulting direct entries go in TLB0). - It has threads, but no "tlbsrx." -- so we need a spinlock and a normal "tlbsx". Because we need this lock, hardware tablewalk is mandatory on e6500 unless we want to add spinlock+tlbsx to the normal bolted TLB miss handler. - TLB1 has no HES (nor next-victim hint) so we need software round robin (TODO: integrate this round robin data with hugetlb/KVM) - The existing tablewalk handlers map half of a page table at a time, because IBM hardware has a fixed 1MiB indirect page size. e6500 has variable size indirect entries, with a minimum of 2MiB. So we can't do the half-page indirect mapping, and even if we could it would be less efficient than mapping the full page. - Like on e5500, the linear mapping is bolted, so we don't need the overhead of supporting nested tlb misses. Note that hardware tablewalk does not work in rev1 of e6500. We do not expect to support e6500 rev1 in mainline Linux. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Mihai Caraman <mihai.caraman@freescale.com>
2014-01-09powerpc: add barrier after writing kernel PTEScott Wood
There is no barrier between something like ioremap() writing to a PTE, and returning the value to a caller that may then store the pointer in a place that is visible to other CPUs. Such callers generally don't perform barriers of their own. Even if callers of ioremap() and similar things did use barriers, the most logical choise would be smp_wmb(), which is not architecturally sufficient when BookE hardware tablewalk is used. A full sync is specified by the architecture. For userspace mappings, OTOH, we generally already have an lwsync due to locking, and if we occasionally take a spurious fault due to not having a full sync with hardware tablewalk, it will not be fatal because we will retry rather than oops. Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-01-09powerpc/fsl_booke: enable the relocatable for the kdump kernelKevin Hao
The RELOCATABLE is more flexible and without any alignment restriction. And it is a superset of DYNAMIC_MEMSTART. So use it by default for a kdump kernel. Signed-off-by: Kevin Hao <haokexin@gmail.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-01-09powerpc/fsl_booke: smp support for booting a relocatable kernel above 64MKevin Hao
When booting above the 64M for a secondary cpu, we also face the same issue as the boot cpu that the PAGE_OFFSET map two different physical address for the init tlb and the final map. So we have to use switch_to_as1/restore_to_as0 between the conversion of these two maps. When restoring to as0 for a secondary cpu, we only need to return to the caller. So add a new parameter for function restore_to_as0 for this purpose. Use LOAD_REG_ADDR_PIC to get the address of variables which may be used before we set the final map in cams for the secondary cpu. Move the setting of cams a bit earlier in order to avoid the unnecessary using of LOAD_REG_ADDR_PIC. Signed-off-by: Kevin Hao <haokexin@gmail.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-01-09powerpc/fsl_booke: make sure PAGE_OFFSET map to memstart_addr for ↵Kevin Hao
relocatable kernel This is always true for a non-relocatable kernel. Otherwise the kernel would get stuck. But for a relocatable kernel, it seems a little complicated. When booting a relocatable kernel, we just align the kernel start addr to 64M and map the PAGE_OFFSET from there. The relocation will base on this virtual address. But if this address is not the same as the memstart_addr, we will have to change the map of PAGE_OFFSET to the real memstart_addr and do another relocation again. Signed-off-by: Kevin Hao <haokexin@gmail.com> [scottwood@freescale.com: make offset long and non-negative in simple case] Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-01-09powerpc/fsl_booke: introduce map_mem_in_cams_addrKevin Hao
Introduce this function so we can set both the physical and virtual address for the map in cams. This will be used by the relocation code. Signed-off-by: Kevin Hao <haokexin@gmail.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-01-09powerpc: introduce early_get_first_memblock_infoKevin Hao
For a relocatable kernel since it can be loaded at any place, there is no any relation between the kernel start addr and the memstart_addr. So we can't calculate the memstart_addr from kernel start addr. And also we can't wait to do the relocation after we get the real memstart_addr from device tree because it is so late. So introduce a new function we can use to get the first memblock address and size in a very early stage (before machine_init). Signed-off-by: Kevin Hao <haokexin@gmail.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-01-09powerpc/fsl_booke: set the tlb entry for the kernel address in AS1Kevin Hao
We use the tlb1 entries to map low mem to the kernel space. In the current code, it assumes that the first tlb entry would cover the kernel image. But this is not true for some special cases, such as when we run a relocatable kernel above the 64M or set CONFIG_KERNEL_START above 64M. So we choose to switch to address space 1 before setting these tlb entries. Signed-off-by: Kevin Hao <haokexin@gmail.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-01-09powerpc: enable the relocatable support for the fsl booke 32bit kernelKevin Hao
This is based on the codes in the head_44x.S. The difference is that the init tlb size we used is 64M. With this patch we can only load the kernel at address between memstart_addr ~ memstart_addr + 64M. We will fix this restriction in the following patches. Signed-off-by: Kevin Hao <haokexin@gmail.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-01-09powerpc: introduce macro LOAD_REG_ADDR_PICKevin Hao
This is used to get the address of a variable when the kernel is not running at the linked or relocated address. Signed-off-by: Kevin Hao <haokexin@gmail.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-01-09powerpc/fsl_booke: introduce get_phys_addr functionKevin Hao
Move the codes which translate a effective address to physical address to a separate function. So it can be reused by other code. Signed-off-by: Kevin Hao <haokexin@gmail.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-01-09powerpc/fsl_booke: protect the access to MAS7Kevin Hao
The e500v1 doesn't implement the MAS7, so we should avoid to access this register on that implementations. In the current kernel, the access to MAS7 are protected by either CONFIG_PHYS_64BIT or MMU_FTR_BIG_PHYS. Since some code are executed before the code patching, we have to use CONFIG_PHYS_64BIT in these cases. Signed-off-by: Kevin Hao <haokexin@gmail.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-01-09powerpc/mpic_timer: fix convert ticks to time subtraction overflowWang Dongsheng
In some cases tmp_sec may be greater than ticks, because in the process of calculation ticks and tmp_sec will be rounded. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-01-09powerpc/mpic_timer: fix the time is not accurate caused by GTCRR toggle bitWang Dongsheng
When the timer GTCCR toggle bit is inverted, we calculated the rest of the time is not accurate. So we need to ignore this bit. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-01-09powerpc/p1022ds: add a interrupt for rtc nodeWang Dongsheng
Add an external interrupt for rtc node. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-01-09powerpc/p1022ds: fix rtc compatible stringWang Dongsheng
RTC Hardware(ds3232) and rtc compatible string does not match. Change "dallas,ds1339" to "dallas,ds3232". Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-01-09powerpc/85xx: add sysfs for pw20 state and altivec idleWang Dongsheng
Add a sys interface to enable/diable pw20 state or altivec idle, and control the wait entry time. Enable/Disable interface: 0, disable. 1, enable. /sys/devices/system/cpu/cpuX/pw20_state /sys/devices/system/cpu/cpuX/altivec_idle Set wait time interface:(Nanosecond) /sys/devices/system/cpu/cpuX/pw20_wait_time /sys/devices/system/cpu/cpuX/altivec_idle_wait_time Example: Base on TBfreq is 41MHZ. 1~48(ns): TB[63] 49~97(ns): TB[62] 98~195(ns): TB[61] 196~390(ns): TB[60] 391~780(ns): TB[59] 781~1560(ns): TB[58] ... Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> [scottwood@freescale.com: change ifdef] Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-01-09ftrace/x86: Load ftrace_ops in parameter not the variable holding itSteven Rostedt
Function tracing callbacks expect to have the ftrace_ops that registered it passed to them, not the address of the variable that holds the ftrace_ops that registered it. Use a mov instead of a lea to store the ftrace_ops into the parameter of the function tracing callback. Signed-off-by: Steven Rostedt <rostedt@goodmis.org> Reviewed-by: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com> Link: http://lkml.kernel.org/r/20131113152004.459787f9@gandalf.local.home Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> Cc: <stable@vger.kernel.org> # v3.8+
2014-01-09Cleanup whitespace, remove old author tagJesper Nilsson
Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
2014-01-09ARM: dts: SiRF: add pin group for USP0 with only RX or TX frame syncRongjun Ying
add pin groups for USP0 only holding one of TX and RX frame sync. this patch matches with the change in drivers/pinctrl/sirf. Signed-off-by: Rongjun Ying <Rongjun.Ying@csr.com> Signed-off-by: Barry Song <Barry.Song@csr.com>
2014-01-09ARM: dts: SiRF: add lost usp1_uart_nostreamctrl pin group for atlas6Qipan Li
this patch adds lost usp1_uart_nostreamctrl pin group for atlas6, which matches with the change in drivers/pinctrl/sirf/pinctrl-atlas6.c. Signed-off-by: Qipan Li <Qipan.Li@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com>
2014-01-09ARM: dts: sirf: add lost minigpsrtc device nodeXianglong Du
This patch adds lost minigpsrtc device node for prima2 and atlas6, which is behind rtc-iobg and whose offset is 2000. Signed-off-by: Xianglong Du <Xianglong.Du@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com>
2014-01-09ARM: dts: sirf: add clock, frequence-voltage table for CPU0Rongjun Ying
prima2 and atlas6 uses cpufreq_cpu0, here we put related clock, operation points in dtsi. Signed-off-by: Rongjun Ying <Rongjun.Ying@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com>
2014-01-09ARM: dts: sirf: add lost bus_width, clock and status for sdhciBin Shi
some nodes missed bus_width, clocks and status properties, here we fix them in prima2 and atlas6 dtsi. Signed-off-by: Bin Shi <Bin.Shi@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com>
2014-01-09ARM: dts: sirf: add lost clocks for cphifbgBarry Song
This patch adds lost clocks property(index 42) for cphifbg node in prima2 and atlas6 dtsi. Signed-off-by: Barry Song <Baohua.Song@csr.com>
2014-01-09CRIS: Add missing syscallsJesper Nilsson
Complete list of syscalls for CRISv10 and CRISv32. Clean up some whitespace at the same time. Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
2014-01-09watchdog: davinci: rename platform driver to davinci-wdtIvan Khoronzhuk
As we switch to use the watchdog core which permits more than one active watchdog in the system, rename platform driver to "davinci-wdt" to be identifiable. Acked-by: Wim Van Sebroeck <wim@iguana.be> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2014-01-09KVM: PPC: Unify kvmppc_get_last_inst and scAlexander Graf
We had code duplication between the inline functions to get our last instruction on normal interrupts and system call interrupts. Unify both helper functions towards a single implementation. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-01-09openrisc: Use get_signal() signal_setup_done()Richard Weinberger
Use the more generic functions get_signal() signal_setup_done() for signal delivery. Signed-off-by: Richard Weinberger <richard@nod.at> Signed-off-by: Jonas Bonn <jonas@southpole.se>
2014-01-09openrisc: Rework signal handlingJonas Bonn
The mainline signal handling code for OpenRISC has been buggy since day one with respect to syscall restart. This patch significantly reworks the signal handling code: i) Move the "work pending" loop to C code (borrowed from ARM arch) ii) Allow a tracer to muck about with the IP and skip syscall restart in that case (again, borrowed from ARM) iii) Make signal handling WRT syscall restart actually work v) Make the signal handling code look more like that of other architectures so that it's easier for others to follow Reported-by: Anders Nystrom <anders@southpole.se> Signed-off-by: Jonas Bonn <jonas@southpole.se>
2014-01-09cris: sync_serial: remove interruptible_sleep_onArnd Bergmann
sleep_on and its variants are racy and going away. This replaces the two uses in the cris sync_serial drivers with the equivalent but race-free wait_event_interruptible. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Mikael Starvik <starvik@axis.com> Cc: linux-cris-kernel@axis.com Signed-off-by: Jesper Nilsson <jespern@axis.com>
2014-01-09KVM: PPC: NULL return of kvmppc_mmu_hpte_cache_next should be handledZhouyi Zhou
NULL return of kvmppc_mmu_hpte_cache_next should be handled Signed-off-by: Zhouyi Zhou <yizhouzhou@ict.ac.cn> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-01-09KVM: PPC: Book3E HV: call RECONCILE_IRQ_STATE to sync the software stateTiejun Chen
Rather than calling hard_irq_disable() when we're back in C code we can just call RECONCILE_IRQ_STATE to soft disable IRQs while we're already in hard disabled state. This should be functionally equivalent to the code before, but cleaner and faster. Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com> [agraf: fix comment, commit message] Signed-off-by: Alexander Graf <agraf@suse.de>
2014-01-09kvm: powerpc: use caching attributes as per linux pteBharat Bhushan
KVM uses same WIM tlb attributes as the corresponding qemu pte. For this we now search the linux pte for the requested page and get these cache caching/coherency attributes from pte. Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> Reviewed-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-01-09kvm: powerpc: define a linux pte lookup functionBharat Bhushan
We need to search linux "pte" to get "pte" attributes for setting TLB in KVM. This patch defines a lookup_linux_ptep() function which returns pte pointer. Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> Reviewed-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-01-09kvm: book3s: rename lookup_linux_pte() to lookup_linux_pte_and_update()Bharat Bhushan
lookup_linux_pte() is doing more than lookup, updating the pte, so for clarity it is renamed to lookup_linux_pte_and_update() Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> Reviewed-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>