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2010-10-30Merge git://git.infradead.org/mtd-2.6Linus Torvalds
* git://git.infradead.org/mtd-2.6: (82 commits) mtd: fix build error in m25p80.c mtd: Remove redundant mutex from mtd_blkdevs.c MTD: Fix wrong check register_blkdev return value Revert "mtd: cleanup Kconfig dependencies" mtd: cfi_cmdset_0002: make sector erase command variable mtd: cfi_cmdset_0002: add CFI detection for SST 38VF640x chips mtd: cfi_util: add support for switching SST 39VF640xB chips into QRY mode mtd: cfi_cmdset_0001: use defined value of P_ID_INTEL_PERFORMANCE instead of hardcoded one block2mtd: dubious assignment P4080/mtd: Fix the freescale lbc issue with 36bit mode P4080/eLBC: Make Freescale elbc interrupt common to elbc devices mtd: phram: use KBUILD_MODNAME mtd: OneNAND: S5PC110: Fix double call suspend & resume function mtd: nand: fix MTD_MODE_RAW writes jffs2: use kmemdup mtd: sm_ftl: cosmetic, use bool when possible mtd: r852: remove useless pci powerup/down from suspend/resume routines mtd: blktrans: fix a race vs kthread_stop mtd: blktrans: kill BKL mtd: allow to unload the mtdtrans module if its block devices aren't open ... Fix up trivial whitespace-introduced conflict in drivers/mtd/mtdchar.c
2010-10-30Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (215 commits) ARM: memblock: setup lowmem mappings using memblock ARM: memblock: move meminfo into find_limits directly ARM: memblock: convert free_highpages() to use memblock ARM: move freeing of highmem pages out of mem_init() ARM: memblock: convert memory detail printing to use memblock ARM: memblock: use memblock to free memory into arm_bootmem_init() ARM: memblock: use memblock when initializing memory allocators ARM: ensure membank array is always sorted ARM: 6466/1: implement flush_icache_all for the rest of the CPUs ARM: 6464/2: fix spinlock recursion in adjust_pte() ARM: fix memblock breakage ARM: 6465/1: Fix data abort accessing proc_info from __lookup_processor_type ARM: 6460/1: ixp2000: fix type of ixp2000_timer_interrupt ARM: 6449/1: Fix for compiler warning of uninitialized variable. ARM: 6445/1: fixup TCM memory types ARM: imx: Add wake functionality to GPIO ARM: mx5: Add gpio-keys to mx51 babbage board ARM: imx: Add gpio-keys to plat-mxc mx31_3ds: Fix spi registration mx31_3ds: Fix the logic for detecting the debug board ...
2010-10-30Merge branch 'master' of ↵David Woodhouse
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git Conflicts: drivers/mtd/mtd_blkdevs.c Merge Grant's device-tree bits so that we can apply the subsequent fixes. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2010-10-29Merge branches 'x86-fixes-for-linus' and 'x86-uv-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86, alternative: Call stop_machine_text_poke() on all cpus x86-32: Restore irq stacks NUMA-aware allocations x86, memblock: Fix early_node_mem with big reserved region. * 'x86-uv-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86, uv: More Westmere support on SGI UV x86, uv: Enable Westmere support on SGI UV
2010-10-29Merge branches 'msm-fixes' and 'msm-video' of ↵Linus Torvalds
git://codeaurora.org/quic/kernel/dwalker/linux-msm * 'msm-fixes' of git://codeaurora.org/quic/kernel/dwalker/linux-msm: msm: Kconfig: drop unused config options msm: fix compile failure when no debug uart is selected msm: fix debug-macro.S build failure msm: timer: Decrease shift on timer clocksource arm: mach-msm: fix error handling in msm_iommu_probe() msm: fix Kconfig target board selection msm: fix compile failure on struct membank node member * 'msm-video' of git://codeaurora.org/quic/kernel/dwalker/linux-msm: drivers/video/msm/mddi.c: Remove multiple KERN_<level> uses drivers: msm: video: add dev_set_name call drivers: video: msm: fix hang on disable_irq
2010-10-29Merge branch 'for-2637/s3c24xx-all' of git://git.fluff.org/bjdooks/linuxLinus Torvalds
* 'for-2637/s3c24xx-all' of git://git.fluff.org/bjdooks/linux: ARM: h1940: add UDA1380 to i2c devices list ARM: h1940: Fix backlight and LCD power functions ARM: S3C2440: fix boot failure introduced by recent changes in gpiolib ARM: S3C2440: various fixes in Kconfig file ARM: rx1950: Add UDA1380 to i2c devices list ARM: rx1950: Add LEDs support ARM: rx1950: Add battery device ARM: h1940: Implement mmc_power function ARM: h1940: Use gpiolib for latch access
2010-10-30ARM: Merge for-2637/s3c24xx/miscBen Dooks
2010-10-30ARM: Merge for-2637/s3c24xx/h1940Ben Dooks
2010-10-30ARM: Merge for-2637/s3c24xx/rx1950Ben Dooks
2010-10-30ARM: h1940: add UDA1380 to i2c devices listVasily Khoruzhick
Register UDA1380 codec during H1940 machine init Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2010-10-30ARM: h1940: Fix backlight and LCD power functionsVasily Khoruzhick
Current implementation of LCD and backlight power control functions is not complete, as result PDA consumes power in suspend. Fix this issue by managing state of some latch bits, just like WinMobile does. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2010-10-29x86, alternative: Call stop_machine_text_poke() on all cpusJason Baron
Currently, text_poke_smp() passes a NULL as the third argument to __stop_machine(), which will only run stop_machine_text_poke() on 1 cpu. Change NULL -> cpu_online_mask, as stop_machine_text_poke() is intended to be run on all cpus. I actually didn't notice any problems with stop_machine_text_poke() only being called on 1 cpu, but found this via code inspection. Signed-off-by: Jason Baron <jbaron@redhat.com> LKML-Reference: <20101028152026.GB2875@redhat.com> Acked-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> Acked-by: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2010-10-30ARM: S3C2440: fix boot failure introduced by recent changes in gpiolibAbdoulaye Walsimou Gaye
Recent changes in s3c gpio break mini2440 board and may be others. The problem is that mach-mini2440.c: mini2440_init() (where we call s3c_gpio_setpull()) is called before s3c2440.c: s3c2440_init() (where we initialize s3c24xx_gpiocfg_default.set_pull function pointer). This causes dereferencing of NULL pointer at boot time and a kernel panic. Signed-off-by: Abdoulaye Walsimou Gaye <awg@embtoolkit.org> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2010-10-30ARM: S3C2440: various fixes in Kconfig fileAbdoulaye Walsimou Gaye
* kconfig symbols defined in arch/arm/mach-s3c2440/Kconfig are only available when ARCH_S3C2410 is selected, so no need to make some of them depend on ARCH_S3C2410. * fix CPU_S3C24405B typo in "config S3C2440_DMA". * mini2440: remove unconditionally select of SND_S3C24XX_SOC_S3C24XX_UDA134X. Those fixes avoid the following warnings at make time: scripts/kconfig/qconf arch/arm/Kconfig warning: (MACH_MINI2440 && ARCH_S3C2410) selects SND_S3C24XX_SOC_S3C24XX_UDA134X which has unmet direct dependencies (SND_S3C24XX_SOC && ARCH_S3C2410) warning: (CPU_S3C2440 && ARCH_S3C2410 && S3C2410_DMA) selects S3C2440_DMA which has unmet direct dependencies (ARCH_S3C2410 && CPU_S3C24405B) warning: (CPU_S3C2440 && ARCH_S3C2410 || CPU_S3C2442 && ARCH_S3C2410) selects CPU_S3C244X which has unmet direct dependencies (!ARCH_S3C2410) Signed-off-by: Abdoulaye Walsimou Gaye <awg@embtoolkit.org> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2010-10-29msm: Kconfig: drop unused config optionsDaniel Walker
These two config options don't exist, and aren't ever going to. So I simply delete them. Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-10-29msm: fix compile failure when no debug uart is selectedDaniel Walker
If the board has a debug uart the user is given a choice of which uart to use. The user can also select NONE, which means not to use one. In most of our header files when NONE is selected nothing is defined for MSM_DEBUG_UART_PHYS or MSM_DEBUG_UART_BASE. This causes a compile failure in debug-macro.S which expect something to be defined there. Example of the failure, arch/arm/kernel/built-in.o: In function `hexbuf': linux-2.6/arch/arm/kernel/debug.S:186: undefined reference to `MSM_DEBUG_UART_PHYS' linux-2.6/arch/arm/kernel/debug.S:186: undefined reference to `MSM_DEBUG_UART_BASE' This fixes the compile failure by adding an ifdef to debug-macro.S that removes all the debug uart code in the case of NONE. Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-10-29msm: fix debug-macro.S build failureDaniel Walker
Originally there was an ifdef case to handle when no debug uart was selected. In commit 0ea1293009826da45e1019f45dfde1e557bb30df that case was removed which causes the following build failure, linux-2.6/arch/arm/kernel/debug.S: Assembler messages: linux-2.6/arch/arm/kernel/debug.S:174: Error: bad instruction `addruart r1,r2' linux-2.6/arch/arm/kernel/debug.S:176: Error: bad instruction `waituart r2,r3' linux-2.6/arch/arm/kernel/debug.S:177: Error: bad instruction `senduart r1,r3' linux-2.6/arch/arm/kernel/debug.S:178: Error: bad instruction `busyuart r2,r3' linux-2.6/arch/arm/kernel/debug.S:190: Error: bad instruction `addruart r1,r2' This is a partial revert to add back the case which was removed with two caveats. First the API for the addruart macro was updated, and the new addruart case now return 0xfff00000 so that a know IO mapping is created instead of a random one. Cc: Jeremy Kerr <jeremy.kerr@canonical.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Jason Wang <jason77.wang@gmail.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Nicolas Pitre <nico@fluxnic.net> Cc: Russell King - ARM Linux <linux@arm.linux.org.uk> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-10-29Merge branch 'for_linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/jwessel/linux-2.6-kgdb * 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jwessel/linux-2.6-kgdb: kgdb,ppc: Individual register get/set for ppc kgdbts: prevent re-entry to kgdbts before it unregisters debug_core,x86,blackfin: Clean up hw debug disable API kdb: Fix early debugging crash regression kgdb,arm: fix register dump kdb: fix per_cpu command to remove supress mask kdb: Add kdb kernel module sample
2010-10-29kgdb,ppc: Individual register get/set for ppcDongdong Deng
commit 534af1082329392bc29f6badf815e69ae2ae0f4c(kgdb,kdb: individual register set and and get API) introduce dbg_get_reg/dbg_set_reg API for individual register get and set. This patch implement those APIs for ppc. Signed-off-by: Dongdong Deng <dongdong.deng@windriver.com> Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
2010-10-29debug_core,x86,blackfin: Clean up hw debug disable APIDongdong Deng
The kgdb_disable_hw_debug() was an architecture specific function for disabling all hardware breakpoints on a per cpu basis when entering the debug core. This patch will remove the weak function kdbg_disable_hw_debug() and change it into a call back which lives with the rest of hw breakpoint call backs in struct kgdb_arch. Signed-off-by: Dongdong Deng <dongdong.deng@windriver.com> Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
2010-10-29kgdb,arm: fix register dumpRabin Vincent
DBG_MAX_REG_NUM incorrectly had the number of indices in the GDB regs array rather than the number of registers, leading to an oops when the "rd" command is used in KDB. Cc: stable@kernel.org Signed-off-by: Rabin Vincent <rabin@rab.in> Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
2010-10-29Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/upstream-linusLinus Torvalds
* 'upstream' of git://git.linux-mips.org/pub/scm/upstream-linus: (46 commits) ftrace/MIPS: Enable C Version of recordmcount ftrace/MIPS: Add module support for C version of recordmcount ftrace/MIPS: Add MIPS64 support for C version of recordmcount MIPS: Make TASK_SIZE reflect proper size for both 32 and 64 bit processes. MIPS: Allow UserLocal on MIPS_R1 processors MIPS: Honor L2 bypass bit MIPS: Add BMIPS CP0 register definitions MIPS: Add BMIPS processor types to Kconfig MIPS: Decouple BMIPS CPU support from bcm47xx/bcm63xx SoC code MIPS: Add support for hardware performance events (mipsxx) MIPS: Perf-events: Add callchain support MIPS: add support for hardware performance events (skeleton) MIPS: add support for software performance events MIPS: define local_xchg from xchg_local to atomic_long_xchg MIPS: AR7: Add support for Titan (TNETV10xx) SoC variant MIPS: AR7: Initialize GPIO earlier MIPS: Add platform device and Kconfig for Octeon USB EHCI / OHCI USB: Add EHCI and OHCH glue for OCTEON II SOCs. MIPS: Octeon: Add register definitions for EHCI / OHCI USB glue logic. MIPS: Octeon: Apply CN63XXP1 errata workarounds. ...
2010-10-29ftrace/MIPS: Enable C Version of recordmcountWu Zhangjin
Selects HAVE_C_RECORDMCOUNT to use the C version of the recordmcount intead of the old Perl Version of recordmcount. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> LKML-Reference: <bb99009a9ac79d3f55a8c8bf1c8bd2bc0e1f160e.1288176026.git.wuzhangjin@gmail.com> Signed-off-by: Steven Rostedt <rostedt@goodmis.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29MIPS: Make TASK_SIZE reflect proper size for both 32 and 64 bit processes.David Daney
The TASK_SIZE macro should reflect the size of a user process virtual address space. Previously for 64-bit kernels, this was not the case. The immediate cause of pain was in hugetlbfs/inode.c:hugetlb_get_unmapped_area() where 32-bit processes trying to mmap a huge page would be served a page with an address outside of the 32-bit address range. But there are other uses of TASK_SIZE in the kernel as well that would like an accurate value. The new definition is nice because it now makes TASK_SIZE and TASK_SIZE_OF() yield the same value for any given process. For 32-bit kernels there should be no change, although I did factor out some code in asm/processor.h that became identical for the 32-bit and 64-bit cases. __UA_LIMIT is now set to ~((1 << SEGBITS) - 1) for 64-bit kernels. This should eliminate the possibility of getting a AddressErrorException in the kernel for addresses that pass the access_ok() test. With the patch applied, I can still run o32, n32 and n64 processes, and have an o32 shell fork/exec both n32 and n64 processes. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1701/
2010-10-29MIPS: Allow UserLocal on MIPS_R1 processorsKevin Cernekee
Some MIPS32R1 processors implement UserLocal (RDHWR $29) to accelerate programs that make extensive use of thread-local storage. Therefore, setting up the HWRENA register should not depend on cpu_has_mips_r2. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org
2010-10-29MIPS: Honor L2 bypass bitKevin Cernekee
On many of the newer MIPS32 cores, CP0 CONFIG2 bit 12 (L2B) indicates that the L2 cache is disabled and therefore Linux should not attempt to use it. [Ralf: Moved the code added by Kevin's original patch into a separate function that can easily be replaced for platforms that need more a different probe.] Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: linux-mips@linux-mips.org> Cc: <linux-kernel@vger.kernel.org> Patchwork: https://patchwork.linux-mips.org/patch/1723/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29MIPS: Add BMIPS CP0 register definitionsKevin Cernekee
Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: mbizon@freebox.fr Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Tested-by: Florian Fainelli <ffainelli@freebox.fr> Patchwork: https://patchwork.linux-mips.org/patch/1708/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org
2010-10-29MIPS: Add BMIPS processor types to KconfigKevin Cernekee
[v2: add "VIPER" marketing name for BMIPS4350] Add processor feature definitions for BMIPS3300, BMIPS4350, BMIPS4380, and BMIPS5000. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: mbizon@freebox.fr Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Tested-by: Florian Fainelli <ffainelli@freebox.fr> Patchwork: https://patchwork.linux-mips.org/patch/1716/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org
2010-10-29MIPS: Decouple BMIPS CPU support from bcm47xx/bcm63xx SoC codeKevin Cernekee
BMIPS processor cores are used in 50+ different chipsets spread across 5+ product lines. In many cases the chipsets do not share the same peripheral register layouts, the same register blocks, the same interrupt controllers, the same memory maps, or much of anything else. But, across radically different SoCs that share nothing more than the same BMIPS CPU, a few things are still mostly constant: SMP operations Access to performance counters DMA cache coherency quirks Cache and memory bus configuration So, it makes sense to treat each BMIPS processor type as a generic "building block," rather than tying it to a specific SoC. This makes it easier to support a large number of BMIPS-based chipsets without unnecessary duplication of code, and provides the infrastructure needed to support BMIPS-proprietary features. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: mbizon@freebox.fr Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Tested-by: Florian Fainelli <ffainelli@freebox.fr> Patchwork: https://patchwork.linux-mips.org/patch/1706/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org
2010-10-29MIPS: Add support for hardware performance events (mipsxx)Deng-Cheng Zhu
This patch adds the mipsxx Perf-events support based on the skeleton. Generic hardware events and cache events are now fully implemented for the 24K/34K/74K/1004K cores. To support other cores in mipsxx (such as R10000/SB1), the generic hardware event tables and cache event tables need to be filled out. To support other CPUs which have different PMU than mipsxx, such as RM9000 and LOONGSON2, the additional files perf_event_$cpu.c need to be created. Raw event is an important part of Perf-events. It helps the user collect performance data for events that are not listed as the generic hardware events and cache events but ARE supported by the CPU's PMU. This patch also adds this feature for mipsxx 24K/34K/74K/1004K. For how to use it, please refer to processor core software user's manual and the comments for mipsxx_pmu_map_raw_event() for more details. Please note that this is a "precise" implementation, which means the kernel will check whether the requested raw events are supported by this CPU and which hardware counters can be assigned for them. To test the functionality of Perf-event, you may want to compile the tool "perf" for your MIPS platform. You can refer to the following URL: http://www.linux-mips.org/archives/linux-mips/2010-10/msg00126.html You also need to customize the CFLAGS and LDFLAGS in tools/perf/Makefile for your libs, includes, etc. In case you encounter the boot failure in SMVP kernel on multi-threading CPUs, you may take a look at: http://www.linux-mips.org/git?p=linux-mti.git;a=commitdiff;h=5460815027d802697b879644c74f0e8365254020 Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> To: linux-mips@linux-mips.org Cc: a.p.zijlstra@chello.nl Cc: paulus@samba.org Cc: mingo@elte.hu Cc: acme@redhat.com Cc: jamie.iles@picochip.com Cc: ddaney@caviumnetworks.com Cc: matt@console-pimps.org Patchwork: https://patchwork.linux-mips.org/patch/1689/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> create mode 100644 arch/mips/kernel/perf_event_mipsxx.c
2010-10-29MIPS: Perf-events: Add callchain supportDeng-Cheng Zhu
Adds callchain support for MIPS Perf-events. For more info on this feature, please refer to tools/perf/Documentation/perf-report.txt and tools/perf/design.txt. Currently userspace callchain data is not recorded, because we do not have a safe way to do this. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> Acked-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Cc: a.p.zijlstra@chello.nl Cc: paulus@samba.org Cc: mingo@elte.hu Cc: acme@redhat.com Cc: jamie.iles@picochip.com Cc: matt@console-pimps.org Patchwork: https://patchwork.linux-mips.org/patch/1690/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29MIPS: add support for hardware performance events (skeleton)Deng-Cheng Zhu
This patch provides the skeleton of the HW perf event support. To enable this feature, we can not choose the SMTC kernel; Oprofile should be disabled; kernel performance events be selected. Then we can enable it in Kernel type menu. Oprofile for MIPS platforms initializes irq at arch init time. Currently we do not change this logic to allow PMU reservation. If a platform has EIC, we can use the irq base and perf counter irq offset defines for the interrupt controller in specific init_hw_perf_events(). Based on this skeleton patch, the 3 different kinds of MIPS PMU, namely, mipsxx/loongson2/rm9000, can be supported by adding corresponding lower level C files at the bottom. The suggested names of these files are perf_event_mipsxx.c/perf_event_loongson2.c/perf_event_rm9000.c. So, for example, we can do this by adding "#include perf_event_mipsxx.c" at the bottom of perf_event.c. In addition, PMUs with 64bit counters are also considered in this patch. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> To: linux-mips@linux-mips.org Cc: a.p.zijlstra@chello.nl Cc: paulus@samba.org Cc: mingo@elte.hu Cc: acme@redhat.com Cc: jamie.iles@picochip.com Cc: ddaney@caviumnetworks.com Cc: matt@console-pimps.org Patchwork: https://patchwork.linux-mips.org/patch/1688/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29MIPS: add support for software performance eventsDeng-Cheng Zhu
Software events are required as part of the measurable stuff by the Linux performance counter subsystem. Here is the list of events added by this patch: PERF_COUNT_SW_PAGE_FAULTS PERF_COUNT_SW_PAGE_FAULTS_MIN PERF_COUNT_SW_PAGE_FAULTS_MAJ PERF_COUNT_SW_ALIGNMENT_FAULTS PERF_COUNT_SW_EMULATION_FAULTS Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> To: linux-mips@linux-mips.org Cc: a.p.zijlstra@chello.nl Cc: paulus@samba.org Cc: mingo@elte.hu Cc: acme@redhat.com Cc: jamie.iles@picochip.com Acked-by: David Daney <ddaney@caviumnetworks.com> Reviewed-by: Matt Fleming <matt@console-pimps.org> Patchwork: https://patchwork.linux-mips.org/patch/1686/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29MIPS: define local_xchg from xchg_local to atomic_long_xchgDeng-Cheng Zhu
Perf-events is now using local_t helper functions internally. There is a use of local_xchg(). On MIPS, this is defined to xchg_local() which is missing in asm/system.h. This patch re-defines local_xchg() in asm/local.h to atomic_long_xchg(). Then Perf-events can pass the build. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> To: linux-mips@linux-mips.org Cc: a.p.zijlstra@chello.nl Cc: paulus@samba.org Cc: mingo@elte.hu Cc: acme@redhat.com Cc: jamie.iles@picochip.com Cc: ddaney@caviumnetworks.com Cc: matt@console-pimps.org Patchwork: https://patchwork.linux-mips.org/patch/1687/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29MIPS: AR7: Add support for Titan (TNETV10xx) SoC variantFlorian Fainelli
Add support for Titan TNETV1050,1055,1056,1060 variants. This SoC is almost completely identical to AR7 except on a few points: - a second bank of gpios is available - vlynq0 on titan is vlynq1 on ar7 - different PHY addresses for cpmac0 This SoC can be found on commercial products like the Linksys WRTP54G Original patch by Xin with improvments by Florian. Signed-off-by: Xin Zhen <xlonestar2000@aim.com> Signed-off-by: Florian Fainelli <florian@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/1563/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2010-10-29MIPS: AR7: Initialize GPIO earlierFlorian Fainelli
In order to detect the Titan variant, we must initialize GPIOs earlier since detection relies on some GPIO values to be set. Signed-off-by: Florian Fainelli <florian@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/1562/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2010-10-29MIPS: Add platform device and Kconfig for Octeon USB EHCI / OHCIDavid Daney
Declare that OCTEON reference boards have both OHCI and EHCI. Add platform devices for the corresponding hardware. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-usb@vger.kernel.org To: dbrownell@users.sourceforge.net Patchwork: http://patchwork.linux-mips.org/patch/1676/ Acked-by: Greg Kroah-Hartman <gregkh@suse.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29MIPS: Octeon: Add register definitions for EHCI / OHCI USB glue logic.David Daney
The EHCI and OHCI blocks connection to the I/O bus is controlled by these registers. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-usb@vger.kernel.org To: dbrownell@users.sourceforge.net Patchwork: http://patchwork.linux-mips.org/patch/1674/ Acked-by: Greg Kroah-Hartman <gregkh@suse.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> create mode 100644 arch/mips/include/asm/octeon/cvmx-uctlx-defs.h
2010-10-29MIPS: Octeon: Apply CN63XXP1 errata workarounds.David Daney
The CN63XXP1 needs a couple of workarounds to ensure memory is not written in unexpected ways. All PREF with hints in the range 0-4,6-24 are replaced with PREF 28. We pass a flag to the assembler to cover compiler generated code, and patch uasm for the dynamically generated code. The write buffer threshold is reduced to 4. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1672/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29MIPS: Octeon: Use I/O clock rate for calculations.David Daney
The I2C and UARTS are clocked by the I/O clock, use its rate for these devices. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1670/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29MIPS: Octeon: Add octeon_get_io_clock_rate() for cn63xxDavid Daney
Starting with cn63xx Octeon I/O blocks are clocked at a different rate than the CPU. Add a new function octeon_get_io_clock_rate() that yields the I/O clock rate. Also rearrange octeon_get_clock_rate() to get the value from the saved sysinfo structure. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1671/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29MIPS: Octeon: Remove bogus code from octeon_get_clock_rate()David Daney
We can run with any simulator clock rate. Get rid of the code overriding it to 6MHz. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1669/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29MIPS: Octeon: Scale Octeon2 clocks in octeon_init_cvmcount()David Daney
The per-CPU clocks are synchronized from IPD_CLK_COUNT, on cn63XX it must be scaled by the clock frequency ratio. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1667/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29MIPS: Octeon: Enable Read Inhibit / eXecute Inhibit on Octeon II.David Daney
Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1666/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29MIPS: Octeon: Probe for Octeon II CPUs.David Daney
The OCTEON II ISA extends the original OCTEON ISA, so give it its own __elf_platform string so optimized libraries can be selected in userspace. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1665/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29MIPS: Octeon: Handle Octeon II caches.David Daney
Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1664/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29MIPS: Add identifiers for Octeon II CPUs.David Daney
Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1662/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29MIPS: Octeon: Update L2 Cache code for CN63XXDavid Daney
The CN63XX has a different L2 cache architecture. Update the helper functions to reflect this. Some joining of split lines was also done to improve readability, as well as reformatting of comments. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1663/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29MIPS: Octeon: Add cn63XX to Octeon chip detection macros.David Daney
Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1661/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29MIPS: Octeon: Update register definitions for CN63XX chipsDavid Daney
The CN63XX is a new 6-CPU SOC based on the new OCTEON II CPU cores. Join some lines back together. This makes some of them exceed 80 columns, but they are uninteresting and this unclutters things. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1668/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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