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2014-03-27KVM: vmx: fix MPX detectionPaolo Bonzini
kvm_x86_ops is still NULL at this point. Since kvm_init_msr_list cannot fail, it is safe to initialize it before the call. Fixes: 93c4adc7afedf9b0ec190066d45b6d67db5270da Reported-by: Fengguang Wu <fengguang.wu@intel.com> Tested-by: Jet Chen <jet.chen@intel.com> Cc: kvm@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-03-27ARM: cache-tauros2: remove ARMv6 codeArnd Bergmann
When building a kernel with support for both ARMv6 and ARMv7 but no MMU, the call from tauros2_internal_init to adjust_cr causes a link error. While that could probably be resolved, we don't actually support cache-tauros2 on ARMv6 any more. All PJ4 CPU implementations support both ARMv6 and ARMv7 and we already assume that we are using them only in ARMv7 mode. Removing the ARMv6 code path reduces the code size and avoids the linker error. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
2014-03-27ARM: moxart: fix CPU selectionArnd Bergmann
Moxart uses an FA526 CPU core, which is ARMv4 based, not ARMv4T. Before moxart, we had no CONFIG_MULTI_V4 option, since no ARMv4 platform was enabled for multiplatform. This now adds the missing option, which will give us slightly more efficient code on pure moxart kernels, because we can build a pure FA526 kernel now rather than a combined FA526+ARM920T kernel that we used to. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-27Merge tag 'zynq-cleanup-for-3.15-v2' of git://git.xilinx.com/linux-xlnx into ↵Arnd Bergmann
next/cleanup2 Merge "arm: Xilinx Zynq cleanup patches for v3.15" from Michal Simek: - Redesign SLCR initialization to enable driver developing which targets SLCR space * tag 'zynq-cleanup-for-3.15-v2' of git://git.xilinx.com/linux-xlnx: ARM: zynq: Add waituart implementation ARM: zynq: Move of_clk_init from clock driver ARM: zynq: Introduce zynq_slcr_unlock() ARM: zynq: Add and use zynq_slcr_read/write() helper functions ARM: zynq: Make zynq_slcr_base static ARM: zynq: Map I/O memory on clkc init ARM: zynq: Hang iomapped slcr address on device_node ARM: zynq: Split slcr in two parts ARM: zynq: Move clock_init from slcr to common arm: dt: zynq: Add fclk-enable property to clkc node [Arnd: remove SOC_BUS support from pull request] Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-27Merge tag 'davinci-for-v3.15/soc-2' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/soc Merge "DaVinci SoC fixes for v3.15" from Sekhar Nori: Includes a patch to enable appended DTB support for DT booting on DA850 boards with older bootloaders. * tag 'davinci-for-v3.15/soc-2' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci: ARM: davinci: fix DT booting with default defconfig Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-27ARM: STi: stih41x: Add support for the FSM Serial Flash ControllerLee Jones
Here we add the necessary device nodes required for successful device probing and Pinctrl setup for the FSM when booting on an STiH415 (Orly1) or STiH416 (Orly2) based b2020 development board. Acked-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> Acked-by Angus Clark <angus.clark@st.com> Acked-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-27ARM: STi: stih416: Add support for the FSM Serial Flash ControllerLee Jones
Here we add the necessary device nodes required for successful device probing and Pinctrl setup for the FSM when booting on an STiH416 (Orly2). Acked-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> Acked-by Angus Clark <angus.clark@st.com> Acked-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-27Merge tag 'keystone-dts-fixes' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into next/dt Merge "Keystone DTS fixes for 3.15" from Santosh Shilimkar: - Few fixes found during NAND ubifs testing - Fix to build all dtbs together with dtbs - Last patch is follow up comment from previous pull request * tag 'keystone-dts-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone: ARM: dts: keystone: use common "ti,keystone" compatible instead of -evm ARM: dts: k2hk-evm: set ubifs partition size for 512M NAND ARM: dts: Build all keystone dt blobs ARM: dts: keystone: Fix control register range for clktsip ARM: dts: keystone: Fix domain register range for clkfftc1 Conflicts: arch/arm/boot/dts/Makefile Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-27Revert "dts: socfpga: Add DTS entry for adding the stmmac glue layer for ↵Arnd Bergmann
stmmac." This reverts commit 7e0b4cd06201ee9dbdf2d13bfd7b8a021b414e42. The binding changes need to be done differently as well, let's take them through netdev, and merge the dts changes in a new patch here. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-26ARM: enable fhandle in multi_v7_defconfigAlexandre Courbot
CONFIG_FHANDLE is required by systemd >= 210 to spawn a serial TTY. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-26ARM: tegra: enable fhandle in tegra_defconfigAlexandre Courbot
CONFIG_FHANDLE is required by systemd >= 210 to spawn a serial TTY. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-26ARM: update multi_v7_defconfig for TegraStephen Warren
This patch adds the same options to multi_v7_defconfig as were added to tegra_defconfig in commit d1c912c1001f "ARM: tegra: defconfig updates". (CONFIG_POWER_RESET_AS3722 is already enabled here.) Suggested-by: Olof Johansson <olof@lixom.net> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-26ARM: tegra: fix board DT pinmux setupStephen Warren
Neither Tegra114 nor Tegra124 allow "low power mode" to be configured on SDIO1 or SDIO3 drive groups. Remove the attempt to configure that option from the Dalmore and Venice2 DTs. The Venice2 DT contained duplicate configurations for most sdmmc1_* pins. Remove the duplicate pins from one of the nodes, and fix the configuration since the remaining clk pin is output-only. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-26ARM: nspire: Fix compiler warningAlexander Shiyan
CC arch/arm/mach-nspire/nspire.o arch/arm/mach-nspire/nspire.c:79:2: warning: initialization from incompatible pointer type [enabled by default] arch/arm/mach-nspire/nspire.c:79:2: warning: (near initialization for '__mach_desc_NSPIRE.restart') [enabled by default] Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-26MIPS: JZ4740: Don't select HAVE_PWMJingoo Han
The HAVE_PWM symbol is only for legacy platforms that provide the PWM API without using the generic framework. The jz4740 platform uses the generic PWM framework, after the commit "f6b8a57 pwm: Add Ingenic JZ4740 support". Signed-off-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Lars-Peter Clausen <lars@metafoo.de> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6525/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26MIPS: Restore init.h usage to arch/mips/ar7/time.cPaul Gortmaker
Commit 0046be10e0c502705fc74d91408eba13a73bc201 ("mips: delete non-required instances of include <linux/init.h>") inadvertently removed an include that was actually correct. Restore it. Note that it gets init.h implicitly anyway, so this is largely a cosmetic fixup; no build regressions were caused by this. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6416/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26MIPS: BCM47XX: Add Belkin F7Dxxxx board detectionCody P Schafer
Add a few Belkin F7Dxxxx entries, with F7D4401 sourced from online documentation and the "F7D7302" being observed. F7D3301, F7D3302, and F7D4302 are reasonable guesses which are unlikely to cause mis-detection. Signed-off-by: Cody P Schafer <devel@codyps.com> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Cc: linux-mips@linux-mips.org Cc: zajec5@gmail.com Cc: Cody P Schafer <devel@codyps.com> Patchwork: https://patchwork.linux-mips.org/patch/6594/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26MIPS: BCM47XX: Add detection and GPIO config for Siemens SE505v2Hauke Mehrtens
This adds board detection for the Siemens SE505v2 and the led gpio configuration. This board does not have any buttons. This is based on OpenWrt broadcom-diag and Manuel Munz's nvram dump. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Cc: linux-mips@linux-mips.org Cc: zajec5@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/6593/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26MIPS: BCM47XX: Add button and led configuration for some Linksys devicesHauke Mehrtens
This adds led and button GPIO configuration for Linksys wrt54g3gv2, wrt54gsv1 and wrtsl54gs. This is based on OpenWrt broadcom-diag code. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Cc: linux-mips@linux-mips.org Cc: zajec5@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/6592/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26MIPS: BCM47XX: Detect some more Linksys devicesHauke Mehrtens
The Linksys WRT54G/GS/GL family uses the same boardtype numbers, and the same gpio configuration. The boardtype numbers are changing with the hardware versions, but these hardware numbers are different or each model. Detect them all as one device, this also worked in OpenWrt. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Cc: linux-mips@linux-mips.org Cc: zajec5@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/6591/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26MIPS: cpu-probe: Add support for probing M5150 coresLeonid Yegoshin
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6597/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26MIPS: Add support for the M5150 processorLeonid Yegoshin
The M5150 core is a 32-bit MIPS RISC which implements the MIPS Architecture Release-5 in a 5-stage pipeline. In addition, it includes the MIPS Architecture Virtualization Module that enables virtualization of operating systems, which provides a scalable, trusted, and secure execution environment. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6596/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26MIPS: Add processor identifier for the M5150 processorLeonid Yegoshin
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6595/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26MIPS: Add defconfig for Malta SMVP with EVAMarkos Chandras
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6581/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26MIPS: Default NR_CPUS=8 for malta SMP defconfigsPaul Burton
The previous NR_CPUS=2 default is not an optimal default for current Malta setups where it is common to have more than 2 CPUs available. It makes sense to increase this to a number which covers all common setups currently in use, such that all of those cores are usable. 8 seems to fit that description. If the user has less than 8 CPUs & they wish to have a more optimal kernel they can simply reduce this in their config. It makes sense for the default to work on as many systems as possible. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6580/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26MIPS: Set page size to 16KB for malta SMP defconfigsPaul Burton
For Malta defconfigs which may run on an SMP configuration without hardware cache anti-aliasing, a 16KB page size is a safer default. Most notably at the moment it will avoid cache aliasing issues for multicore proAptiv systems. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6579/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26MIPS: Malta: Enable DEVTMPFSMarkos Chandras
Recent versions of udev and systemd require the kernel to be compiled with CONFIG_DEVTMPFS in order to populate the /dev directory. Most MIPS platforms have it enabled by default, so enable it for Malta configs as well. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6582/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26MIPS: Regenerate malta defconfigsPaul Burton
This patch simply regenerates the malta defconfigs such that they don't change after being used & saved as a defconfig again. ie. it is the result of running the following: for cfg in arch/mips/configs/malta*; do ARCH=mips make `basename ${cfg}` ARCH=mips make savedefconfig mv -v defconfig ${cfg} done Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6578/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26MIPS: Alchemy: pata_platform for DB1200Manuel Lauss
The au1xxx-ide driver isn't any faster than pata_platform since it spends a lot of time busy waiting for DMA to finish; faster PIO/DMA modes only work on the db1200 with a certain cpu speed, UDMA is broken, and finally the old IDE layer is on death row, so time to switch to the newer ATA layer. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/6662/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26MIPS: Alchemy: fold mach-db1xxx/db1x00 headers into board codeManuel Lauss
Merge the db1200.h and db1300.h headers into their only users. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/6660/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26MIPS: Alchemy: Unify Devboard support.Manuel Lauss
This patch merges support for all DB1xxx and PB1xxx boards into a single image, along with a new single defconfig for them. Run-tested on DB1300 and DB1500. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/6577/ Patchwork: https://patchwork.linux-mips.org/patch/6659/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26MIPS: Alchemy: Determine cohereny at runtime based on cpu typeManuel Lauss
All Alchemy chips have coherent DMA, but for example the USB or AC97 peripherals on the Au1000/1500/1100 are not. This patch uses DMA_MAYBE_COHERENT on Alchemy and sets coherentio based on CPU type. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/6576/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26MIPS: Extend DMA_MAYBE_COHERENT logic to DMA_NONCOHERENT useManuel Lauss
Setting DMA_MAYBE_COHERENT gives a platform the opportunity to select use of cache ops at boot. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/6575/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-26MIPS: Enable MIPS 3.5 features on MaltaMarkos Chandras
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26MIPS: malta: Add support for SMP EVAMarkos Chandras
Allow secondary cores to program their segment control registers during smp bootstrap code. This enables EVA on Malta SMP configurations Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26MIPS: malta: malta-init: Fix System Controller memory mapping for EVALeonid Yegoshin
Shift System Controller memory mapping to 0x80000000 Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26MIPS: malta: malta-memory: Add free_init_pages_eva() callbackMarkos Chandras
Use a Malta specific function to free the init section once the kernel has booted. When operating in EVA mode, the physical memory is shifted to 0x80000000. Kernel is loaded into 0x80000000 (virtual) so the offset between physical and virtual addresses is 0. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26MIPS: malta: malta-memory: Use the PHYS_OFFSET to build the memory mapMarkos Chandras
PHYS_OFFSET is used to denote the physical start address of the first bank of RAM. When the Malta board is in EVA mode, the physical start address of RAM is shifted to 0x80000000 so it's necessary to use this macro in order to make the code EVA agnostic. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26MIPS: malta: malta-memory: Add support for the 'ememsize' variableMarkos Chandras
The 'ememsize' variable is used to denote the real RAM which is present on the Malta board. This is different compared to 'memsize' which is capped to 256MB. The 'ememsize' is used to get the actual physical memory when setting up the Malta memory layout. This only makes sense in case the core operates in the EVA mode, and it's ignored otherwise. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26MIPS: malta: spaces.h: Add spaces.h file for Malta (EVA)Markos Chandras
Add a spaces.h file for Malta to override certain memory macros when operating in EVA mode. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26MIPS: malta: Configure Segment Control registers for EVA bootMarkos Chandras
The Malta board aliases 0x80000000 - 0xffffffff to 0x00000000 - 0x7fffffff ignoring the 256 MB IO hole in 0x10000000. The physical memory is shifted to 0x80000000 so up to 2GB can be used. Kuseg is expanded to 3GB (due to board limitations only 2GB can be accessed) and lowmem (kernel space) is expanded to 2GB. The Segment Control registers are programmed as follows: Virtual memory Physical memory Mapping 0x00000000 - 0x7fffffff 0x80000000 - 0xfffffffff MUSUK (kuseg) 0x80000000 - 0x9fffffff 0x00000000 - 0x1ffffffff MUSUK (kseg0) 0xa0000000 - 0xbf000000 0x00000000 - 0x1ffffffff MUSUK (kseg1) 0xc0000000 - 0xdfffffff - MK (kseg2) 0xe0000000 - 0xffffffff - MK (kseg3) The location of exception vectors remain the same since 0xbfc00000 (traditional exception base) still maps to 0x1fc00000 physical. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26MIPS: mm: c-r4k: Flush scache to avoid cache aliasesLeonid Yegoshin
There is a chance for the secondary cache to have memory aliases. This can happen if the bootloader is in a non-EVA mode (or even in EVA mode but with different mapping from the kernel) and the kernel switching to EVA afterwards. It's best to flush the icache to avoid having the secondary CPUs fetching stale data from it. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26MIPS: mm: c-r4k: Add support for flushing user pages from cacheMarkos Chandras
Use the userspace cache flushing functions if the interrupted process is a userspace one. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26MIPS: mm: c-r4k: Build EVA {d,i}cache flushing functionsLeonid Yegoshin
Build EVA specific cache flushing functions (ie cachee). They will be used by a subsequent patch. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26MIPS: mm: init: Add free_init_pages() callback for EVAMarkos Chandras
A core in EVA mode can have any possible segment mapping, so the default free_initmem_default() function may not always work as expected. Therefore, add a callback that platforms can use to free up the init section. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26MIPS: kernel: proc: Add EVA to the list of CPU featuresMarkos Chandras
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26MIPS: kernel: cpu-probe: Enable EVA option on supported coresMarkos Chandras
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26MIPS: asm: cpu: Add cpu flag for Enhanced Virtual AddressingMarkos Chandras
The MIPS *Aptiv family uses bit 28 in Config5 CP0 register to indicate whether the core supports EVA or not. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26MIPS: asm: page: Allow __pa_symbol overridesLeonid Yegoshin
This will allow platforms to use an alternative way to get the physical address of a symbol. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-03-26MIPS: kernel: {ftrace,kgdb}: Set correct address limit for cache flushesLeonid Yegoshin
When flushing the icache, make sure the address limit is correct so the appropriate 'cache' instruction will be used. This has no impact on cores operating in non-eva mode. However, when EVA is enabled, we ensure that 'cache' will be used instead of 'cachee'. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>