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2014-03-25Merge tag 'kvm-s390-20140325' of ↵Paolo Bonzini
git://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux into kvm-next 3 fixes - memory leak on certain SIGP conditions - wrong size for idle bitmap (always too big) - clear local interrupts on initial CPU reset 1 performance improvement - improve performance with many guests on certain workloads
2014-03-25KVM: s390: clear local interrupts at cpu initial resetJens Freimann
Empty list of local interrupts when vcpu goes through initial reset to provide a clean state Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2014-03-25KVM: s390: Fix possible memory leak in SIGP functionsThomas Huth
When kvm_get_vcpu() returned NULL for the destination CPU in __sigp_emergency() or __sigp_external_call(), the memory for the "inti" structure was not released anymore. This patch fixes this issue by moving the check for !dst_vcpu before the kzalloc() call. Signed-off-by: Thomas Huth <thuth@linux.vnet.ibm.com> Reviewed-by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2014-03-25KVM: s390: fix calculation of idle_mask array sizeJens Freimann
We need BITS_TO_LONGS, not sizeof(long) to calculate the correct size. idle_mask is a bitmask, each bit representing the state of a cpu. The desired outcome is an array of unsigned long fields that can fit KVM_MAX_VCPUS bits. We should not use sizeof(long) which returnes the size in bytes, but BITS_TO_LONGS Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com> Reviewed-by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2014-03-25KVM: s390: randomize sca addressChristian Borntraeger
We allocate a page for the 2k sca, so lets use the space to improve hit rate of some internal cpu caches. No need to change the freeing of the page, as this will shift away the page offset bits anyway. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: David Hildenbrand <dahi@linux.vnet.ibm.com>
2014-03-25crypto: x86/sha1 - reduce size of the AVX2 asm implementationMathias Krause
There is really no need to page align sha1_transform_avx2. The default alignment is just fine. This is not the hot code but only the entry point, after all. Cc: Chandramouli Narayanan <mouli@linux.intel.com> Signed-off-by: Mathias Krause <minipli@googlemail.com> Reviewed-by: H. Peter Anvin <hpa@linux.intel.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2014-03-25crypto: x86/sha1 - fix stack alignment of AVX2 variantMathias Krause
The AVX2 implementation might waste up to a page of stack memory because of a wrong alignment calculation. This will, in the worst case, increase the stack usage of sha1_transform_avx2() alone to 5.4 kB -- way to big for a kernel function. Even worse, it might also allocate *less* bytes than needed if the stack pointer is already aligned bacause in that case the 'sub %rbx, %rsp' is effectively moving the stack pointer upwards, not downwards. Fix those issues by changing and simplifying the alignment calculation to use a 32 byte alignment, the alignment really needed. Cc: Chandramouli Narayanan <mouli@linux.intel.com> Signed-off-by: Mathias Krause <minipli@googlemail.com> Reviewed-by: H. Peter Anvin <hpa@linux.intel.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2014-03-25crypto: x86/sha1 - re-enable the AVX variantMathias Krause
Commit 7c1da8d0d0 "crypto: sha - SHA1 transform x86_64 AVX2" accidentally disabled the AVX variant by making the avx_usable() test not only fail in case the CPU doesn't support AVX or OSXSAVE but also if it doesn't support AVX2. Fix that regression by splitting up the AVX/AVX2 test into two functions. Also test for the BMI1 extension in the avx2_usable() test as the AVX2 implementation not only makes use of BMI2 but also BMI1 instructions. Cc: Chandramouli Narayanan <mouli@linux.intel.com> Signed-off-by: Mathias Krause <minipli@googlemail.com> Reviewed-by: H. Peter Anvin <hpa@linux.intel.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2014-03-25Revert "xen: properly account for _PAGE_NUMA during xen pte translations"David Vrabel
This reverts commit a9c8e4beeeb64c22b84c803747487857fe424b68. PTEs in Xen PV guests must contain machine addresses if _PAGE_PRESENT is set and pseudo-physical addresses is _PAGE_PRESENT is clear. This is because during a domain save/restore (migration) the page table entries are "canonicalised" and uncanonicalised". i.e., MFNs are converted to PFNs during domain save so that on a restore the page table entries may be rewritten with the new MFNs on the destination. This canonicalisation is only done for PTEs that are present. This change resulted in writing PTEs with MFNs if _PAGE_PROTNONE (or _PAGE_NUMA) was set but _PAGE_PRESENT was clear. These PTEs would be migrated as-is which would result in unexpected behaviour in the destination domain. Either a) the MFN would be translated to the wrong PFN/page; b) setting the _PAGE_PRESENT bit would clear the PTE because the MFN is no longer owned by the domain; or c) the present bit would not get set. Symptoms include "Bad page" reports when munmapping after migrating a domain. Signed-off-by: David Vrabel <david.vrabel@citrix.com> Acked-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Cc: <stable@vger.kernel.org> [3.12+]
2014-03-24Merge branch 'parisc-3.14' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux Pull parisc updates from Helge Deller: - revert parts of the latest patch regarding font selection with STICON console - wire up the utimes() syscall for parisc - remove the unused parisc tmpalias code and unnecessary arch*relax defines * 'parisc-3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux: parisc: locks: remove redundant arch_*_relax operations parisc: wire up sys_utimes parisc: Remove unused CONFIG_PARISC_TMPALIAS code partly revert commit 8a10bc9: parisc/sti_console: prefer Linux fonts over built-in ROM fonts
2014-03-24Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparcLinus Torvalds
Pull sparc fixes from David Miller: 1) Do serial locking in a way that makes things clear that these are IRQ spinlocks. 2) Conversion to generic idle loop broke first generation Niagara machines, need to have %pil interrupts enabled during cpu yield hypervisor call. 3) Do not use magic constants for iterations over tsb tables, from Doug Wilson. 4) Fix erroneous truncation of 64-bit system call return values to 32-bit. From Dave Kleikamp. * git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc: sparc64: Make sure %pil interrupts are enabled during hypervisor yield. sparc64:tsb.c:use array size macro rather than number sparc64: don't treat 64-bit syscall return codes as 32-bit sparc: serial: Clean up the locking for -rt
2014-03-24uml/net_kern: Call dev_consume_skb_any instead of dev_kfree_skb.Eric W. Biederman
Replace dev_kfree_skb with dev_consume_skb_any in uml_net_start_xmit as it can be called in hard irq and other contexts. dev_consume_skb_any is used as uml_net_start_xmit typically consumes (not drops) packets. Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
2014-03-24sparc64: Make sure %pil interrupts are enabled during hypervisor yield.David S. Miller
In arch_cpu_idle() we must enable %pil based interrupts before potentially invoking the hypervisor cpu yield call. As per the Hypervisor API documentation for cpu_yield: Interrupts which are blocked by some mechanism other that pstate.ie (for example %pil) are not guaranteed to cause a return from this service. It seems that only first generation Niagara chips are hit by this bug. My best guess is that later chips implement this in hardware and wake up anyways from %pil events, whereas in first generation chips the yield is implemented completely in hypervisor code and requires %pil to be enabled in order to wake properly from this call. Fixes: 87fa05aeb3a5 ("sparc: Use generic idle loop") Reported-by: Fabio M. Di Nitto <fabbione@fabbione.net> Reported-by: Jan Engelhardt <jengelh@inai.de> Tested-by: Jan Engelhardt <jengelh@inai.de> Signed-off-by: David S. Miller <davem@davemloft.net>
2014-03-24x86, kaslr: fix module lock ordering problemKees Cook
There was a potential lock ordering problem with the module kASLR patch ("x86, kaslr: randomize module base load address"). This patch removes the usage of the module_mutex and creates a new mutex to protect the module base address offset value. Chain exists of: text_mutex --> kprobe_insn_slots.mutex --> module_mutex [ 0.515561] Possible unsafe locking scenario: [ 0.515561] [ 0.515561] CPU0 CPU1 [ 0.515561] ---- ---- [ 0.515561] lock(module_mutex); [ 0.515561] lock(kprobe_insn_slots.mutex); [ 0.515561] lock(module_mutex); [ 0.515561] lock(text_mutex); [ 0.515561] [ 0.515561] *** DEADLOCK *** Reported-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Andy Honig <ahonig@google.com> Signed-off-by: Kees Cook <keescook@chromium.org> Reviewed-by: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2014-03-24x86, vdso: Fix size of get_unmapped_area()Stefani Seibold
The size of the reserved memory for a 32 bit vdso must be the size of the 32 bit vDSO in pages + HPET page + VVAR page. One page is not enough for this. Grrrr.... silly copy and paste bug, was right in previous patch. Signed-off-by: Stefani Seibold <stefani@seibold.net> Cc: Andy Lutomirski <luto@amacapital.net> Link: http://lkml.kernel.org/r/1395592694-20571-1-git-send-email-stefani@seibold.net Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2014-03-24ARM: bockw: fixup SND_SOC_DAIFMT_CBx_CFx flagsKuninori Morimoto
SND_SOC_DAIFMT_CBx_CFx means "codec" side master/slave mode. Then, rcar will be master mode if it was SND_SOC_DAIFMT_CBS_CFS. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Mark Brown <broonie@linaro.org>
2014-03-24arm64: Remove pgprot_dmacoherent()Catalin Marinas
Since this macro is identical to pgprot_writecombine() and is only used in a single place, remove it completely to avoid confusion. On ARMv7+ processors, the coherent DMA mapping must be Normal NonCacheable (a.k.a. writecombine) to avoid mismatched hardware attribute aliases (with the kernel linear mapping as Normal Cacheable). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-03-24arm64: Support DMA_ATTR_WRITE_COMBINELaura Abbott
DMA_ATTR_WRITE_COMBINE is currently ignored. Set the pgprot appropriately for non coherent opperations. Signed-off-by: Laura Abbott <lauraa@codeaurora.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-03-24arm64: Implement custom mmap functions for dma mappingLaura Abbott
The current dma_ops do not specify an mmap function so maping falls back to the default implementation. There are at least two issues with using the default implementation: 1) The pgprot is always pgprot_noncached (strongly ordered) memory even with coherent operations 2) dma_common_mmap calls virt_to_page on the remapped non-coherent address which leads to invalid memory being mapped. Fix both these issue by implementing a custom mmap function which correctly accounts for remapped addresses and sets vm_pg_prot appropriately. Signed-off-by: Laura Abbott <lauraa@codeaurora.org> [catalin.marinas@arm.com: replaced "arm64_" with "__" prefix for consistency] Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-03-24Merge remote-tracking branch 'scott/next' into nextBenjamin Herrenschmidt
Freescale updates from Scott. Mostly support for critical and machine check exceptions on 64-bit BookE, some new PCI suspend/resume work and misc bits.
2014-03-24powerpc/book3s: Fix CFAR clobbering issue in machine check handler.Mahesh Salgaonkar
While checking powersaving mode in machine check handler at 0x200, we clobber CFAR register. Fix it by saving and restoring it during beq/bgt. Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24powerpc/compat: 32-bit little endian machine name is ppcle, not ppcAnton Blanchard
I noticed this when testing setarch. No, we don't magically support a big endian userspace on a little endian kernel. Signed-off-by: Anton Blanchard <anton@samba.org> Cc: stable@vger.kernel.org # v3.10+ Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24powerpc/le: Big endian arguments for ppc_rtas()Greg Kurz
The ppc_rtas() syscall allows userspace to interact directly with RTAS. For the moment, it assumes every thing is big endian and returns either EINVAL or EFAULT when called in a little endian environment. As suggested by Benjamin, to avoid bugs when userspace wants to pass a non 32 bit value to RTAS, it is far better to stick with a simple rationale: ppc_rtas() should be called with a big endian rtas_args structure. With this patch, it is now up to userspace to forge big endian arguments, as expected by RTAS. Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24powerpc: Use default set of netfilter modules (CONFIG_NETFILTER_ADVANCED=n)Anton Blanchard
Our netfilter options are stale and important things like masquerading are no longer enabled. Instead of trying to keep up with any updates, set CONFIG_NETFILTER_ADVANCED=n on ppc64* and pseries* defconfigs. This enables the most common netfilter modules for us. While here, enable the network bridge module which is heavily used in KVM setups. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24powerpc/defconfigs: Enable THP in pseries defconfigAneesh Kumar K.V
We also set it to be enabled always. This helps in wider testing Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24powerpc/mm: Make sure a local_irq_disable prevent a parallel THP splitAneesh Kumar K.V
We have generic code like the one in get_futex_key that assume that a local_irq_disable prevents a parallel THP split. Support that by adding a dummy smp call function after setting _PAGE_SPLITTING. Code paths like get_user_pages_fast still need to check for _PAGE_SPLITTING after disabling IRQ which indicate that a parallel THP splitting is ongoing. Now if they don't find _PAGE_SPLITTING set, then we can be sure that parallel split will now block in pmdp_splitting flush until we enables IRQ Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Acked-by: Rik van Riel <riel@redhat.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24powerpc: Rate-limit users spamming kernel log bufferMichael Neuling
The facility unavailable exception can be triggered from userspace by accessing PMU registers when EBB is not enabled. This causes the included pr_err() to run, hence spamming the kernel log buffer. This avoids this by rate limiting these messages. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24powerpc/perf: Fix handling of L3 events with bank == 1Michael Ellerman
Currently we reject events which have the L3 bank == 1, such as 0x000084918F, because the cache field is non-zero. However that is incorrect, because although the bank is non-zero, the value we would write into MMCRC is zero, and so we can count the event. So fix the check to ignore the bank selector when checking whether the cache selector is non-zero. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24powerpc/perf: Add kconfig option for hypervisor provided countersCody P Schafer
The commit adds a Kconfig option which allows the hv_gpci and hv_24x7 PMUs, added in the preceeding commits, to be built. Signed-off-by: Cody P Schafer <cody@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24powerpc/perf: Add support for the hv 24x7 interfaceCody P Schafer
This provides a basic interface between hv_24x7 and perf. Similar to the one provided for gpci, it lacks transaction support and does not list any events. Example usage via perf tool: perf stat -e 'hv_24x7/domain=2,offset=8,starting_index=0,lpar=0xffffffff/' -r 0 -C 0 -x ' ' sleep 0.1 Signed-off-by: Cody P Schafer <cody@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24powerpc/perf: Add support for the hv gpci (get performance counter info) ↵Cody P Schafer
interface This provides a basic link between perf and hv_gpci. Notably, it does not yet support transactions and does not list any events (they can still be manually composed). Example usage via perf tool: perf stat -e 'hv_gpci/counter_info_version=3,offset=0,length=8,secondary_index=0,starting_index=0xffffffff,request=0x10/' -r 0 -C 0 -x ' ' sleep 0.1 Signed-off-by: Cody P Schafer <cody@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24powerpc/perf: Add macros for defining event fields & formatsCody P Schafer
Add two macros which generate functions to extract the relevent bits from event->attr.config{,1,2}. EVENT_DEFINE_RANGE() defines an accessor for a range of bits in the event, as well as a "max" function that gives the maximum value of the field based on the bit width. EVENT_DEFINE_RANGE_FORMAT() defines the accessor & max routine and also a format attribute for use in the PMU's attr_groups. Signed-off-by: Cody P Schafer <cody@linux.vnet.ibm.com> [mpe: move to powerpc, ugly but descriptive macro names] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24powerpc/perf: Add a shared interface to get gpci version and capabilitiesCody P Schafer
This exposes a simple way to grab the firmware provided collect_priveliged, ga, expanded, and lab capability bits. All of these bits come in from the same gpci request, so we've exposed all of them. Only the collect_priveliged bit is really used by the hv-gpci/hv-24x7 code, the other bits are simply exposed in sysfs to inform the user. Signed-off-by: Cody P Schafer <cody@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24powerpc/perf: Add 24x7 interface headersCody P Schafer
24x7 (also called hv_24x7 or H_24X7) is an interface to obtain performance counters from the hypervisor. These counters do not have a fixed format/possition and are instead documented in a "24x7 Catalog", which is provided by the hypervisor (that interface is also documented paritialy in the included hv-24x7-catalog.h and fully in at https://raw.githubusercontent.com/jmesmon/catalog-24x7/master/hv-24x7-catalog.h ). The 24x7 data access is simply a copy operation into a 4 dimentional array of 64bit counters (from hypervisor to kernel memory). There is no interupt triggered on overflow, these are completely disjoint from the typical power pmu. This method of obtaining performance counters from the hypervisor is intended to paritialy replace the gpci interface. Signed-off-by: Cody P Schafer <cody@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24powerpc/perf: Add hv_gpci interface headerCody P Schafer
"H_GetPerformanceCounterInfo" (refered to as hv_gpci or just gpci from here on) is an interface to retrieve specific performance counters and other data from the hypervisor. All outputs have a fixed format. This header only describes the portions of the interface that we plan on using in linux at this time. Signed-off-by: Cody P Schafer <cody@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24powerpc: Add hvcalls for 24x7 and gpci (Get Performance Counter Info)Cody P Schafer
Signed-off-by: Cody P Schafer <cody@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24powerpc/perf: Enable BHRB access for EBB eventsMichael Ellerman
The previous commit added constraint and register handling to allow processes using EBB (Event Based Branches) to request access to the BHRB (Branch History Rolling Buffer). With that in place we can allow processes using EBB to access the BHRB. This is achieved by setting BHRBA in MMCR0 when we enable EBB access. We must also clear BHRBA when we are disabling. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24powerpc/perf: Add BHRB constraint and IFM MMCRA handling for EBBMichael Ellerman
We want a way for users of EBB (Event Based Branches) to also access the BHRB (Branch History Rolling Buffer). EBB does not interoperate with our existing BHRB support, which is wired into the generic Linux branch stack sampling support. To support EBB & BHRB we add three new bits to the event code. The first bit indicates that the event wants access to the BHRB, and the other two bits indicate the desired IFM (Instruction Filtering Mode). We allow multiple events to request access to the BHRB, but they must agree on the IFM value. Events which are not interested in the BHRB can also interoperate with events which do. Finally we program the desired IFM value into MMCRA. Although we do this for every event, we know that the value will be identical for all events that request BHRB access. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24powerpc/perf: Avoid mutating event in power8_get_constraint()Michael Ellerman
We only need to mask the EBB bit out of the event for the check of the special PMC 5 & 6 events. So use a local to do it just for that code, rather than changing the event value for the life of the function. While we're there move the set of mask and value after all the checks. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24powerpc/perf: Clean up the EBB hash defines a littleMichael Ellerman
Rather than using PERF_EVENT_CONFIG_EBB_SHIFT everywhere, add an EVENT_EBB_SHIFT like every other event and use that. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24powerpc/perf: Reject EBB events which specify a sample_typeMichael Ellerman
Although we already block EBB events which request sampling using sample_period, technically it's possible for an event to set sample_type but not sample_period. Nothing terrible will happen if an EBB event does specify sample_type, but it signals a major confusion on the part of userspace, and so we do them the favor of rejecting it. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24powerpc/perf: Add lost exception workaroundMichael Ellerman
Some power8 revisions have a hardware bug where we can lose a PMU exception, this commit adds a workaround to detect the bad condition and rectify the situation. See the comment in the commit for a full description. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24powerpc: Add a cpu feature CPU_FTR_PMAO_BUGMichael Ellerman
Some power8 revisions have a hardware bug where we can lose a Performance Monitor (PMU) exception under certain circumstances. We will be adding a workaround for this case, see the next commit for details. The observed behaviour is that writing PMAO doesn't cause an exception as we would expect, hence the name of the feature. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24powerpc/perf: Define perf_event_print_debug() to print PMU register valuesAnshuman Khandual
Currently the sysrq ShowRegs command does not print any PMU registers as we have an empty definition for perf_event_print_debug(). This patch defines perf_event_print_debug() to print various PMU registers. Example output: CPU: 0 PMU registers, ppmu = POWER7 n_counters = 6 PMC1: 00000000 PMC2: 00000000 PMC3: 00000000 PMC4: 00000000 PMC5: 00000000 PMC6: 00000000 PMC7: deadbeef PMC8: deadbeef MMCR0: 0000000080000000 MMCR1: 0000000000000000 MMCRA: 0f00000001000000 SIAR: 0000000000000000 SDAR: 0000000000000000 SIER: 0000000000000000 Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com> [mpe: Fix 32 bit build and rework formatting for compactness] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24powerpc/perf: Make some new raw event codes available in sysfsAnshuman Khandual
This patchset adds some missing event list for POWER7 PMU raw events which are exported through sysfs interface. Also updates the ABI documentation to add all the sysfs exported raw events. Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24powerpc/powernv: Enable fetching of platform sensor dataNeelesh Gupta
This patch enables fetching of various platform sensor data through OPAL and expects a sensor handle from the driver to pass to OPAL. Signed-off-by: Neelesh Gupta <neelegup@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24powerpc/powernv: Enable reading and updating of system parametersNeelesh Gupta
This patch enables reading and updating of system parameters through OPAL call. Signed-off-by: Neelesh Gupta <neelegup@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-24powerpc/powernv: Infrastructure to support OPAL async completionNeelesh Gupta
This patch adds support for notifying the clients of their request completion. Clients request for the token before making OPAL call and then wait for the response. This patch uses messaging infrastructure to pull the data to linux by registering itself for the message type OPAL_MSG_ASYNC_COMP. Signed-off-by: Neelesh Gupta <neelegup@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-03-23parisc: locks: remove redundant arch_*_relax operationsWill Deacon
Now that the arch_{spin,read,write}_relax macros default to cpu_relax(), remove the redundant definitions for parisc. Cc: Helge Deller <deller@gmx.de> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Helge Deller <deller@gmx.de>
2014-03-23parisc: wire up sys_utimesHelge Deller
We seem to be nearly the only platform which does not provide the sys_utimes syscall. Adding it now makes our life much easier with userspace applications (like dietlibc and e2fsprogs) since we then behave like all other platforms too and don't need extra patches which are hard to get upstream anyway because we are not a mainstream architecture. Signed-off-by: Helge Deller <deller@gmx.de> Cc: stable@vger.kernel.org # v3.13