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2014-07-31x86, apic: Remove x86_32_numa_cpu_node callbackDavid Rientjes
Since commit b5660ba76b41 ("x86, platforms: Remove NUMAQ") removed NUMAQ, the x86_32_numa_cpu_node() apic callback has been obsolete. Remove it. Signed-off-by: David Rientjes <rientjes@google.com> Link: http://lkml.kernel.org/r/alpine.DEB.2.02.1407302348060.17503@chino.kir.corp.google.com Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2014-07-31x86/kvm: Resolve shadow warnings in macro expansionMark D Rustad
Resolve shadow warnings that appear in W=2 builds. Instead of using ret to hold the return pointer, save the length in a new variable saved_len and compute the pointer on exit. This also resolves a very technical error, in that ret was declared as a const char *, when it really was a char * const. Signed-off-by: Mark Rustad <mark.d.rustad@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-07-31Merge tag 'kvm-s390-20140730' of ↵Paolo Bonzini
git://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux into kvm-next Two fixes for recently introduced regressions - a memory leak on busy SIGP - pontentially lost SIGP stop in rare situations (shutdown loops) The first issue is not part of a released kernel. The 2nd issue is present in all KVM versions, but did not trigger before commit 7dfc63cf977447e09b1072911c2 (KVM: s390: allow only one SIGP STOP (AND STORE STATUS) at a time) with Linux as a guest. So no need for cc stable
2014-07-31arm64: KVM: GICv3: move system register access to msr_s/mrs_sMarc Zyngier
Commit 72c583951526 (arm64: gicv3: Allow GICv3 compilation with older binutils) changed the way we express the GICv3 system registers, but couldn't change the occurences used by KVM as the code wasn't merged yet. Just fix the accessors. Cc: Will Deacon <will.deacon@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Christoffer Dall <christoffer.dall@linaro.org> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
2014-07-31Revert "arm64: dmi: Add SMBIOS/DMI support"Will Deacon
This reverts commit a28e3f4b90543f7c249a956e3ca518e243a04618. Ard and Yi Li report that this patch is broken by design, so revert it and let them sort it out for 3.18 instead. Reported-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
2014-07-31MIPS: GIC: Prevent array overrunJeffrey Deans
A GIC interrupt which is declared as having a GIC_MAP_TO_NMI_MSK mapping causes the cpu parameter to gic_setup_intr() to be increased to 32, causing memory corruption when pcpu_masks[] is written to again later in the function. Signed-off-by: Jeffrey Deans <jeffrey.deans@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: stable@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7375/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-31arm64: fpsimd: fix a typo in fpsimd_save_partial_state ENDPROCbyungchul.park
Commit 190f1ca85d07 ("arm64: add support for kernel mode NEON in interrupt context") introduced a typing error in fpsimd_save_partial_state ENDPROC. This patch fixes the typing error. Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: byungchul.park <byungchul.park@lge.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2014-07-31arm64: don't call break hooks for BRK exceptions from EL0Will Deacon
Our break hooks are used to handle brk exceptions from kgdb (and potentially kprobes if that code ever resurfaces), so don't bother calling them if the BRK exception comes from userspace. This prevents userspace from trapping to a kdb shell on systems where kgdb is enabled and active. Cc: <stable@vger.kernel.org> Reported-by: Omar Sandoval <osandov@osandov.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2014-07-31KVM: PPC: PR: Handle FSCR feature deselectsAlexander Graf
We handle FSCR feature bits (well, TAR only really today) lazily when the guest starts using them. So when a guest activates the bit and later uses that feature we enable it for real in hardware. However, when the guest stops using that bit we don't stop setting it in hardware. That means we can potentially lose a trap that the guest expects to happen because it thinks a feature is not active. This patch adds support to drop TAR when then guest turns it off in FSCR. While at it it also restricts FSCR access to 64bit systems - 32bit ones don't have it. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-07-31KVM: s390: rework broken SIGP STOP interrupt handlingDavid Hildenbrand
A VCPU might never stop if it intercepts (for whatever reason) between "fake interrupt delivery" and execution of the stop function. Heart of the problem is that SIGP STOP is an interrupt that has to be processed on every SIE entry until the VCPU finally executes the stop function. This problem was made apparent by commit 7dfc63cf977447e09b1072911c2 (KVM: s390: allow only one SIGP STOP (AND STORE STATUS) at a time). With the old code, the guest could (incorrectly) inject SIGP STOPs multiple times. The bug of losing a sigp stop exists in KVM before 7dfc63cf97, but it was hidden by Linux guests doing a sigp stop loop. The new code (rightfully) returns CC=2 and does not queue a new interrupt. This patch is a simple fix of the problem. Longterm we are going to rework that code - e.g. get rid of the action bits and so on. Signed-off-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> [some additional patch description]
2014-07-31ARM: config: enable ARCH_HIX5HD2Haojian Zhuang
Since both ARCH_HI3xxx and ARCH_HIX5HD2 are based on Cortex A9 & they're using similiar kernel features, make them share the hi3xxx_config. And add it into multi_v7_defconfig too. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Acked-by: Wei Xu <xuwei5@hisilicon.com> [olof: also turn on ARCH_HISI in multi_v7] Signed-off-by: Olof Johansson <olof@lixom.net>
2014-07-30Merge tag 'v3.17-rockchip-rk3xxx-dts-2' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt Merge "two more dts changes for Rockchip Cortex-A9 SoCs" from Heiko Stübner: Watchdog nodes and a duplicate pinctrl property. * tag 'v3.17-rockchip-rk3xxx-dts-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rockchip: add watchdog node ARM: dts: rockchip: remove pinctrl setting from radxarock uart2 Signed-off-by: Olof Johansson <olof@lixom.net>
2014-07-30ARM: hisi: remove smp from machine descriptorHaojian Zhuang
Use CPU_METHOD_OF_DECLARE() instead. And declare smp method in dts file. Changelog: v6: * Use hisilicon,hi3620-smp as enable-method property in Hi3620 dts. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Acked-by: Wei Xu <xuwei5@hisilicon.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2014-07-30power: reset: move hisilicon reboot codeHaojian Zhuang
Move reboot code from hisilicon platform driver into reset driver. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Acked-by: Wei Xu <xuwei5@hisilicon.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2014-07-30ARM: dts: Add hix5hd2-dkb dts file.Haifeng Yan
Add dts file for Hisilicon x5hd2 development kit board. Signed-off-by: Haifeng Yan <yanhaifeng@gmail.com> Signed-off-by: Jiancheng Xue <jchxue@gmail.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Acked-by: Wei Xu <xuwei5@hisilicon.com> [olof: Rename dts/dtsi to include hisi prefix] Signed-off-by: Olof Johansson <olof@lixom.net>
2014-07-30ARM: debug: Rename Hi3716 to HIX5HD2Haifeng Yan
Rename Hisilicon HI3716 to HIX5HD2 and add dependency on ARCH_HIX5HD2. HiX5HD2 is a SoC with dual Cortex A9 cores for STB market, and original Hi3xxx SoC is for mobile market. To avoid confusing the two types of SoCs and also because of different implementation (SMP, IPs integrated and earlycon config), rename Hi3716 to HIX5HD2 and add ARCH_HIX5HD2. Signed-off-by: Haifeng Yan <yanhaifeng@gmail.com> Signed-off-by: Jiancheng Xue <jchxue@gmail.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Acked-by: Wei Xu <xuwei5@hisilicon.com> [olof: fixed description typos] Signed-off-by: Olof Johansson <olof@lixom.net>
2014-07-30ARM: hisi: enable hix5hd2 SoCHaifeng Yan
Enable support for the Hisilicon HiX5HD2 SoC. This HiX5HD2 SoC series support both single and dual Cortex-A9 cores. Add ARCH_HIX5HD2 to distinguish HiX5HD2 from Hi3xxx. They are different in implementation such as SMP, IPs integarted and earlycon configure. Signed-off-by: Haifeng Yan <yanhaifeng@gmail.com> Signed-off-by: Jiancheng Xue <jchxue@gmail.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Acked-by: Wei Xu <xuwei5@hisilicon.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2014-07-30ARM: hisi: add ARCH_HISIHaojian Zhuang
Since multiple ARCH configuration will be appended into mach-hisi directory, add ARCH_HISI as common configuration for different platforms in mach-hisi. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Acked-by: Wei Xu <xuwei5@hisilicon.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2014-07-31powerpc/t2080rdb: Add T2080RDB board supportShengzhou Liu
T2080PCIe-RDB is a Freescale Reference Design Board that hosts T2080 SoC. The board feature overview: Processor: - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz DDR Memory: - Single memory controller capable of supporting DDR3 and DDR3-LP devices - 72bit 4GB DDR3-LP SODIMM in slot Ethernet interfaces: - Two 1Gbps RGMII ports on-board - Two 10Gbps SFP+ ports on-board - Two 10Gbps Base-T ports on-board Accelerator: - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC IFC/Local Bus - NOR: 128MB 16-bit NOR flash - NAND: 1GB 8-bit NAND flash - CPLD: for system controlling with programable header on-board eSPI: - 64MB N25Q512 SPI flash USB: - Two USB2.0 ports with internal PHY (both Type-A) PCIe: - One PCIe x4 goldfinger(support SR-IOV) - One PCIe x4 slot - One PCIe x2 end-point device (C293 crypto co-processor) SATA: - Two SATA 2.0 ports on-board SDHC: - support a MicroSD/TF card on-board I2C: - Four I2C controllers. UART: - Dual 4-pins UART serial ports Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2014-07-30Merge tag 'v3.17-rockchip-rk3288-2' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt Merge "Basic rk3288 usb support" from Heiko Stübner: Add support for rk3288 ehci controllers. * tag 'v3.17-rockchip-rk3288-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: Enable USB host0 (EHCI) on rk3288-evb ARM: dts: add rk3288 ehci usb devices ARM: dts: Turn on USB host vbus on rk3288-evb Signed-off-by: Olof Johansson <olof@lixom.net>
2014-07-31ARM: dts: Enable USB host0 (EHCI) on rk3288-evbDoug Anderson
This is the top USB port on the evb (the one closest to the Ethernet connector). Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-07-31ARM: dts: add rk3288 ehci usb devicesKever Yang
rk3288 has two kind of usb controller; this adds the ehci variant for host0 and hsic. At the moment we don't add any phys for these controllers, but the default settings seem to work OK. There is a hardware problem in ohci controller which make it unavailable and host0 controller can only support high-speed devices. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-07-31ARM: dts: Turn on USB host vbus on rk3288-evbDoug Anderson
There is no phy driver that works on the Rockchip board for either USB host port yet. For now just hardcode the vbus signal to be on all the time which makes both the dwc2 host and the EHCI port work. Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-07-30MIPS: ptrace: Change GP regset to use correct core dump register layoutAlex Smith
Commit 6a9c001b7ec3 ("MIPS: Switch ELF core dumper to use regsets.") switched the core dumper to use regsets, however the GP regset code simply makes a direct copy of the kernel's pt_regs, which does not match the original core dump register layout as defined in asm/reg.h. Furthermore, the definition of pt_regs can vary with certain Kconfig variables, therefore the GP regset can never be relied upon to return registers in the same layout. Therefore, this patch changes the GP regset to match the original core dump layout. The layout differs for 32- and 64-bit processes, so separate implementations of the get/set functions are added for the 32- and 64-bit regsets. Signed-off-by: Alex Smith <alex@alex-smith.me.uk> Cc: <stable@vger.kernel.org> # v3.13+ Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7452/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-30MIPS: asm/reg.h: Make 32- and 64-bit definitions available at the same timeAlex Smith
Get rid of the WANT_COMPAT_REG_H test and instead define both the 32- and 64-bit register offset definitions at the same time with MIPS{32,64}_ prefixes, then define the existing EF_* names to the correct definitions for the kernel's bitness. This patch is a prerequisite of the following bug fix patch. Signed-off-by: Alex Smith <alex@alex-smith.me.uk> Cc: <stable@vger.kernel.org> # v3.13+ Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7451/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-30MIPS: ptrace: Test correct task's flags in task_user_regset_view()Alex Smith
task_user_regset_view() should test for TIF_32BIT_REGS in the flags of the specified task, not of the current task. Signed-off-by: Alex Smith <alex@alex-smith.me.uk> Cc: <stable@vger.kernel.org> # v3.13+ Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7450/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-30MIPS: ptrace: Avoid smp_processor_id() when retrieving FPU IRAlex Smith
Whenever ptrace attempts to retrieve the FPU implementation register it accesses it through current_cpu_data, which calls smp_processor_id(). Since the code may execute with preemption enabled, this can trigger a warning. Fix this by using boot_cpu_data to get the IR instead. Signed-off-by: Alex Smith <alex@alex-smith.me.uk> Cc: <stable@vger.kernel.org> # v3.15+ Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7449/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-30MIPS: BCM47XX: Detect more then 128 MiB of RAM (HIGHMEM)Rafał Miłecki
So far BCM47XX can only detect amount of HIGHMEM. It still requires adding (registering) and well-testing before enabling by default. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Acked-by: Hauke Mehrtens <hauke@hauke-m.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7396/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-30Revert "MIPS: Delete unused function add_temporary_entry."Rafał Miłecki
This reverts commit d7a887a73dec6c387b02a966a71aac767bbd9ce6. Function add_temporary_entry is needed by bcm47xx to support highmem. We need to add a temporary entry to check for amount of RAM. The only change made in this revert was replacing (ENTER|EXIT)_CRITICAL. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Cc: linux-mips@linux-mips.org Cc: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: https://patchwork.linux-mips.org/patch/7395/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-30MIPS: BCM47XX: Devices database update for 3.17Rafał Miłecki
Detect more devices and register leds & buttons for them. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7394/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-30Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/netDavid S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-07-30MIPS: BCM47XX: Select SYS_SUPPORTS_HIGHMEM for BCM47XX_BCMARafał Miłecki
It seems that bcm47xx can handle only 128 MiB of RAM directly. There are few devices with 256 MiB, but Broadcom's SDK uses highmem to handle anything above 128 MiB. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Cc: linux-mips@linux-mips.org Cc: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: https://patchwork.linux-mips.org/patch/7101/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-30MIPS: BCM47XX: Move shared symbols to the config BCM47XXRafał Miłecki
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Cc: linux-mips@linux-mips.org Cc: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: https://patchwork.linux-mips.org/patch/7100/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-30MIPS: BCM47xx: Fix LEDs on WRT54GS V1.0Rafał Miłecki
Reported-by: Catalin Patulea <cat@vv.carleton.ca> Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Acked-by: Hauke Mehrtens <hauke@hauke-m.de> Cc: linux-mips@linux-mips.org Cc: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: https://patchwork.linux-mips.org/patch/7113/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-30MIPS: BCM47xx: Distinguish WRT54G series devices by boardtypeRafał Miłecki
Catalin reported that GPIOs used by bcm47xx don't match layout of his WRT54GS V1.0 board. It seems we need to distinguish these 54G* devices. Reported-by: Catalin Patulea <cat@vv.carleton.ca> Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Cc: linux-mips@linux-mips.org Cc: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: https://patchwork.linux-mips.org/patch/7112/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-30Merge tag 'zynq-dt-for-3.17-3' of git://git.xilinx.com/linux-xlnx into next/dtOlof Johansson
Merge "Xilinx Zynq dt changes for v3.17 - third pull request" from Michal Simek: arm: Xilinx Zynq dt patches for v3.17 third pull request - Add Adapteva Parallella board/DT - Add SPI nodes - Add CAN nodes - Clean Zynq description * tag 'zynq-dt-for-3.17-3' of git://git.xilinx.com/linux-xlnx: ARM: zynq: DT: Clarify Xilinx Zynq platform ARM: zynq: DT: Remove DMA from board DTs ARM: zynq: DT: Add CAN node ARM: dts: zynq: Add SPI ARM: dts: zynq: Add DMAC for Parallella ARM: dts: zynq: Add Parallella device tree Documentation: devicetree: Adapteva boards Documentation: devicetree: Adapteva vendor prefix Signed-off-by: Olof Johansson <olof@lixom.net>
2014-07-30ARM: tegra: apalis t30: fix device tree compatible nodeMarcel Ziswiler
Working on sound support I noticed the Apalis T30 Evaluation board device tree missing the more generic Apalis T30 compatible string. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2014-07-30ARM: tegra: paz00: Fix some indentation inconsistenciesThierry Reding
Indentation of the clock property used a hodgepodge of tabs and spaces. Make them more consistent (tabs for indentation followed by spaces for alignment). Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2014-07-30MIPS: Loongson: Rename CONFIG_LEMOTE_MACH3A to CONFIG_LOONGSON_MACH3XHuacai Chen
Since this CONFIG option will be used for both Loongson-3A/3B machines, and not all Loongson-3 machines are produced by Lemote, we rename CONFIG_LEMOTE_MACH3A to CONFIG_LOONGSON_MACH3X. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7190/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-30ARM: nomadik: fix up double inversion in DTLinus Walleij
The GPIO pin connected to card detect was inverted twice: once by the argument to the GPIO line itself where it was magically marked as active low by the flag GPIO_ACTIVE_LOW (0x01) in the third cell, and also marked active low AGAIN by explicitly stating "cd-inverted" (a deprecated method). After commit 78f87df2b4f8760954d7d80603d0cfcbd4759683 "mmc: mmci: Use the common mmc DT parser" this results in the line being inverted twice so it was effectively uninverted, while the old code would not have this effect, instead disregarding the flag on the GPIO line altogether, which is a bug. I admit the semantics may be unclear but inverting twice is as good a definition as any on how this should work. So fix up the buggy device tree. Use proper #includes so the DTS is clear and readable. Cc: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2014-07-30MIPS: Loongson-3: Enable the COP2 usageHuacai Chen
Loongson-3 has some specific instructions (MMI/SIMD) in coprocessor 2. COP2 isn't independent because it share COP1 (FPU)'s registers. This patch enable the COP2 usage so user-space programs can use the MMI/SIMD instructions. When COP2 exception happens, we enable both COP1 (FPU) and COP2, only in this way the fp context can be saved and restored correctly. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7189/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-30MIPS: Add Loongson-3B supportHuacai Chen
Loongson-3B is a 8-cores processor. In general it looks like there are two Loongson-3A integrated in one chip: 8 cores are separated into two groups (two NUMA node), each node has its own local memory. Of course there are some differences between one Loongson-3B and two Loongson-3A. E.g., the base addresses of IPI registers of each node are not the same; Loongson-3A use ChipConfig register to enable/disable clock, but Loongson-3B use FreqControl register instead. There are two revision of Loongson-3B, the first revision is called as Loongson-3B1000, whose frequency is 1GHz and has a PRid 0x6306, the second revision is called as Loongson-3B1500, whose frequency is 1.5GHz and has a PRid 0x6307. Both revisions has a bug that clock cannot be disabled at runtime, but this will be fixed in future. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7188/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-30MIPS: Add numa api supportHuacai Chen
Enable sys_mbind()/sys_get_mempolicy()/sys_set_mempolicy() for O32, N32, and N64 ABIs. By the way, O32/N32 should use the compat version of sys_migrate_pages()/sys_move_pages(), so fix that. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7186/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-30MIPS: Add NUMA support for Loongson-3Huacai Chen
Multiple Loongson-3A chips can be interconnected with HT0-bus. This is a CC-NUMA system that every chip (node) has its own local memory and cache coherency is maintained by hardware. The 64-bit physical memory address format is as follows: 0x-0000-YZZZ-ZZZZ-ZZZZ The high 16 bits should be 0, which means the real physical address supported by Loongson-3 is 48-bit. The "Y" bits is the base address of each node, which can be also considered as the node-id. The "Z" bits is the address offset within a node, which means every node has a 44 bits address space. Macros XPHYSADDR and MAX_PHYSMEM_BITS are modified unconditionally, because many other MIPS CPUs have also extended their address spaces. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7187/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-30MIPS: Loongson: Modify ChipConfig register definitionHuacai Chen
This patch is prepared for Multi-chip interconnection. Since each chip has a ChipConfig register, LOONGSON_CHIPCFG should be an array. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7185/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-30MIPS: Support CPU topology files in sysfsHuacai Chen
This patch is prepared for Loongson's NUMA support, it offer meaningful sysfs files such as physical_package_id, core_id, core_siblings and thread_siblings in /sys/devices/system/cpu/cpu?/topology. Signed-off-by: Huacai Chen <chenhc@lemote.com> Reviewed-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7184/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-30MIPS: Support hard limit of cpu count (nr_cpu_ids)Huacai Chen
On MIPS currently, only the soft limit of cpu count (maxcpus) has its effect, this patch enable the hard limit (nr_cpus) as well. Processor cores which greater than maxcpus and less than nr_cpus can be taken up via cpu hotplug. The code is borrowed from X86. Signed-off-by: Huacai Chen <chenhc@lemote.com> Reviewed-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7183/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-30Merge tag 'renesas-clock3-for-v3.17' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt Merge "Third Round of Renesas ARM Based SoC Clock Updates for v3.17" from Simon Horman: Third Round of Renesas ARM Based SoC Clock Updates for v3.17 * Add legacy clocks for SCI for SoCs that do not yet have CCF support. This is to allow timer devices to be enabled using DT and will be removed after CCF support is added for each SoC. This is in keeping with the approach taken for enabling SCI (serial) devices using DT on these SoCs. * tag 'renesas-clock3-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: sh73a0: add CMT1 clock support for DT ARM: shmobile: r8a7740: add CMT1 clock support for DT ARM: shmobile: r8a73a4: add CMT1 clock support for DT ARM: shmobile: r8a7740: add TMU clock support for DT ARM: shmobile: r8a7778: add TMU clock support for DT Signed-off-by: Olof Johansson <olof@lixom.net>
2014-07-30MIPS: Remove BUG_ON(!is_fpu_owner()) in do_ade()Huacai Chen
In do_ade(), is_fpu_owner() isn't preempt-safe. For example, when an unaligned ldc1 is executed, do_cpu() is called and then FPU will be enabled (and TIF_USEDFPU will be set for the current process). Then, do_ade() is called because the access is unaligned. If the current process is preempted at this time, TIF_USEDFPU will be cleard. So when the process is scheduled again, BUG_ON(!is_fpu_owner()) is triggered. This small program can trigger this BUG in a preemptible kernel: int main (int argc, char *argv[]) { double u64[2]; while (1) { asm volatile ( ".set push \n\t" ".set noreorder \n\t" "ldc1 $f3, 4(%0) \n\t" ".set pop \n\t" ::"r"(u64): ); } return 0; } V2: Remove the BUG_ON() unconditionally due to Paul's suggestion. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Jie Chen <chenj@lemote.com> Signed-off-by: Rui Wang <wangr@lemote.com> Cc: <stable@vger.kernel.org> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: stable@vger.kernel.org Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-30MIPS: Remove incorrect NULL check in local_flush_tlb_page()Emil Goode
We check that the struct vm_area_struct pointer vma is NULL and then dereference it a few lines below. The intent was to make sure vma is not NULL but this is not necessary since the bug pre-dates GIT history and seem to never have caused a problem. The tlb-4k and tlb-8k versions of local_flush_tlb_page() don't bother checking if vma is NULL, also vma is dereferenced before being passed to local_flush_tlb_page(), thus it is safe to remove this NULL check. Signed-off-by: Emil Goode <emilgoode@gmail.com> Reviewed-by: Jonas Gorski <jogo@openwrt.org> Acked-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: kernel-janitors@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7264/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>