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2014-11-19ARM: OMAP2+: hwmod: add parent_hwmod supportTomi Valkeinen
Add parent_hwmod pointer to omap_hwmod. This can be set to point to a "parent" hwmod that needs to be enabled for the "child" hwmod to work. This is used at hwmod setup time: when doing the initial setup and reset, first enable the parent hwmod, and after setup and reset is done, restore the parent hwmod to postsetup_state. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Reviewed-by: Archit Taneja <archit.taneja@gmail.com> [paul@pwsan.com: add kerneldoc documentation for parent_hwmod; note that it is a temporary workaround] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2014-11-19Merge tag 'renesas-dt-cleanups2-for-v3.19' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt Pull "Second Round of Renesas ARM Based SoC DT Cleanups for v3.19" from Simon Horman: * Drop console= bootargs parameter on alt * Correct scifb* naming on r8a73a4 * Drop 0x unit-address prefixes * Remove unnecessary MMC options * tag 'renesas-dt-cleanups2-for-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: alt dts: Drop console= bootargs parameter ARM: shmobile: r8a73a4: fix scifb* naming ARM: shmobile: kzm9g-reference dts: Drop bogus 0x unit-address prefix ARM: shmobile: r8a7791 dtsi: Drop bogus 0x unit-address prefix ARM: shmobile: r8a7790 dtsi: Drop bogus 0x unit-address prefix ARM: shmobile: r8a7790 dtsi: Remove unnecessary MMC options ARM: shmobile: r8a7779 dtsi: Remove unnecessary MMC options ARM: shmobile: r8a7778 dtsi: Remove unnecessary MMC options Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-11-19Merge tag 'renesas-dt-for-v3.19' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt Pull "Renesas ARM Based SoC DT Updates for v3.19" from Simon Horman: * Add Add SoC-specific SATA compatible property to r8a7779 * Enable DMA for MMCIF on r8a7791 and r8a7790 * Enable USB-PHY, HS-USB and USB3.0 on r8a7791 and r8a7790 * Enable TMU timer via DT on r8a7778 * Enable CMT timer via DT on r8a73a4 * Add MMP and {SR}GX clocks to r8a7791 and r8a7790 * Correct scifa2 clock index on r8a7740 * Add missing INTCA for irqpin on r8a7740 * tag 'renesas-dt-for-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (34 commits) ARM: shmobile: r8a7779 dtsi: Add SoC-specific SATA compatible property ARM: shmobile: r8a7791: Reference DMA channels in MMCIF DT node ARM: shmobile: r8a7790: Reference DMA channels in MMCIF DT nodes ARM: shmobile: r8a7791: Add MMCIF0 DT node ARM: shmobile: r8a7790: Rename mmcif node to mmc ARM: shmobile: r8a7778: Add SoC-specific TMU compatible property ARM: shmobile: r8a73a4: Add SoC-specific CMT compatible property ARM: shmobile: henninger: enable HS-USB ARM: shmobile: koelsch: enable HS-USB ARM: shmobile: r8a7791: add HS-USB device node ARM: shmobile: lager: enable HS-USB ARM: shmobile: r8a7790: add HS-USB device node ARM: shmobile: r8a7791: add USB3.0 device node ARM: shmobile: lager: enable USB3.0 ARM: shmobile: r8a7790: add USB3.0 device node ARM: shmobile: r8a7794: Add arch_timer to device tree ARM: shmobile: bockw-reference: Initialise TMU device using DT ARM: shmobile: r8a7778: Add TMU nodes ARM: shmobile: armadillo800eva dts: Enable TMU0 ARM: shmobile: r8a7740 dtsi: Add TMU0 and TMU1 device nodes ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-11-19Merge branch 'renesas/dt-du' into next/dtArnd Bergmann
This is a base for the DT updates, merged through the arm-soc cleanup branch. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-11-19Merge tag 'renesas-dt-du-for-v3.19' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/cleanup Pull "Renesas ARM Based SoC DT DU Updates for v3.19" from Simon Horman: * Enable DU using DT on marzen/r8a7779, lager/r8a7790 and koelsch/r8a7791 * tag 'renesas-dt-du-for-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: koelsch: Enable DU device in DT ARM: shmobile: koelsch-reference: Remove DU platform device ARM: shmobile: lager: Enable DU device in DT ARM: shmobile: lager-reference: Remove DU platform device ARM: shmobile: marzen: Enable DU device in DT ARM: shmobile: dts: Add common file for AA104XD12 panel ARM: shmobile: r8a7791: Add DU node to device tree ARM: shmobile: r8a7790: Add DU node to device tree ARM: shmobile: r8a7779: Add DU node to device tree Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-11-19Merge tag 'renesas-boards-cleanups2-for-v3.19' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/cleanup Pull "Second Round of Renesas ARM Based SoC Boards Cleanups for v3.19" form Simon Horman: * marzen-reference: Don't include legacy clock.h * tag 'renesas-boards-cleanups2-for-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: marzen-reference: Don't include legacy clock.h Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-11-19separate kernel- and userland-side msghdrAl Viro
Kernel-side struct msghdr is (currently) using the same layout as userland one, but it's not a one-to-one copy - even without considering 32bit compat issues, we have msg_iov, msg_name and msg_control copied to kernel[1]. It's fairly localized, so we get away with a few functions where that knowledge is needed (and we could shrink that set even more). Pretty much everything deals with the kernel-side variant and the few places that want userland one just use a bunch of force-casts to paper over the differences. The thing is, kernel-side definition of struct msghdr is *not* exposed in include/uapi - libc doesn't see it, etc. So we can add struct user_msghdr, with proper annotations and let the few places that ever deal with those beasts use it for userland pointers. Saner typechecking aside, that will allow to change the layout of kernel-side msghdr - e.g. replace msg_iov/msg_iovlen there with struct iov_iter, getting rid of the need to modify the iovec as we copy data to/from it, etc. We could introduce kernel_msghdr instead, but that would create much more noise - the absolute majority of the instances would need to have the type switched to kernel_msghdr and definition of struct msghdr in include/linux/socket.h is not going to be seen by userland anyway. This commit just introduces user_msghdr and switches the few places that are dealing with userland-side msghdr to it. [1] actually, it's even trickier than that - we copy msg_control for sendmsg, but keep the userland address on recvmsg. Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2014-11-19Merge tag 'renesas-soc3-for-v3.19' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc Pull "Third Round of Renesas ARM Based Soc Updates for v3.19" from Simon Horman: * Always build rcar setup for armv7 - Fixes allmodconfig build fauilre caused by "ARM: shmobile: always build rcar setup for armv7" * Add restart callback to sh73a0 * tag 'renesas-soc3-for-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: always build rcar setup for armv7 ARM: shmobile: sh73a0: Add restart callback Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-11-19Merge tag 'renesas-soc2-for-v3.19' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc Pull "Second Round of Renesas ARM Based SoC Soc Updates for v3.19" from Simon Horman: * Enable PCI domains for R-Car Gen2 devices * Make APMU resource code SoC-specific * tag 'renesas-soc2-for-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: Enable PCI domains for R-Car Gen2 devices ARM: shmobile: r8a7791: Correct number of CPU cores ARM: shmobile: Separate APMU resource data into CPU dependant part Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-11-19Merge tag 'renesas-soc-for-v3.19' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc Pull "Renesas ARM Based SoC Soc Updates for v3.19" from Simon Horman: * Select CONFIG_ZONE_DMA when CONFIG_ARM_LPAE is enabled * Add CA7 arch_timer initialization for r8a7794 * Handle CA7 arch timer delay * Add shmobile_init_late() to sh7372 - This is consistent with other shmobile SoCs * tag 'renesas-soc-for-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: Select CONFIG_ZONE_DMA when CONFIG_ARM_LPAE is enabled ARM: shmobile: rcar-gen2: Add CA7 arch_timer initialization for r8a7794 ARM: shmobile: sh7372: Add shmobile_init_late() ARM: shmobile: Handle CA7 arch timer delay Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-11-19Merge tag 'renesas-runtime-pm-for-v3.19' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc Merge "Renesas ARM Based SoC Runtime PM Updates for v3.19" * 8a7740/armadillo800eva legacy PM domain support * tag 'renesas-runtime-pm-for-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: r8a7740: Add A3SM pm domain support ARM: shmobile: r8a7740: Add A4SU pm domain support ARM: shmobile: r8a7740/armadillo legacy: Add A4R pm domain support ARM: shmobile: r8a7740: Add D4 pm domain support ARM: shmobile: r8a7740/armadillo legacy: Add A4MP pm domain support ARM: shmobile: r8a7740: Add A3SG pm domain support ARM: shmobile: r8a7740: Add A3RV pm domain support ARM: shmobile: armadillo800eva legacy: Add missing A4S pm domain devices ARM: shmobile: armadillo800eva legacy: Add missing A3SP pm domain devices ARM: shmobile: r8a7740: Add missing A4S pm domain devices ARM: shmobile: r8a7740: Add missing A3SP pm domain devices Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-11-19x86/kvm/tracing: Use helper function trace_seq_buffer_ptr()Steven Rostedt (Red Hat)
To allow for the restructiong of the trace_seq code, we need users of it to use the helper functions instead of accessing the internals of the trace_seq structure itself. Link: http://lkml.kernel.org/r/20141104160221.585025609@goodmis.org Tested-by: Jiri Kosina <jkosina@suse.cz> Acked-by: Jiri Kosina <jkosina@suse.cz> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Acked-by: Mark Rustad <mark.d.rustad@intel.com> Reviewed-by: Petr Mladek <pmladek@suse.cz> Cc: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
2014-11-19ftrace/x86/extable: Add is_ftrace_trampoline() functionSteven Rostedt (Red Hat)
Stack traces that happen from function tracing check if the address on the stack is a __kernel_text_address(). That is, is the address kernel code. This calls core_kernel_text() which returns true if the address is part of the builtin kernel code. It also calls is_module_text_address() which returns true if the address belongs to module code. But what is missing is ftrace dynamically allocated trampolines. These trampolines are allocated for individual ftrace_ops that call the ftrace_ops callback functions directly. But if they do a stack trace, the code checking the stack wont detect them as they are neither core kernel code nor module address space. Adding another field to ftrace_ops that also stores the size of the trampoline assigned to it we can create a new function called is_ftrace_trampoline() that returns true if the address is a dynamically allocate ftrace trampoline. Note, it ignores trampolines that are not dynamically allocated as they will return true with the core_kernel_text() function. Link: http://lkml.kernel.org/r/20141119034829.497125839@goodmis.org Cc: Ingo Molnar <mingo@redhat.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
2014-11-19ftrace/x86: Add frames pointers to trampoline as necessarySteven Rostedt (Red Hat)
When CONFIG_FRAME_POINTERS are enabled, it is required that the ftrace_caller and ftrace_regs_caller trampolines set up frame pointers otherwise a stack trace from a function call wont print the functions that called the trampoline. This is due to a check in __save_stack_address(): #ifdef CONFIG_FRAME_POINTER if (!reliable) return; #endif The "reliable" variable is only set if the function address is equal to contents of the address before the address the frame pointer register points to. If the frame pointer is not set up for the ftrace caller then this will fail the reliable test. It will miss the function that called the trampoline. Worse yet, if fentry is used (gcc 4.6 and beyond), it will also miss the parent, as the fentry is called before the stack frame is set up. That means the bp frame pointer points to the stack of just before the parent function was called. Link: http://lkml.kernel.org/r/20141119034829.355440340@goodmis.org Cc: Ingo Molnar <mingo@redhat.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: x86@kernel.org Cc: stable@vger.kernel.org # 3.7+ Acked-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
2014-11-19x86, mce: Support memory error recovery for both UCNA and Deferred error in ↵Chen Yucong
machine_check_poll Uncorrected no action required (UCNA) - is a uncorrected recoverable machine check error that is not signaled via a machine check exception and, instead, is reported to system software as a corrected machine check error. UCNA errors indicate that some data in the system is corrupted, but the data has not been consumed and the processor state is valid and you may continue execution on this processor. UCNA errors require no action from system software to continue execution. Note that UCNA errors are supported by the processor only when IA32_MCG_CAP[24] (MCG_SER_P) is set. -- Intel SDM Volume 3B Deferred errors are errors that cannot be corrected by hardware, but do not cause an immediate interruption in program flow, loss of data integrity, or corruption of processor state. These errors indicate that data has been corrupted but not consumed. Hardware writes information to the status and address registers in the corresponding bank that identifies the source of the error if deferred errors are enabled for logging. Deferred errors are not reported via machine check exceptions; they can be seen by polling the MCi_STATUS registers. -- AMD64 APM Volume 2 Above two items, both UCNA and Deferred errors belong to detected errors, but they can't be corrected by hardware, and this is very similar to Software Recoverable Action Optional (SRAO) errors. Therefore, we can take some actions that have been used for handling SRAO errors to handle UCNA and Deferred errors. Acked-by: Borislav Petkov <bp@suse.de> Signed-off-by: Chen Yucong <slaoub@gmail.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
2014-11-19x86, mce, severity: Extend the the mce_severity mechanism to handle ↵Chen Yucong
UCNA/DEFERRED error Until now, the mce_severity mechanism can only identify the severity of UCNA error as MCE_KEEP_SEVERITY. Meanwhile, it is not able to filter out DEFERRED error for AMD platform. This patch extends the mce_severity mechanism for handling UCNA/DEFERRED error. In order to do this, the patch introduces a new severity level - MCE_UCNA/DEFERRED_SEVERITY. In addition, mce_severity is specific to machine check exception, and it will check MCIP/EIPV/RIPV bits. In order to use mce_severity mechanism in non-exception context, the patch also introduces a new argument (is_excp) for mce_severity. `is_excp' is used to explicitly specify the calling context of mce_severity. Reviewed-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> Signed-off-by: Chen Yucong <slaoub@gmail.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
2014-11-19assorted conversions to %p[dD]Al Viro
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2014-11-19KVM: x86: Remove FIXMEs in emulate.cNicholas Krause
Remove FIXME comments about needing fault addresses to be returned. These are propaagated from walk_addr_generic to gva_to_gpa and from there to ops->read_std and ops->write_std. Signed-off-by: Nicholas Krause <xerofoify@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-11-19KVM: emulator: remove duplicated limit checkPaolo Bonzini
The check on the higher limit of the segment, and the check on the maximum accessible size, is the same for both expand-up and expand-down segments. Only the computation of "lim" varies. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-11-19ARM: multi_v7_defconfig: fix failure setting CPU voltage by enabling ↵Tyler Baker
dependent I2C controller This patch fixes a long standing issue introduced during the 3.16 merge window. Shortly after the merge, exynos5250-based arndale boards began to produce the following errors: kern.err kernel: exynos-cpufreq exynos-cpufreq: failed to set cpu voltage kern.err kernel: cpufreq: __target_index: Failed to change cpu frequency: -22 Further analysis revealed that the S5M8767 voltage regulator used on the exynos5250-based arndale board utilizes the S3C2410 I2C controller. If the S3C2410 I2C controller driver is not enabled, the S5M8767 voltage regulator fails to probe. Therefore a dependency exists between these two drivers. In the exynos_defconfig both CONFIG_REGULATOR_S5M8767 and CONFIG_I2C_S3C2410 options are enabled, and no errors are produced. However, in the multi_v7_defconfig only the CONFIG_REGULATOR_S5M8767 option is enabled and the errors are present. So let's enable the CONFIG_I2C_S3C2410 option in the multi_v7_defconfig to allow the S5M8767 voltage regulator to probe. Signed-off-by: Tyler Baker <tyler.baker@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Kevin Hilman <khilman@linaro.org>
2014-11-19KVM: emulator: remove code duplication in register_address{,_increment}Paolo Bonzini
register_address has been a duplicate of address_mask ever since the ancestor of __linearize was born in 90de84f50b42 (KVM: x86 emulator: preserve an operand's segment identity, 2010-11-17). However, we can put it to a better use by including the call to reg_read in register_address. Similarly, the call to reg_rmw can be moved to register_address_increment. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-11-19MIPS: jump_label.c: Handle the microMIPS J instruction encodingMaciej W. Rozycki
Implement the microMIPS encoding of the J instruction for the purpose of the static keys feature, fixing a crash early on in bootstrap as the kernel is unhappy seeing the ISA bit set in jump table entries. Make sure the ISA bit correctly reflects the instruction encoding chosen for the kernel, 0 for the standard MIPS and 1 for the microMIPS encoding. Also make sure the instruction to patch is a 32-bit NOP in the microMIPS mode as by default the 16-bit short encoding is assumed Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8516/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-19MIPS: jump_label.c: Correct the span of the J instructionMaciej W. Rozycki
Correct the check for the span of the 256MB segment addressable by the J instruction according to this instruction's semantics. The calculation of the jump target is applied to the address of the delay-slot instruction that immediately follows. Adjust the check accordingly by adding 4 to `e->code' that holds the address of the J instruction itself. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8515/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-19MIPS: Zero variable read by get_user / __get_user in case of an error.Ralf Baechle
This wasn't happening in all cases. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-19MIPS: lib: memcpy: Restore NOP on delay slot before returning to callerMarkos Chandras
Commit cf62a8b8134dd3 ("MIPS: lib: memcpy: Use macro to build the copy_user code") switched to a macro in order to build the memcpy symbols in preparation for the EVA support. However, this commit also removed the NOP instruction after the 'jr ra' when returning back to the caller. This had no visible side-effects since the next instruction was a load to the t0 register which was already in the clobbered list, but it may have undesired effects in the future if some other code is introduced in between the .Ldone and the .Ll_exc_copy labels. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: <stable@vger.kernel.org> # v3.15+ Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8512/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-19MIPS: tlb-r4k: Add missing HTW stop/start sequencesMarkos Chandras
HTW needs to stop and start again whenever the EntryHI register changes otherwise an inflight HTW operation might use the new EntryHI register for updating an old entry and that could lead to crashes or even a machine check exception. We fix this by ensuring the HTW has stop whenever the EntryHI register is about to change Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: <stable@vger.kernel.org> # v3.17+ Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8511/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-19MIPS: asm: uaccess: Add v1 register to clobber list on EVAMarkos Chandras
When EVA is turned on and prefetching is being used in memcpy.S, the v1 register is being used as a helper register to the PREFE instruction. However, v1 ($3) was not in the clobber list, which means that the compiler did not preserve it across function calls, and that could corrupt the value of the register leading to all sorts of userland crashes. We fix this problem by using the DADDI_SCRATCH macro to define the clobbered register when CONFIG_EVA && CONFIG_CPU_HAS_PREFETCH are enabled. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: <stable@vger.kernel.org> # v3.15+ Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8510/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-19MIPS: oprofile: Fix backtrace on 64-bit kernelAaro Koskinen
Fix incorrect cast that always results in wrong address for the new frame on 64-bit kernels. Signed-off-by: Aaro Koskinen <aaro.koskinen@nsn.com> Cc: stable@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8110/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-19MIPS: Loongson: Set Loongson-3's ISA level to MIPS64R1Huacai Chen
In CPU manual Loongson-3 is MIPS64R2 compatible, but during tests we found that its EI/DI instructions have problems. So we just set the ISA level to MIPS64R1. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/8320/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-19MIPS: Loongson: Fix the write-combine CCA value settingHuacai Chen
All Loongson-2/3 processors support _CACHE_UNCACHED_ACCELERATED, not only Loongson-3A. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/8319/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-19MIPS: IP27: Fix __node_distances undefined errorJames Cowgill
export the __node_distances symbol in the ip27 memory code to fix the build error: Building modules, stage 2. MODPOST 311 modules ERROR: "__node_distances" [drivers/block/nvme.ko] undefined! scripts/Makefile.modpost:90: recipe for target '__modpost' failed when building the kernel with: CONFIG_SGI_IP27=y CONFIG_BLK_DEV_NVME=m Signed-off-by: James Cowgill <James.Cowgill@imgtec.com> Cc: <stable@vger.kernel.org> # v3.15+ Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-19MIPS: Loongson3: Fix __node_distances undefined errorJames Cowgill
export the __node_distances symbol in the loongson3 numa code to fix the build error: Building modules, stage 2. MODPOST 221 modules ERROR: "__node_distances" [drivers/block/nvme.ko] undefined! scripts/Makefile.modpost:90: recipe for target '__modpost' failed when building the kernel with: CONFIG_CPU_LOONGSON3=y CONFIG_NUMA=y CONFIG_BLK_DEV_NVME=m Signed-off-by: James Cowgill <James.Cowgill@imgtec.com> Cc: <stable@vger.kernel.org> # v3.17+ Reviewed-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Huacai Chen <chenhc@lemote.com> Cc: linux-mips@linux-mips.org Cc: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Patchwork: https://patchwork.linux-mips.org/patch/8444/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-19KVM: x86: Move __linearize masking of la into switchNadav Amit
In __linearize there is check of the condition whether to check if masking of the linear address is needed. It occurs immediately after switch that evaluates the same condition. Merge them. Signed-off-by: Nadav Amit <namit@cs.technion.ac.il> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-11-19KVM: x86: Non-canonical access using SS should cause #SSNadav Amit
When SS is used using a non-canonical address, an #SS exception is generated on real hardware. KVM emulator causes a #GP instead. Fix it to behave as real x86 CPU. Signed-off-by: Nadav Amit <namit@cs.technion.ac.il> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-11-19KVM: x86: Perform limit checks when assigning EIPNadav Amit
If branch (e.g., jmp, ret) causes limit violations, since the target IP > limit, the #GP exception occurs before the branch. In other words, the RIP pushed on the stack should be that of the branch and not that of the target. To do so, we can call __linearize, with new EIP, which also saves us the code which performs the canonical address checks. On the case of assigning an EIP >= 2^32 (when switching cs.l), we also safe, as __linearize will check the new EIP does not exceed the limit and would trigger #GP(0) otherwise. Signed-off-by: Nadav Amit <namit@cs.technion.ac.il> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-11-19KVM: x86: Emulator performs privilege checks on __linearizeNadav Amit
When segment is accessed, real hardware does not perform any privilege level checks. In contrast, KVM emulator does. This causes some discrepencies from real hardware. For instance, reading from readable code segment may fail due to incorrect segment checks. In addition, it introduces unnecassary overhead. To reference Intel SDM 5.5 ("Privilege Levels"): "Privilege levels are checked when the segment selector of a segment descriptor is loaded into a segment register." The SDM never mentions privilege level checks during memory access, except for loading far pointers in section 5.10 ("Pointer Validation"). Those are actually segment selector loads and are emulated in the similarily (i.e., regardless to __linearize checks). This behavior was also checked using sysexit. A data-segment whose DPL=0 was loaded, and after sysexit (CPL=3) it is still accessible. Therefore, all the privilege level checks in __linearize are removed. Signed-off-by: Nadav Amit <namit@cs.technion.ac.il> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-11-19KVM: x86: Stack size is overridden by __linearizeNadav Amit
When performing segmented-read/write in the emulator for stack operations, it ignores the stack size, and uses the ad_bytes as indication for the pointer size. As a result, a wrong address may be accessed. To fix this behavior, we can remove the masking of address in __linearize and perform it beforehand. It is already done for the operands (so currently it is inefficiently done twice). It is missing in two cases: 1. When using rip_relative 2. On fetch_bit_operand that changes the address. This patch masks the address on these two occassions, and removes the masking from __linearize. Note that it does not mask EIP during fetch. In protected/legacy mode code fetch when RIP >= 2^32 should result in #GP and not wrap-around. Since we make limit checks within __linearize, this is the expected behavior. Partial revert of commit 518547b32ab4 (KVM: x86: Emulator does not calculate address correctly, 2014-09-30). Signed-off-by: Nadav Amit <namit@cs.technion.ac.il> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-11-19KVM: x86: Revert NoBigReal patch in the emulatorNadav Amit
Commit 10e38fc7cab6 ("KVM: x86: Emulator flag for instruction that only support 16-bit addresses in real mode") introduced NoBigReal for instructions such as MONITOR. Apparetnly, the Intel SDM description that led to this patch is misleading. Since no instruction is using NoBigReal, it is safe to remove it, we fully understand what the SDM means. Signed-off-by: Nadav Amit <namit@cs.technion.ac.il> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-11-19Merge tag 'tegra-for-3.18-fixes-for-rc5' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into fixes Pull "ARM: tegra: Device tree fixes for v3.18-rc5" from Thierry Reding: This contains the serial port numbering fixes that are required for the serial port numbering to stay the same with or without the serial core making use of the aliases defined in DT. eMMC is also fixed for TN7 and Roth boards which were using the wrong regulators. * tag 'tegra-for-3.18-fixes-for-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: ARM: tegra: roth: Fix SD card VDD_IO regulator ARM: tegra: Remove eMMC vmmc property for roth/tn7 ARM: dts: tegra: move serial aliases to per-board ARM: tegra: Add serial port labels to Tegra124 DT Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-11-19Merge tag 'renesas-clock-fixes-for-v3.18' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into fixes Pull "Renesas ARM Based SoC Clock Fixes for v3.18" from Simon Horman: * Correct IIC0 parent clock for r8a7740 * Add missing INTCA clock for irqpin module for r8a7740 * Correct SD3CKCR address on r8a7790 * tag 'renesas-clock-fixes-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: r8a7740 legacy: Correct IIC0 parent clock ARM: shmobile: r8a7740 legacy: Add missing INTCA clock for irqpin module ARM: shmobile: r8a7790: Fix SD3CKCR address Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-11-19Merge tag 'renesas-dt-fixes-for-v3.18' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into fixes Pull "Renesas ARM Based SoC DT Fixes for v3.18" from Simon Horman: * Correct IIC0 parent clock on r8a7740 * Correct SD3CKCR address to device tree on r8a7790 * tag 'renesas-dt-fixes-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: r8a7740 dtsi: Correct IIC0 parent clock ARM: shmobile: r8a7790: Fix SD3CKCR address to device tree Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-11-19Merge tag 'renesas-soc-fixes-for-v3.18' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into fixes Pull "Renesas ARM Based SoC Fixes for v3.18" from Simon Horman: * Set i2c clks_per_count to 2 on kzm9g * tag 'renesas-soc-fixes-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: kzm9g legacy: Set i2c clks_per_count to 2 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-11-19ARM: at91/dt: at91sam9g45: add ISI nodeBoris Brezillon
Add ISI (Image Sensor Interface) DT node + pinctrl definition. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2014-11-19ARM: at91/dt: enable the RTT block on the at91sam9m10g45ek boardBoris Brezillon
Enable the RTT and GPBR devices and specify the general purpose register used to store the current time. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2014-11-19ARM: at91/dt: enable the RTT block on the sam9g20ek boardBoris Brezillon
Enable the RTT and GPBR devices and specify the general purpose register used to store the current time. Enable wakeup on RTT event on the shutdown controller device. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2014-11-19ARM: at91/dt: add GPBR nodesBoris Brezillon
Add GPBR (General Purpose Block Backup Registers) nodes. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2014-11-19ARM: at91/dt: add RTT nodes to at91 dtsisBoris Brezillon
at91sam926x, at91sam9g45 and at91sam9rl SoCs all have at least one RTT block. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2014-11-19ARM: at91/dt: at91sam9rl: add rtcAlexandre Belloni
Add rtc support to the at91sam9rl dtsi file. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2014-11-19ARM: at91: fix GPLv2 wordingNicolas Ferre
During the submission of these new sama5d4 files, the GPL notice mentioned the device tree as a library, which is not really accurate. Fix all these library mentions to reflect the fact that it's actually just a file. Reported-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2014-11-19Merge tag 'sunxi-fixes-for-3.18' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into fixes Merge "Allwinner fixes for 3.18" from Maxime Ripard: A fix for the A31 dma controller that requires the AHB clock to be parented to PLL6 in order to operate. * tag 'sunxi-fixes-for-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: ARM: dts: sun6i: Re-parent ahb1_mux to pll6 as required by dma controller Signed-off-by: Arnd Bergmann <arnd@arndb.de>