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Moving IBS macros from oprofile to <asm/perf_event.h> to make it
available to perf. No additional changes.
Signed-off-by: Robert Richter <robert.richter@amd.com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/1316597423-25723-2-git-send-email-robert.richter@amd.com
Signed-off-by: Ingo Molnar <mingo@elte.hu>
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Now that the NMI handler are broken into lists, increment the appropriate
stats for each list. This allows us to see what is going on when they
get printed out in the next patch.
Signed-off-by: Don Zickus <dzickus@redhat.com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/1317409584-23662-6-git-send-email-dzickus@redhat.com
Signed-off-by: Ingo Molnar <mingo@elte.hu>
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Previous patches allow the NMI subsystem to process multipe NMI events
in one NMI. As previously discussed this can cause issues when an event
triggered another NMI but is processed in the current NMI. This causes the
next NMI to go unprocessed and become an 'unknown' NMI.
To handle this, we first have to flag whether or not the NMI handler handled
more than one event or not. If it did, then there exists a chance that
the next NMI might be already processed. Once the NMI is flagged as a
candidate to be swallowed, we next look for a back-to-back NMI condition.
This is determined by looking at the %rip from pt_regs. If it is the same
as the previous NMI, it is assumed the cpu did not have a chance to jump
back into a non-NMI context and execute code and instead handled another NMI.
If both of those conditions are true then we will swallow any unknown NMI.
There still exists a chance that we accidentally swallow a real unknown NMI,
but for now things seem better.
An optimization has also been added to the nmi notifier rountine. Because x86
can latch up to one NMI while currently processing an NMI, we don't have to
worry about executing _all_ the handlers in a standalone NMI. The idea is
if multiple NMIs come in, the second NMI will represent them. For those
back-to-back NMI cases, we have the potentail to drop NMIs. Therefore only
execute all the handlers in the second half of a detected back-to-back NMI.
Signed-off-by: Don Zickus <dzickus@redhat.com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/1317409584-23662-5-git-send-email-dzickus@redhat.com
Signed-off-by: Ingo Molnar <mingo@elte.hu>
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Just convert all the files that have an nmi handler to the new routines.
Most of it is straight forward conversion. A couple of places needed some
tweaking like kgdb which separates the debug notifier from the nmi handler
and mce removes a call to notify_die.
[Thanks to Ying for finding out the history behind that mce call
https://lkml.org/lkml/2010/5/27/114
And Boris responding that he would like to remove that call because of it
https://lkml.org/lkml/2011/9/21/163]
The things that get converted are the registeration/unregistration routines
and the nmi handler itself has its args changed along with code removal
to check which list it is on (most are on one NMI list except for kgdb
which has both an NMI routine and an NMI Unknown routine).
Signed-off-by: Don Zickus <dzickus@redhat.com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Acked-by: Corey Minyard <minyard@acm.org>
Cc: Jason Wessel <jason.wessel@windriver.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Robert Richter <robert.richter@amd.com>
Cc: Huang Ying <ying.huang@intel.com>
Cc: Corey Minyard <minyard@acm.org>
Cc: Jack Steiner <steiner@sgi.com>
Link: http://lkml.kernel.org/r/1317409584-23662-4-git-send-email-dzickus@redhat.com
Signed-off-by: Ingo Molnar <mingo@elte.hu>
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The NMI handlers used to rely on the notifier infrastructure. This worked
great until we wanted to support handling multiple events better.
One of the key ideas to the nmi handling is to process _all_ the handlers for
each NMI. The reason behind this switch is because NMIs are edge triggered.
If enough NMIs are triggered, then they could be lost because the cpu can
only latch at most one NMI (besides the one currently being processed).
In order to deal with this we have decided to process all the NMI handlers
for each NMI. This allows the handlers to determine if they recieved an
event or not (the ones that can not determine this will be left to fend
for themselves on the unknown NMI list).
As a result of this change it is now possible to have an extra NMI that
was destined to be received for an already processed event. Because the
event was processed in the previous NMI, this NMI gets dropped and becomes
an 'unknown' NMI. This of course will cause printks that scare people.
However, we prefer to have extra NMIs as opposed to losing NMIs and as such
are have developed a basic mechanism to catch most of them. That will be
a later patch.
To accomplish this idea, I unhooked the nmi handlers from the notifier
routines and created a new mechanism loosely based on doIRQ. The reason
for this is the notifier routines have a couple of shortcomings. One we
could't guarantee all future NMI handlers used NOTIFY_OK instead of
NOTIFY_STOP. Second, we couldn't keep track of the number of events being
handled in each routine (most only handle one, perf can handle more than one).
Third, I wanted to eventually display which nmi handlers are registered in
the system in /proc/interrupts to help see who is generating NMIs.
The patch below just implements the new infrastructure but doesn't wire it up
yet (that is the next patch). Its design is based on doIRQ structs and the
atomic notifier routines. So the rcu stuff in the patch isn't entirely untested
(as the notifier routines have soaked it) but it should be double checked in
case I copied the code wrong.
Signed-off-by: Don Zickus <dzickus@redhat.com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/1317409584-23662-3-git-send-email-dzickus@redhat.com
Signed-off-by: Ingo Molnar <mingo@elte.hu>
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The nmi stuff is changing a lot and adding more functionality. Split it
out from the traps.c file so it doesn't continue to pollute that file.
This makes it easier to find and expand all the future nmi related work.
No real functional changes here.
Signed-off-by: Don Zickus <dzickus@redhat.com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/1317409584-23662-2-git-send-email-dzickus@redhat.com
Signed-off-by: Ingo Molnar <mingo@elte.hu>
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Intel does not have guest/host-only bit in perf counters like AMD
does. To support GO/HO bits KVM needs to switch EVENTSELn values
(or PERF_GLOBAL_CTRL if available) at a guest entry. If a counter is
configured to count only in a guest mode it stays disabled in a host,
but VMX is configured to switch it to enabled value during guest entry.
This patch adds GO/HO tracking to Intel perf code and provides interface
for KVM to get a list of MSRs that need to be switched on a guest entry.
Only cpus with architectural PMU (v1 or later) are supported with this
patch. To my knowledge there is not p6 models with VMX but without
architectural PMU and p4 with VMX are rare and the interface is general
enough to support them if need arise.
Signed-off-by: Gleb Natapov <gleb@redhat.com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/1317816084-18026-7-git-send-email-gleb@redhat.com
Signed-off-by: Ingo Molnar <mingo@elte.hu>
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* 'fixes' of git://git.linaro.org/people/arnd/arm-soc:
ARM: mach-ux500: enable fix for ARM errata 754322
ARM: OMAP: musb: Remove a redundant omap4430_phy_init call in usb_musb_init
ARM: OMAP: Fix i2c init for twl4030
ARM: OMAP4: MMC: fix power and audio issue, decouple USBC1 from MMC1
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This fixes a compilation error in cpu-tegra.c which was introduced in
dc8d966bccde ("ARM: convert PCI defines to variables") which removed the
now obsolete mach/hardware.h from the mach-tegra subtree.
Signed-off-by: Marc Dietrich <marvin24@gmx.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
Cc: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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* 'upstream' of git://git.linux-mips.org/pub/scm/upstream-linus: (29 commits)
MIPS: Call oops_enter, oops_exit in die
staging/octeon: Software should check the checksum of no tcp/udp packets
MIPS: Octeon: Enable C0_UserLocal probing.
MIPS: No branches in delay slots for huge pages in handle_tlbl
MIPS: Don't clobber CP0_STATUS value for CONFIG_MIPS_MT_SMTC
MIPS: Octeon: Select CONFIG_HOLES_IN_ZONE
MIPS: PM: Use struct syscore_ops instead of sysdevs for PM (v2)
MIPS: Compat: Use 32-bit wrapper for compat_sys_futex.
MIPS: Do not use EXTRA_CFLAGS
MIPS: Alchemy: DB1200: Disable cascade IRQ in handler
SERIAL: Lantiq: Set timeout in uart_port
MIPS: Lantiq: Fix setting the PCI bus speed on AR9
MIPS: Lantiq: Fix external interrupt sources
MIPS: tlbex: Fix build error in R3000 code.
MIPS: Alchemy: Include Au1100 in PM code.
MIPS: Alchemy: Fix typo in MAC0 registration
MIPS: MSP71xx: Fix build error.
MIPS: Handle __put_user() sleeping.
MIPS: Allow forced irq threading
MIPS: i8259: Mark cascade interrupt non-threaded
...
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Activate watchdog, rtc, usb, usb-gadget, keypad, audio for broader test
coverage. Disable remote controls. Activate ARM errata as mentioned in [1].
Rest of changes is caused by version bump to 3.1-rc9.
[1] http://www.spinics.net/lists/arm-kernel/msg88710.html
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Conflicts:
arch/arm/mach-ux500/cpu.c
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While suspending, we're enabling a clock in ->suspend() but we're in atomic
context, leading to this :
[30803.667305] PM: late suspend of devices complete after 1.237 msecs
[30803.667449] BUG: sleeping function called from invalid context at kernel/mutex.c:271
[30803.667464] in_atomic(): 0, irqs_disabled(): 128, pid: 4941, name: pm-suspend
[30803.667474] INFO: lockdep is turned off.
[30803.667483] irq event stamp: 0
[30803.667489] hardirqs last enabled at (0): [< (null)>] (null)
[30803.667503] hardirqs last disabled at (0): [<c001e4a8>] copy_process.part.48+0x1e0/0xa7c
[30803.667543] softirqs last enabled at (0): [<c001e4a8>] copy_process.part.48+0x1e0/0xa7c
[30803.667562] softirqs last disabled at (0): [< (null)>] (null)
[30803.667574] Backtrace:
[30803.667611] [<c0010e00>] (dump_backtrace+0x0/0x110) from [<c0424c00>] (dump_stack+0x18/0x1c)
[30803.667624] r6:00000000 r5:00000000 r4:d9648000 r3:d9648000
[30803.667652] [<c0424be8>] (dump_stack+0x0/0x1c) from [<c0424eec>] (__might_sleep.part.101+0x90/0xa8)
[30803.667673] [<c0424e5c>] (__might_sleep.part.101+0x0/0xa8) from [<c001a5c4>] (__might_sleep+0x80/0x94)
[30803.667686] r4:c05d58c0
[30803.667705] [<c001a544>] (__might_sleep+0x0/0x94) from [<c043230c>] (mutex_lock_nested+0x2c/0x30c)
[30803.667735] [<c04322e0>] (mutex_lock_nested+0x0/0x30c) from [<c0017834>] (clk_enable+0x28/0x50)
[30803.667747] r8:c0438464 r7:00000003 r6:00000000 r5:00000000 r4:c05d2e98
[30803.667780] [<c001780c>] (clk_enable+0x0/0x50) from [<c0017260>] (mx5_suspend_enter+0x1c/0x98)
[30803.667792] r4:00000003 r3:c060dfe0
[30803.667821] [<c0017244>] (mx5_suspend_enter+0x0/0x98) from [<c0059b48>] (suspend_enter+0xec/0x15c)
[30803.667833] r4:00000003 r3:c0017244
[30803.667856] [<c0059a5c>] (suspend_enter+0x0/0x15c) from [<c0059c4c>] (suspend_devices_and_enter+0x94/0x130)
[30803.667868] r6:00000000 r5:00000003 r4:c0c0af00 r3:00002710
[30803.667897] [<c0059bb8>] (suspend_devices_and_enter+0x0/0x130) from [<c0059db0>] (enter_state+0xc8/0x130)
[30803.667909] r6:00000000 r5:00000003 r4:c05286e4
[30803.667934] [<c0059ce8>] (enter_state+0x0/0x130) from [<c00592d4>] (state_store+0xac/0xc0)
[30803.667945] r6:00000003 r5:00000003 r4:df39d000 r3:00000003
[30803.667978] [<c0059228>] (state_store+0x0/0xc0) from [<c01b0100>] (kobj_attr_store+0x1c/0x28)
[30803.668009] [<c01b00e4>] (kobj_attr_store+0x0/0x28) from [<c00e435c>] (sysfs_write_file+0x88/0xbc)
[30803.668032] [<c00e42d4>] (sysfs_write_file+0x0/0xbc) from [<c0091fa0>] (vfs_write+0xbc/0x138)
[30803.668051] [<c0091ee4>] (vfs_write+0x0/0x138) from [<c0092204>] (sys_write+0x44/0x70)
[30803.668062] r8:00000000 r7:00000004 r6:00000003 r5:002694d0 r4:d966acc0
[30803.668094] [<c00921c0>] (sys_write+0x0/0x70) from [<c000db00>] (ret_fast_syscall+0x0/0x3c)
[30803.668106] r9:d9648000 r8:c000dcc4 r6:00000001 r5:002694d0 r4:00000003
[30803.669927] PM: early resume of devices complete after 0.972 msecs
Just move the clk_enable/disable in ->prepare() and ->finish()
Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
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This tries to clear up the confusion between integers and iomem pointers
in the marvell pxa platform. MMIO addresses are supposed to be __iomem*
values, in order to let the Linux type checking work correctly. This
patch moves the cast to __iomem as far back as possible, to the place
where the MMIO virtual address windows are defined.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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The sharpsl code selects the max1111 spi driver, so it must also
ensure that SPI itself is enabled. The platform does not work
without max1111.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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The two platforms are part of the palm27x family and use the same
code. Select the palm27x symbol to make sure they can be built
standalone.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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Reported-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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The raumfeld platform code calls power_supply_set_battery_charged
which is part of the power supply layer, so that always has
to be enabled.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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We cannot support ARMv5 and ARMv7 based boards in a single kernel,
so introduce a new option in mach-pxa to select between the two.
The PJ4 (ARMv7) based boards are now only visible when
CONFIG_ARCH_PXA_V7 is set, the other boards are only visible
when it's not set.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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The pxa specific cpufreq code is based on the cpu_freq_table
module, so we have to select that.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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saarb uses pxa3xx_map_io and pxa3xx_handle_irq, which are part
of the pxa3xx code. This makes sure the necessary header and
implementation is used when building the board file.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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There are two variants of the palmtreo machine, the 680 and the
centro, and Kconfig allows selecting one or both of them.
This changes the board file so that it's actually possible
to build all configurations that are allowed.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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The pxa3xx_u2d_start_hc/pxa3xx_u2d_stop_hc symbols are used by the
ohci-pxa27x driver, which can be a module.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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When support for zylonite is disabled, the zylonite_pxa300_init
and zylonite_pxa320_init functions are not there, but the declaration
is still kept around if any other boards for the same soc are
enabled. This changes the declaration to be conditional on the
same symbol as the code.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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Cc: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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ARMv6 cores do not implement the DBGOSLAR register, so we don't need to
try and clear it on boot. Furthermore, the VCR is zeroed out of reset,
so we don't need to zero it explicitly when a CPU comes online.
Tested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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* pm-qos:
PM / QoS: Update Documentation for the pm_qos and dev_pm_qos frameworks
PM / QoS: Add function dev_pm_qos_read_value() (v3)
PM QoS: Add global notification mechanism for device constraints
PM QoS: Implement per-device PM QoS constraints
PM QoS: Generalize and export constraints management code
PM QoS: Reorganize data structs
PM QoS: Code reorganization
PM QoS: Minor clean-ups
PM QoS: Move and rename the implementation files
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* pm-domains:
PM / Domains: Split device PM domain data into base and need_restore
ARM: mach-shmobile: sh7372 sleep warning fixes
ARM: mach-shmobile: sh7372 A3SM support
ARM: mach-shmobile: sh7372 generic suspend/resume support
PM / Domains: Preliminary support for devices with power.irq_safe set
PM: Move clock-related definitions and headers to separate file
PM / Domains: Use power.sybsys_data to reduce overhead
PM: Reference counting of power.subsys_data
PM: Introduce struct pm_subsys_data
ARM / shmobile: Make A3RV be a subdomain of A4LC on SH7372
PM / Domains: Rename argument of pm_genpd_add_subdomain()
PM / Domains: Rename GPD_STATE_WAIT_PARENT to GPD_STATE_WAIT_MASTER
PM / Domains: Allow generic PM domains to have multiple masters
PM / Domains: Add "wait for parent" status for generic PM domains
PM / Domains: Make pm_genpd_poweron() always survive parent removal
PM / Domains: Do not take parent locks to modify subdomain counters
PM / Domains: Implement subdomain counters as atomic fields
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Based on the documents that I have here, there doesn't appear to be an
equivalent to erratum i443 for OMAP3630, so restrict this one to OMAP34xx
chips.
Also, explicitly restrict this erratum to EMU and HS devices.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
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The way that we detect which OMAP3 chips support I/O wakeup and
software I/O chain clock control is broken.
Currently, I/O wakeup is marked as present for all OMAP3 SoCs other
than the AM3505/3517. The TI81xx family of SoCs are at present
considered to be OMAP3 SoCs, but don't support I/O wakeup. To resolve
this, convert the existing blacklist approach to an explicit,
whitelist support, in which only SoCs which are known to support I/O
wakeup are listed. (At present, this only includes OMAP34xx,
OMAP3503, OMAP3515, OMAP3525, OMAP3530, and OMAP36xx.)
Also, the current code incorrectly detects the presence of a
software-controllable I/O chain clock on several chips that don't
support it. This results in writes to reserved bitfields, unnecessary
delays, and console messages on kernels running on those chips:
http://www.spinics.net/lists/linux-omap/msg58735.html
Convert this test to a feature test with a chip-by-chip whitelist.
Thanks to Dave Hylands <dhylands@gmail.com> for reporting this problem
and doing some testing to help isolate the cause. Thanks to Steve
Sakoman <sakoman@gmail.com> for catching a bug in the first version of
this patch. Thanks to Russell King <linux@arm.linux.org.uk> for
comments.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Dave Hylands <dhylands@gmail.com>
Cc: Steve Sakoman <sakoman@gmail.com>
Tested-by: Steve Sakoman <sakoman@gmail.com>
Cc: Russell King - ARM Linux <linux@arm.linux.org.uk>
Signed-off-by: Kevin Hilman <khilman@ti.com>
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The context lost count is modified in omap_sram_idle() path when
pwrdm_post_transition() is called. But pwrdm_post_transition() is called
only after omap_gpio_resume_after_idle() is called. Correct this so that
context lost count is modified before calling omap_gpio_resume_after_idle().
This would be useful when OMAP GPIO save/restore context is called by
the OMAP GPIO driver itself.
Signed-off-by: Charulatha V <charu@ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
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into next/devel
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This helps resolve the conflicts between the imx cleanups and the
new code that has gone into the imx tree.
Conflict resolution was originally done by Sascha Hauer.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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While suspending, we're enabling a clock in ->suspend() but we're in atomic
context, leading to this :
[30803.667305] PM: late suspend of devices complete after 1.237 msecs
[30803.667449] BUG: sleeping function called from invalid context at kernel/mutex.c:271
[30803.667464] in_atomic(): 0, irqs_disabled(): 128, pid: 4941, name: pm-suspend
[30803.667474] INFO: lockdep is turned off.
[30803.667483] irq event stamp: 0
[30803.667489] hardirqs last enabled at (0): [< (null)>] (null)
[30803.667503] hardirqs last disabled at (0): [<c001e4a8>] copy_process.part.48+0x1e0/0xa7c
[30803.667543] softirqs last enabled at (0): [<c001e4a8>] copy_process.part.48+0x1e0/0xa7c
[30803.667562] softirqs last disabled at (0): [< (null)>] (null)
[30803.667574] Backtrace:
[30803.667611] [<c0010e00>] (dump_backtrace+0x0/0x110) from [<c0424c00>] (dump_stack+0x18/0x1c)
[30803.667624] r6:00000000 r5:00000000 r4:d9648000 r3:d9648000
[30803.667652] [<c0424be8>] (dump_stack+0x0/0x1c) from [<c0424eec>] (__might_sleep.part.101+0x90/0xa8)
[30803.667673] [<c0424e5c>] (__might_sleep.part.101+0x0/0xa8) from [<c001a5c4>] (__might_sleep+0x80/0x94)
[30803.667686] r4:c05d58c0
[30803.667705] [<c001a544>] (__might_sleep+0x0/0x94) from [<c043230c>] (mutex_lock_nested+0x2c/0x30c)
[30803.667735] [<c04322e0>] (mutex_lock_nested+0x0/0x30c) from [<c0017834>] (clk_enable+0x28/0x50)
[30803.667747] r8:c0438464 r7:00000003 r6:00000000 r5:00000000 r4:c05d2e98
[30803.667780] [<c001780c>] (clk_enable+0x0/0x50) from [<c0017260>] (mx5_suspend_enter+0x1c/0x98)
[30803.667792] r4:00000003 r3:c060dfe0
[30803.667821] [<c0017244>] (mx5_suspend_enter+0x0/0x98) from [<c0059b48>] (suspend_enter+0xec/0x15c)
[30803.667833] r4:00000003 r3:c0017244
[30803.667856] [<c0059a5c>] (suspend_enter+0x0/0x15c) from [<c0059c4c>] (suspend_devices_and_enter+0x94/0x130)
[30803.667868] r6:00000000 r5:00000003 r4:c0c0af00 r3:00002710
[30803.667897] [<c0059bb8>] (suspend_devices_and_enter+0x0/0x130) from [<c0059db0>] (enter_state+0xc8/0x130)
[30803.667909] r6:00000000 r5:00000003 r4:c05286e4
[30803.667934] [<c0059ce8>] (enter_state+0x0/0x130) from [<c00592d4>] (state_store+0xac/0xc0)
[30803.667945] r6:00000003 r5:00000003 r4:df39d000 r3:00000003
[30803.667978] [<c0059228>] (state_store+0x0/0xc0) from [<c01b0100>] (kobj_attr_store+0x1c/0x28)
[30803.668009] [<c01b00e4>] (kobj_attr_store+0x0/0x28) from [<c00e435c>] (sysfs_write_file+0x88/0xbc)
[30803.668032] [<c00e42d4>] (sysfs_write_file+0x0/0xbc) from [<c0091fa0>] (vfs_write+0xbc/0x138)
[30803.668051] [<c0091ee4>] (vfs_write+0x0/0x138) from [<c0092204>] (sys_write+0x44/0x70)
[30803.668062] r8:00000000 r7:00000004 r6:00000003 r5:002694d0 r4:d966acc0
[30803.668094] [<c00921c0>] (sys_write+0x0/0x70) from [<c000db00>] (ret_fast_syscall+0x0/0x3c)
[30803.668106] r9:d9648000 r8:c000dcc4 r6:00000001 r5:002694d0 r4:00000003
[30803.669927] PM: early resume of devices complete after 0.972 msecs
Just move the clk_enable/disable in ->prepare() and ->finish()
Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
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The LEON MMU Model (SRMMU) does not implement MMu Table probing
in hardware, instead it is implemented in software. However the
software implementation does not return the PTE as it should which
always results in INVALID entires and the PROM mappings are not
inherited as they should during startup. The following patch
removes the masking of the PTE.
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Conflicts:
net/batman-adv/soft-interface.c
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Defconfig file for at91sam9g45 SoC family:
at91sam9g45, at91sam9g46, at91sam9m10, at91sam9m11.
The Atmel Evaluation Kit for this family is the at91sam9m10g45ek.
It is so useful for automatic compile tests...
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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This applies ARM errata fix 754322 for all ux500 platforms.
Cc: stable@kernel.org
Signed-off-by: srinidhi kasagar <srinidhi.kasagar@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Signed-off-by: Richard Zhu <richard.zhu@linaro.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Richard Zhu <richard.zhu@linaro.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Richard Zhu <richard.zhu@linaro.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Richard Zhu <richard.zhu@linaro.org>
Tested-by: Hector Oron Martinez <hector.oron@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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