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2012-03-16ARM: ux500: Provide local timer support for Device TreeLee Jones
This enables local timer (AKA: private timer) support for all u8500 based hardware using DT. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2012-03-16ARM: ux500: Enable PL022 SSP Controller in Device TreeLee Jones
This SSP Controller supports a number of serial communication methods and as such cannot be registered using of_register_spi_devices. Instead we register it simply as a primecell device. Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2012-03-16ARM: ux500: Enable PL310 Level 2 Cache Controller in Device TreeLee Jones
This provides PL310 Level 2 Cache Controller Device Tree support for all u8500 based devices. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2012-03-16ARM: ux500: Enable PL011 AMBA UART Controller for Device TreeLee Jones
Enables the 3 UARTs found on a u8500 using DT. Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2012-03-16ARM: ux500: Enable Cortex-A9 GIC (Generic Interrupt Controller) in Device TreeLee Jones
This enables the embedded GIC on all u8500 based hardware using DT. Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2012-03-16ARM: ux500: db8500: list most devices in the snowball device treeLee Jones
This adds all devices that are normally present through the u8500_init_machine function in the device tree as well, which will duplicate the devices that are visible. This will not do much by itself because the device from the device tree are not matched by any device driver until they are converted as well. The next step is to move over one device at a time to actually be used from the device tree instead of the hardcoded device using auxdata to pass the correct platform_data. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2012-03-16ARM: ux500: split dts file for snowball into generic partArnd Bergmann
db8500.dtsi can be used by all systems with a db8500 or db9500 SoC, while snowball.dts is board specific. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2012-03-16ARM: ux500: combine the board init functions for DT bootArnd Bergmann
This lets us move over evertything to device tree one by one. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2012-03-16ARM: ux500: Initial Device Tree support for SnowballArnd Bergmann
This provides very basic Device Tree support for ST-Ericsson's low-cost development platform, Snowball. If Device Tree for ux500 is enabled and the correct board is configured within the Device Tree blob, the correct *_init_machine() will be called. This patch is based on some original work completed by: Niklas Hernaeus <niklas.hernaeus@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Niklas Hernaeus <niklas.hernaeus@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2012-03-16ARM: ux500: CONFIG: Enable Device Tree support for future endeavoursLee Jones
Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2012-03-16powerpc/83xx: mpc836x - fix failed phy detection for ucc ethernet on MDSPaul Gortmaker
The mpc836x_mds platform has been broken since the commit 6fe3264945ee63292cdfb27b6e95bc52c603bb09 "netdev/phy: Use mdiobus_read() so that proper locks are taken" which caused the fsl_pq_mdio TBI autoprobe to oops. The oops was "fixed" in commit 28d8ea2d568534026ccda3e8936f5ea1e04a86a1 "fsl_pq_mdio: Clean up tbi address configuration" by simply removing the the autoscan code, and making tbi nodes mandatory. Some of the newer reference platforms were updated to have tbi nodes in 220669495bf8b68130a8218607147c7b74c28d2b "powerpc: Add TBI PHY node to first MDIO bus" but the older mpc836x didn't get one and hence was just failing with -EBUSY as follows: fsl-pq_mdio: probe of e0102120.mdio failed with error -16 ... net eth0: Could not attach to PHY eth0: Cannot initialize PHY, aborting. Add a TBI node and use the 1st free address for it. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-03-16Merge branch 'depends/driver-core' into ux500/dtArnd Bergmann
Conflicts: drivers/base/cpu.c
2012-03-16Merge branch 'ux500/soc' into ux500/dtArnd Bergmann
2012-03-16ARM: S3C64XX: Hook up supply for WM8994 LDOs on LittlemillMark Brown
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
2012-03-16mfd: Remove unused LDO supply field from WM8994 pdataMark Brown
It's causing confusion with the regulator level field of the same name and serves no useful function. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
2012-03-16perf: Adding sysfs group format attribute for pmu deviceJiri Olsa
Adding sysfs group 'format' attribute for pmu device that contains a syntax description on how to construct raw events. The event configuration is described in following struct pefr_event_attr attributes: config config1 config2 Each sysfs attribute within the format attribute group, describes mapping of name and bitfield definition within one of above attributes. eg: "/sys/...<dev>/format/event" contains "config:0-7" "/sys/...<dev>/format/umask" contains "config:8-15" "/sys/...<dev>/format/usr" contains "config:16" the attribute value syntax is: line: config ':' bits config: 'config' | 'config1' | 'config2" bits: bits ',' bit_term | bit_term bit_term: VALUE '-' VALUE | VALUE Adding format attribute definitions for x86 cpu pmus. Acked-by: Peter Zijlstra <peterz@infradead.org> Signed-off-by: Peter Zijlstra <peterz@infradead.org> Signed-off-by: Jiri Olsa <jolsa@redhat.com> Link: http://lkml.kernel.org/n/tip-vhdk5y2hyype9j63prymty36@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2012-03-16powerpc/85xx: p1022ds: enable monitor switching via pixis indirect modeTimur Tabi
When the P1022's DIU video controller is active, the pixis must be accessed in "indirect" mode, which uses localbus chip select addresses. Switching between the DVI and LVDS monitor ports is handled by the pixis, so that switching needs to be done via indirect mode. This has the side-effect of no longer requiring U-Boot to enable the DIU. Now Linux can enable the DIU all by itself. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-03-16powerpc/85xx: Board support for GE IMP3AMartyn Welch
Initial board support for the GE IMP3A, a 3U compactPCI card with a p2020 processor. Signed-off-by: Martyn Welch <martyn.welch@ge.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-03-16powerpc: Move GE PIC driversMartyn Welch
Move the GE PIC drivers to allow these to be used by non-86xx boards. Signed-off-by: Martyn Welch <martyn.welch@ge.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-03-16gpio: Move GE GPIO driver to reside within GPIO subsystemMartyn Welch
The GE GPIO driver provides basic support (set direction, read/write state) for the GPIO provided on some GE single board computers. This patch moves the driver from the 86xx specific platform directrory to the GPIO subsystem so that it can be used on non-86xx boards. Signed-off-by: Martyn Welch <martyn.welch@ge.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-03-16powerpc: Add GE FPGA config optionMartyn Welch
This patch adds the GE_FPGA configuration option. This is being carried out as ground work to allow the PIC and GPIO drivers to be move from the powerpc 86xx platform directory to more general locations to allow them to be used on non-86xx boards and to reduce churn when further boards using these drivers are added. Signed-off-by: Martyn Welch <martyn.welch@ge.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-03-16powerpc/85xx: Add dts for p1020rdb-pc boardZhicheng Fan
P1020RDB-PC Overview ------------------ 1Gbyte DDR3 SDRAM 32 Mbyte NAND flash 10 16Mbyte NOR flash 16 Mbyte SPI flash SD connector to interface with the SD memory card Real-time clock on I2C bus PCIe: - x1 PCIe slot - x1 mini-PCIe slot 10/100/1000 BaseT Ethernet ports: - eTSEC1, RGMII: one 10/100/1000 port using VitesseTM VSC7385 L2 switch - eTSEC2, SGMII: one 10/100/1000 port using VitesseTM VSC8221 - eTSEC3, RGMII: one 10/100/1000 port using AtherosTM AR8021 USB 2.0 port: - Two USB2.0 Type A receptacles - One USB2.0 signal to Mini PCIe slot Dual RJ45 UART ports: - DUART interface: supports two UARTs up to 115200 bps for console display Signed-off-by: Zhicheng Fan <b32736@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-03-16powerpc/85xx: Add p1020rdb-pc platform supportZhicheng Fan
Signed-off-by: Zhicheng Fan <b32736@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-03-16powerpc/85xx: add P1020UTM-PC platform supportJerry Huang
The p1020utm-pc has the similar feature as the p1020rdb. Therefore, p1020utm-pc use the same platform file as the p1/p2 rdb board. Overview of P1020UTM-PC platform: - DDR3 1GB - NOR flash 32MB - I2C EEPROM 256Kb - eTSEC1 (RGMII PHY Atheros AR8021) - eTSEC2 (SGMII PHY Vitesse VSC8221) - eTSEC3 (RGMII PHY Atheros AR8021) - SDHC - 2 USB ports - PCIe (Lane1 to dual SATA controller) Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-03-16powerpc/85xx: add P1020MBG-PC platform supportJerry Huang
The p1020mbg-pc has the similar feature as the p1020rdb. Therefore, p1020mbg-pc use the same platform file as the p1/p2 rdb board. Overview of P1020MBG-PC platform: - DDR3 2GB - NOR flash 64MB - I2C EEPROM 256Kb - eTSEC1 (RGMII PHY) connected to VSC7385 L2 switch - eTSEC2 (SGMII PHY) - eTSEC3 (RGMII PHY) - SDHC - 2 USB ports - 4 TDM ports - PCIe (Lane1 to dual SATA controller) Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-03-16powerpc/85xx: Clean up partition nodes in dts for MPC8572DSJia Hongtao
Signed-off-by: Jin Qing <b24347@freescale.com> Signed-off-by: Jia Hongtao <B38951@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-03-16powerpc/85xx: p1022ds: disable the NOR flash node if video is enabledTimur Tabi
The Freescale P1022 has a unique pin muxing "feature" where the DIU video controller's video signals are muxed with 24 of the local bus address signals. When the DIU is enabled, the bulk of the local bus is disabled, preventing access to memory-mapped devices like NOR flash and the pixis FPGA. Therefore, if the DIU is going to be enabled, then memory-mapped devices on the localbus, like NOR flash, need to be disabled. This also means that the localbus is not a 'simple-bus' any more, so remove that string from the compatible node. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-03-16powerpc/85xx: create 32-bit DTS for the P1022DSTimur Tabi
Create a 32-bit address space version of p1022ds.dts. To avoid confusion, p1022ds.dts is renamed to p1022ds_36b.dts. We also create p1022ds.dtsi to store some common nodes. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-03-16powerpc/85xx: Add magic-packet properties for etsecXie Xiaobo
The properties indicates that the hardware supports waking up via magic packet. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-03-16powerpc/85xx: Add some DTS nodes and attributes for mpc8536dsXie Xiaobo
Add partitions for NOR and NAND Flash. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-03-16powerpc/fsl_msi: return proper error value when ioremap failed.Liu Shuo
Signed-off-by: Liu Shuo <soniccat.liu@gmail.com> Acked-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-03-16powerpc/85xx: fix typo in p1010rdb.dtsiGustavo Zacarias
Fix typo introduced by "powerpc: Add TBI PHY node to first MDIO bus" from Andy Fleming. It's device_type rather than device-type, which causes the mdio probe to fail thus making all gianfar ethernet interfaces unusable. Signed-off-by: Gustavo Zacarias <gustavo@zacarias.com.ar> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-03-16powerpc/85xx: p2020rdb & p1010rdb - lower spi flash freq to 40MhzSebastian Andrzej Siewior
This is here most likely since the FSL bsp. Back in the FSL bsp it was set to 50Mhz and working. However the driver divided the SoC freq. only by 2. According to the TRM the platform clock (which the manual refers in its formula) is the system clock divided by two. So in the end it has to divide by 4 and this is what the fsl-spi driver in tree is doing. Since then the flash is not wokring I guess. After chaning the freq from 50Mhz to 40Mhz like others do then I can access the flash. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-03-16powerpc/85xx: p2020rdb - move the NAND address.Sebastian Andrzej Siewior
It is not at 0xffa00000. According to current u-boot source the NAND controller is always at 0xff800000 and it is either at CS0 or CS1 depending on NAND or NAND+NOR mode. In 36bit mode it is shifted to 0xfff800000 but it has always an eight there and never an A. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-03-16powerpc/srio: Fix the compile errors when building with 64bitLiu Gang
For the file "arch/powerpc/sysdev/fsl_rmu.c", there will be some compile errors while using the corenet64_smp_defconfig: .../fsl_rmu.c:315: error: cast from pointer to integer of different size .../fsl_rmu.c:320: error: cast to pointer from integer of different size .../fsl_rmu.c:320: error: cast to pointer from integer of different size .../fsl_rmu.c:320: error: cast to pointer from integer of different size .../fsl_rmu.c:330: error: cast to pointer from integer of different size .../fsl_rmu.c:332: error: cast to pointer from integer of different size .../fsl_rmu.c:339: error: cast to pointer from integer of different size .../fsl_rmu.c:340: error: cast to pointer from integer of different size .../fsl_rmu.c:341: error: cast to pointer from integer of different size .../fsl_rmu.c:348: error: cast to pointer from integer of different size .../fsl_rmu.c:348: error: cast to pointer from integer of different size .../fsl_rmu.c:348: error: cast to pointer from integer of different size .../fsl_rmu.c:659: error: cast from pointer to integer of different size .../fsl_rmu.c:659: error: format '%8.8x' expects type 'unsigned int', but argument 5 has type 'size_t' .../fsl_rmu.c:985: error: cast from pointer to integer of different size .../fsl_rmu.c:997: error: cast to pointer from integer of different size Rewrote the corresponding code with the support of 64bit building. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reported-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-03-16powerpc/srio: Fix the relocation errors when building with 64bitLiu Gang
For the file "arch/powerpc/sysdev/fsl_rio.c", there will be some relocation errors while using the corenet64_smp_defconfig: WARNING: modpost: Found 6 section mismatch(es). To see full details build your kernel with: 'make CONFIG_DEBUG_SECTION_MISMATCH=y' GEN .version CHK include/generated/compile.h UPD include/generated/compile.h CC init/version.o LD init/built-in.o LD .tmp_vmlinux1 arch/powerpc/sysdev/built-in.o:(__ex_table+0x0): relocation truncated to fit: R_PPC64_ADDR16 against `.text'+3208 arch/powerpc/sysdev/built-in.o:(__ex_table+0x2): relocation truncated to fit: R_PPC64_ADDR16 against `.fixup' arch/powerpc/sysdev/built-in.o:(__ex_table+0x4): relocation truncated to fit: R_PPC64_ADDR16 against `.text'+3230 arch/powerpc/sysdev/built-in.o:(__ex_table+0x6): relocation truncated to fit: R_PPC64_ADDR16 against `.fixup'+c arch/powerpc/sysdev/built-in.o:(__ex_table+0x8): relocation truncated to fit: R_PPC64_ADDR16 against `.text'+3250 arch/powerpc/sysdev/built-in.o:(__ex_table+0xa): relocation truncated to fit: R_PPC64_ADDR16 against `.fixup'+18 Rewrote the corresponding code with the support of 64bit building. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-03-16powerpc/85xx: Add dts for p1025rdb boardZhicheng Fan
P1025RDB Overview ------------------ 1Gbyte DDR3 SDRAM 32 Mbyte NAND flash 16Mbyte NOR flash 16 Mbyte SPI flash SD connector to interface with the SD memory card Real-time clock on I2C bus PCIe: - x1 PCIe slot - x1 mini-PCIe slot 10/100/1000 BaseT Ethernet ports: - eTSEC1, RGMII: one 10/100/1000 port using AtherosTM AR8021 - eTSEC2, SGMII: one 10/100/1000 port using VitesseTM VSC8221 - eTSEC3, RGMII: one 10/100/1000 port using AtherosTM AR8021 USB 2.0 port: - Two USB2.0 Type A receptacles - One USB2.0 signal to Mini PCIe slot Dual RJ45 UART ports: - DUART interface: supports two UARTs up to 115200 bps for console display Signed-off-by: Zhicheng Fan <b32736@freescale.com> Acked-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-03-16powerpc/85xx: Add p1025rdb platform supportZhicheng Fan
Signed-off-by: Zhicheng Fan <b32736@freescale.com> Acked-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-03-16powerpc/85xx: Add usb controller version infoRamneek Mehresh
Add usb controller version info for the following: MPC8536, P1010, P1020, P1021, P1022, P1023, P2020, P2041, P3041, P3060, P5020 Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-03-16powerpc/85xx: Add p2020rdb-pc dts supportTang Yuantian
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Tang Yuantian <b29983@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-03-16powerpc/85xx: Adds Support for P2020RDB-PC boardTang Yuantian
P2020RDB-PC Board shares the same design(PCB) as P102x RDB style platforms. The difference between this platform and the already existing P2020RDB is mainly with respect to DDR. The P2020RDB-PC has a DDR3 memory. The P2020RDB-PC also has a CPLD device connected to local bus. The main differences from the P102x RDB-PC is 64-bit DDR and SYSCLK of 100Mhz. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Tang Yuantian <b29983@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-03-16powerpc/85xx: Added P1021RDB-PC Platform supportXu Jiucheng
Signed-off-by: Xu Jiucheng <B37781@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-03-16powerpc/85xx: Added dts for P1021RDB-PC boardXu Jiucheng
P1021RDB-PC Overview ----------------- 1Gbyte DDR3 (on board DDR) 16Mbyte NOR flash 32Mbyte eSLC NAND Flash 256 Kbit M24256 I2C EEPROM 128 Mbit SPI Flash memory Real-time clock on I2C bus SD/MMC connector to interface with the SD memory card PCIex - x1 PCIe slot or x1 PCIe to dual SATA controller - x1 mini-PCIe slot USB 2.0 - ULPI PHY interface: SMSC USB3300 USB PHY and Genesys Logic’s GL850A - Two USB2.0 Type A receptacles - One USB2.0 signal to Mini PCIe slot eTSEC1: Connected to RGMII PHY VSC7385 eTSEC2: Connected to SGMII PHY VSC8221 eTSEC3: Connected to SGMII PHY AR8021 DUART interface: supports two UARTs up to 115200 bps for console display Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Xu Jiucheng <B37781@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-03-16C6X: remove dead code from entry.SMark Salter
The ENDPROC() on sys_fadvise64_c6x() in arch/c6x/kernel/entry.S is outside of the conditional block with the matching ENTRY() macro. This leads a newer (v2.22 vs. v2.20) assembler to complain: /tmp/ccGZBaPT.s: Assembler messages: /tmp/ccGZBaPT.s: Error: .size expression for sys_fadvise64_c6x does not evaluate to a constant The conditional block became dead code when c6x switched to generic unistd.h and should be removed along with the offending ENDPROC(). Signed-off-by: Mark Salter <msalter@redhat.com> Acked-by: David Howells <dhowells@redhat.com>
2012-03-16Merge branch 'at91-3.4-cleanup2-DT2+USB' of ↵Arnd Bergmann
git://github.com/at91linux/linux-at91 into next/dt * 'at91-3.4-cleanup2-DT2+USB' of git://github.com/at91linux/linux-at91: ARM: at91: sam9g20 udc add dt support USB: at91: Device udc add dt support
2012-03-16Merge branch 'at91-3.4-cleanup2-DT2' of ↵Arnd Bergmann
git://github.com/at91linux/linux-at91 into next/dt * 'at91-3.4-cleanup2-DT2' of git://github.com/at91linux/linux-at91: (23 commits) ARM: at91: dt: enable usb ehci for sam9g45 and sam9x5 ARM: at91: usb ehci add dt support ARM: at91: dt: enable usb ohci for sam9g20, sam9g45 amd sam9x5 ARM: at91: usb ohci add dt support ARM: at91: add Shutdown Controller (SHDWC) DT support ARM: at91: add ram controller DT support ARM: at91: add RSTC (Reset Controller) dt support ARM: at91: always enable sam9 restart ARM: at91: add pmc DT support ARM: at91/dt: add specific DT soc init ARM: at91/dt: add Calao DAB-MMX daugther board support for USB-A9G20 ARM: at91: sam9x5 add i2c DT support ARM: at91: sam9g45 add i2c DT support ARM: at91: usb_a9g20 add DT i2c support ARM: at91: sam9g20 add i2c DT support i2c/gpio: add DT support ARM: at91: sam9x5 add nand support atmel/nand: add DT support of/mtd/nand: add generic bindings and helpers of: introduce helper to manage boolean ...
2012-03-16ARM: kirkwood: use devicetree for rtc-mvJason Cooper
Signed-off-by: Jason Cooper <jason@lakedaemon.net> Acked-by: Arnd Bergmann <arnd@arndb.de>
2012-03-16ARM: kirkwood: fdt: define uart[01] as disabled, enable uart0Jason Cooper
Define both uarts in kirkwood.dtsi as they are common to all kirkwood SoCs. Each board may enable all or none of them, so they are disabled by default. uart0 is enabled for the dreamplug. tclk can vary for each board, so we leave it undefined in the kirkwood dtsi. Each board can then set it as appropriate when enabling the uart. Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2012-03-16ARM: kirkwood: fdt: facilitate new boards during fdt migrationJason Cooper
Move all dreamplug-specific code out of board-dt.c and into board-dreamplug.c. This way new boards that are added during the conversion to fdt don't clutter up board-dt.c. Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2012-03-16ARM: kirkwood: fdt: absorb kirkwood_init()Jason Cooper
We need to absorb kirkwood_init() into kirkwood_dt_init() so that as we convert drivers, we can remove the platform call, eg kirkwood_rtc_init(). This maintains compatibility with non-fdt configurations because they still call kirkwood_init() in common.c. As drivers are converted, we will reinstate the 'static' qualifier in common.c. Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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