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2012-09-27m68knommu: fix inconsistent formating in ColdFire 5307 definitionsGreg Ungerer
Fix tab broken address defines to be consistent with others in this file. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-27m68knommu: fix inconsistent formating in ColdFire 527x definitionsGreg Ungerer
Fix tab broken address defines to be consistent with others in this file. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-27m68knommu: fix inconsistent formating in ColdFire 5272 definitionsGreg Ungerer
Fix tab broken defines to be consistent with others in this file. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-27m68knommu: fix inconsistent formating in ColdFire 523x definitionsGreg Ungerer
Fix tab broken address defines to be consistent with others in this file. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-27m68knommu: clean up ColdFire 54xx General Timer definitionsGreg Ungerer
Convert the ColdFire 54xx CPU General Timer register address definitions to include the MCF_MBAR peripheral region offset. This makes them consistent with all other 54xx address register definitions (in m54xxsim.h). The goal is to reduce different definitions used (some including offsets and others not) causing bugs when used incorrectly. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-27m68knommu: clean up Pin Assignment definitions for the 54xx ColdFire CPUGreg Ungerer
The Pin Assignment register definitions for the ColdFire 54xx CPU family are inconsistently named and defined compared to the other ColdFire part definitions. Rename them with the same prefix as used on other parts, MCFGPIO_PAR_, and make their definitions include the MCF_MBAR periphperal region offset. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-27m68knommu: fix multi-function pin setup for FEC module on ColdFire 523xGreg Ungerer
The multi-function pin setup code for the FEC ethernet module is using just plain wrong. Looks like it was cut-and-pasted from other init code. It has hard coded register addresses that are incorrect for the 523x, and it is manipulating bits that don't make sense. Add proper register definitions for the Pin Assignment registers of the 532x, and then use them to fix the setup code for the FEC hardware module. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-27m68knommu: move ColdFire slice timer address defiens to 54xx headerGreg Ungerer
Move the base address defines of the ColdFire 54xx CPU slice timers into the 54xx specific header (m54xxsim.h). They are CPU specific, and belong with the CPU specific defines. Also make them relative to the MBAR peripheral region, making the define the absolute address. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-27m68knommu: use read/write IO access functions in ColdFire m532x setup codeGreg Ungerer
Get rid of the use of local IO access macros and switch to using the standard read*/write* family of access functions for the ColdFire m532x setup code. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-27m68knommu: modify ColdFire 532x GPIO register definitions to be consistentGreg Ungerer
The ColdFire 532x CPU register definitions for the multi-function setup pins are inconsistently defined compared with other ColdFire parts. Modify the register defintions to be just the addresses, not pointers. This also fixes the erroneous use in one case of using these values in the UART setup code for the 532x. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-27m68knommu: remove a lot of unsed definitions for 532x ColdFireGreg Ungerer
There are a lot of unused and uneccessary definitions in the header to support the ColdFire 532x CPU family. Remove the junk. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-27m68knommu: use definitions for the ColdFire 528x FEC multi-function pinsGreg Ungerer
Currently the setup code for the FEC multi-function pins on the ColdFire 528x has the addresses hard coded in the code. Use the register defines that already exist for this. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-27m68knommu: remove address offsets relative to IPSBAR for ColdFire 527xGreg Ungerer
Remove the last address definitions relative to the IPSBAR peripheral region for the ColdFire 527x family. This involved cleaning up some magic numbers used in the code part, and making them proper register definitions in the 527x specific header. This is part of the process of cleaning up the ColdFire register definitions to make them consistently use absolute addresses for the primary registers. This will reduce the occasional bugs caused by inconsistent definition of the register addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-27m68knommu: remove unused ColdFire 5282 register definitionsGreg Ungerer
There is a bunch of old unused and ugly register definitions in the ColdFire 5282 header. Remove them. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-27m68knommu: fix wrong register offsets used for ColdFire 5272 multi-function pinsGreg Ungerer
The registers used to configure and set the multifunction pins on the 5272 ColdFire are defined as absolute addresses. So the use of them does not need to be offset relative to the peripheral region address. Fix two cases of incorrect usage of these addresses. Both affect UART initialization, one in the common UART pin setup code, the other in the NETtel board specific UART signal handling. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-27m68knommu: make ColdFire 5249 MBAR2 register definitions absolute addressesGreg Ungerer
Make the ColdFire 5249 MBAR peripheral register definitions absolute addresses, instead of offsets into the region. The various ColdFire parts use different methods to address the internal registers, some are absolute, some are relative to peripheral regions which can be mapped at different address ranges (such as the MBAR and IPSBAR registers). We don't want to deal with this in the code when we are accessing these registers, so make all register definitions the absolute address - factoring out whether it is an offset into a peripheral region. This makes them all consistently defined, and reduces the occasional bugs caused by inconsistent definition of the register addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-27m68knommu: make remaining ColdFire 5272 register definitions absolute addressesGreg Ungerer
Make the remaining definitions of the 5272 ColdFire registers absolute addresses. Currently some are relative to the MBAR peripheral region. The various ColdFire parts use different methods to address the internal registers, some are absolute, some are relative to peripheral regions which can be mapped at different address ranges (such as the MBAR and IPSBAR registers). We don't want to deal with this in the code when we are accessing these registers, so make all register definitions the absolute address - factoring out whether it is an offset into a peripheral region. This makes them all consistently defined, and reduces the occasional bugs caused by inconsistent definition of the register addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-27m68knommu: make ColdFire Park and Assignment register definitions absolute ↵Greg Ungerer
addresses Make all definitions of the ColdFire MPARK and IRQ Assignment registers absolute addresses. Currently some are relative to the MBAR peripheral region. The various ColdFire parts use different methods to address the internal registers, some are absolute, some are relative to peripheral regions which can be mapped at different address ranges (such as the MBAR and IPSBAR registers). We don't want to deal with this in the code when we are accessing these registers, so make all register definitions the absolute address - factoring out whether it is an offset into a peripheral region. This makes them all consistently defined, and reduces the occasional bugs caused by inconsistent definition of the register addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-27m68knommu: make ColdFire Chip Select register definitions absolute addressesGreg Ungerer
Make all definitions of the ColdFire Chip Select registers absolute addresses. Currently some are relative to the MBAR peripheral region. The various ColdFire parts use different methods to address the internal registers, some are absolute, some are relative to peripheral regions which can be mapped at different address ranges (such as the MBAR and IPSBAR registers). We don't want to deal with this in the code when we are accessing these registers, so make all register definitions the absolute address - factoring out whether it is an offset into a peripheral region. This makes them all consistently defined, and reduces the occasional bugs caused by inconsistent definition of the register addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-27m68knommu: make ColdFire Interrupt Source register definitions absolute ↵Greg Ungerer
addresses Make all definitions of the ColdFire Interrupt Source registers absolute addresses. Currently some are relative to the MBAR peripheral region. The various ColdFire parts use different methods to address the internal registers, some are absolute, some are relative to peripheral regions which can be mapped at different address ranges (such as the MBAR and IPSBAR registers). We don't want to deal with this in the code when we are accessing these registers, so make all register definitions the absolute address - factoring out whether it is an offset into a peripheral region. This makes them all consistently defined, and reduces the occasional bugs caused by inconsistent definition of the register addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-27m68knommu: make ColdFire Pin Assignment register definitions absolute addressesGreg Ungerer
Make all definitions of the ColdFire Pin Assignment registers absolute addresses. Currently some are relative to the MBAR peripheral region. The various ColdFire parts use different methods to address the internal registers, some are absolute, some are relative to peripheral regions which can be mapped at different address ranges (such as the MBAR and IPSBAR registers). We don't want to deal with this in the code when we are accessing these registers, so make all register definitions the absolute address - factoring out whether it is an offset into a peripheral region. This makes them all consistently defined, and reduces the occasional bugs caused by inconsistent definition of the register addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-27m68knommu: make ColdFire watchdog register definitions absolute addressesGreg Ungerer
Make all definitions of the ColdFire Software watchdog registers absolute addresses. Currently some are relative to the MBAR peripheral region. The various ColdFire parts use different methods to address the internal registers, some are absolute, some are relative to peripheral regions which can be mapped at different address ranges (such as the MBAR and IPSBAR registers). We don't want to deal with this in the code when we are accessing these registers, so make all register definitions the absolute address - factoring out whether it is an offset into a peripheral region. This makes them all consistently defined, and reduces the occasional bugs caused by inconsistent definition of the register addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-27m68knommu: make ColdFire SYPCR and RSR register definitions absolute addressesGreg Ungerer
Make all definitions of the ColdFire Reset and System registers absolute addresses. Currently some are relative to the MBAR peripheral region. The various ColdFire parts use different methods to address the internal registers, some are absolute, some are relative to peripheral regions which can be mapped at different address ranges (such as the MBAR and IPSBAR registers). We don't want to deal with this in the code when we are accessing these registers, so make all register definitions the abolsute address - factoring out whether it is an offset into a peripheral region. This makes them all consistently defined, and reduces the occasional bugs caused by inconsistent definition of the register addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-27m68knommu: make ColdFire IMR and IPR register definitions absolute addressesGreg Ungerer
Make all definitions of the ColdFire Interrupt Mask and Pending registers absolute addresses. Currently some are relative to the MBAR peripheral region. The various ColdFire parts use different methods to address the internal registers, some are absolute, some are relative to peripheral regions which can be mapped at different address ranges (such as the MBAR and IPSBAR registers). We don't want to deal with this in the code when we are accessing these registers, so make all register definitions the absolute address - factoring out whether it is an offset into a peripheral region. This makes them all consistently defined, and reduces the occasional bugs caused by inconsistent definition of the register addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-27m68knommu: use "r", not "i" constraint in cacheflush asm'sPhilippe De Muyter
Let the compiler choose which register to use in the cache flushing asm statements, instead of imposing %d0. Additionally, fix two typo's. Signed-off-by: Philippe De Muyter <phdm@macqel.be> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-27m68k: drop unused parts of 68VZ328 MakefilePaul Bolle
DRAGEN2 should obviously be CONFIG_DRAGEN2, but the screen.h entry it triggers only references files that are nowhere to be found in the current tree. Besides, nothing uses screen.h. So just drop all that. Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-09-27powerpc/fsl-pci: use 'Header Type' to identify PCIE modeMinghuan Lian
The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, some latest silicons do not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so change code to use 'Header Type' field to judge PCIE mode. Because FSL PCI controller does not support 'Header Type', patch still uses 'Programming Interface' to identify PCI mode. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-09-27ARM: ux500: tidy up pin sleep modesLinus Walleij
This named the sleep mode pin configurations as *slpm* rather than *sleep* to correspond better with the settings from the datasheet. It also defines an optional sleep mode for the SPI controller SPI2. Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-09-27arm64: ptrace: remove obsolete ptrace request numbers from user headersWill Deacon
The use of regsets has removed the need for many private ptrace requests, so remove the corresponding definitions from the user-visible ptrace.h Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2012-09-27dw_dmac: autoconfigure data_width or get it via platform dataAndy Shevchenko
Not all of the controllers support the 64 bit data width. Make it configurable via platform data. The driver will try to get a value from the component parameters, otherwise it will use the platform data. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
2012-09-27dw_dmac: autoconfigure block_size or use platform dataAndy Shevchenko
The maximum block size is a configurable parameter for the chip. So, driver will try to get it from the encoded component parameters. Otherwise it will come from the platform data. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
2012-09-27sparc64: Fix return value of Niagara-2 memcpy.David S. Miller
It gets clobbered by the kernel's VISEntryHalf, so we have to save it in a different register than the set clobbered by that macro. The instance in glibc is OK and doesn't have this problem. Signed-off-by: David S. Miller <davem@davemloft.net>
2012-09-27crypto: cast5/avx - fix storing of new IV in CBC encryptionJussi Kivilinna
cast5/avx incorrectly XORs new IV over old IV at end of CBC encryption function when it should store. This causes CBC encryption to give incorrect output on multi-page encryption requests. Signed-off-by: Jussi Kivilinna <jussi.kivilinna@mbnet.fi> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2012-09-27sparc64: Add SPARC-T4 optimized memcpy.David S. Miller
Before After -------------- -------------- bw_tcp: 1288.53 MB/sec 1637.77 MB/sec bw_pipe: 1517.18 MB/sec 2107.61 MB/sec bw_unix: 1838.38 MB/sec 2640.91 MB/sec make -s -j128 allmodconfig 5min 49sec 5min 31sec Signed-off-by: David S. Miller <davem@davemloft.net>
2012-09-27perf/x86: Fix typo in uncore_pmu_to_boxYan, Zheng
The variable box should not be declared as static. This could probably cause crashes with sufficiently parallel uncore PMU use. Signed-off-by: Yan, Zheng <zheng.z.yan@intel.com> Cc: eranian@google.com Cc: a.p.zijlstra@chello.nl Link: http://lkml.kernel.org/r/1348709606-2759-1-git-send-email-zheng.z.yan@intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
2012-09-27powerpc/eeh: Don't release eeh_mutex in eeh_phb_pe_getAneesh Kumar K.V
Acked-by: Gavin Shan <shangw@linux.vnet.ibm.com> ===================================== [ BUG: bad unlock balance detected! ] 3.6.0-rc5-00338-gcaa1d63-dirty #6 Not tainted ------------------------------------- swapper/0/1 is trying to release lock (eeh_mutex) at: [<c000000000058218>] .eeh_add_to_parent_pe+0x318/0x410 but there are no more locks to release! other info that might help us debug this: no locks held by swapper/0/1. stack backtrace: Call Trace: [c00000003e483870] [c000000000013310] .show_stack+0x70/0x1c0 (unreliable) [c00000003e483920] [c0000000000d8310] .print_unlock_inbalance_bug+0x110/0x120 [c00000003e4839b0] [c0000000000d9a50] .lock_release+0x1d0/0x240 [c00000003e483a60] [c000000000778064] .__mutex_unlock_slowpath+0xb4/0x250 [c00000003e483b10] [c000000000058218] .eeh_add_to_parent_pe+0x318/0x410 [c00000003e483bc0] [c00000000005a118] .pseries_eeh_of_probe+0x258/0x2f0 [c00000003e483cc0] [c000000000032528] .traverse_pci_devices+0xa8/0x150 [c00000003e483d70] [c000000000aa7288] .eeh_init+0xd4/0x140 [c00000003e483e00] [c00000000000abc4] .do_one_initcall+0x64/0x1e0 [c00000003e483ec0] [c000000000a90418] .kernel_init+0x1e8/0x2bc [c00000003e483f90] [c00000000002048c] .kernel_thread+0x54/0x70 EEH: PCI Enhanced I/O Error Handling Enabled Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-09-27powerpc: Remove tlb batching hack for nighthawkMichael Ellerman
In hpte_init_native() we call tlb_batching_enabled() to decide if we should setup ppc_md.flush_hash_range. tlb_batching_enabled() checks the _unflattened_ device tree, to see if we are running on a nighthawk. Since commit a223535 ("dont allow pSeries_probe to succeed without initialising MMU", Dec 2006), hpte_init_native() has been called from pSeries_probe() - at which point we have not yet unflattened the device tree. This means tlb_batching_enabled() will always return true, so the hack has effectively been disabled since Dec 2006. Ergo, I think we can drop it. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-09-27powerpc: Set paca->data_offset = 0 for boot cpuMichael Ellerman
In commit 407821a we assigned a poison value to the paca->data_offset. Unfortunately with CONFIG_LOCK_STAT=y lockdep will read & write to percpu data very early in boot, prior to us initialising the percpu areas, leading to a crash. We have been getting away with this because the data_offset was previously set to zero. This causes lockdep to read & write to the initial copy of the percpu variables, which are discarded later in boot. Although that is "fishy", it does work, and for lock statistics it is no big deal to discard the counts from early boot. So set the paca->data_offset = 0 for the boot cpu paca only. Reported-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Tested-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-09-27powerpc/perf: Sample only if SIAR-Valid bit is set in P7+sukadev@linux.vnet.ibm.com
powerpc/perf: Sample only if SIAR-Valid bit is set in P7+ On POWER7+ two new bits (mmcra[35] and mmcra[36]) indicate whether the contents of SIAR and SDAR are valid. For marked instructions on P7+, we must save the contents of SIAR and SDAR registers only if these new bits are set. This code/check for the SIAR-Valid bit is specific to P7+, so rather than waste a CPU-feature bit use the PVR flag. Note that Carl Love proposed a similar change for oprofile: https://lkml.org/lkml/2012/6/22/309 Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-09-27Merge remote-tracking branch 'kumar/next' into nextBenjamin Herrenschmidt
A few more fsl updates from Kumar
2012-09-27Merge remote-tracking branch 'agust/next' into nextBenjamin Herrenschmidt
mpc5xxx updates from Anatolij
2012-09-26hypfs: ->d_parent is never NULL or negativeAl Viro
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2012-09-26switch simple cases of fget_light to fdgetAl Viro
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2012-09-26make get_file() return its argumentAl Viro
simplifies a bunch of callers... Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2012-09-26switch hpux_getdents() to fget_light()Al Viro
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2012-09-26switch itanic perfmonctl(2) to fget_light()Al Viro
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2012-09-26switch osf_getdirentries() to fget_light()Al Viro
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2012-09-26switch spufs/coredump to iterate_fd()Al Viro
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2012-09-26um: resurrect the right variant of mconsole_proc()Al Viro
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2012-09-26ARM: Orion5x: Fix too small coherent pool.Andrew Lunn
Some Orion5x devices allocate their coherent buffers from atomic context. Increase size of atomic coherent pool to make sure such the allocations won't fail during boot. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Olof Johansson <olof@lixom.net>
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