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2012-12-06KVM: PPC: Book3S HV: Restructure HPT entry creation codePaul Mackerras
This restructures the code that creates HPT (hashed page table) entries so that it can be called in situations where we don't have a struct vcpu pointer, only a struct kvm pointer. It also fixes a bug where kvmppc_map_vrma() would corrupt the guest R4 value. Most of the work of kvmppc_virtmode_h_enter is now done by a new function, kvmppc_virtmode_do_h_enter, which itself calls another new function, kvmppc_do_h_enter, which contains most of the old kvmppc_h_enter. The new kvmppc_do_h_enter takes explicit arguments for the place to return the HPTE index, the Linux page tables to use, and whether it is being called in real mode, thus removing the need for it to have the vcpu as an argument. Currently kvmppc_map_vrma creates the VRMA (virtual real mode area) HPTEs by calling kvmppc_virtmode_h_enter, which is designed primarily to handle H_ENTER hcalls from the guest that need to pin a page of memory. Since H_ENTER returns the index of the created HPTE in R4, kvmppc_virtmode_h_enter updates the guest R4, corrupting the guest R4 in the case when it gets called from kvmppc_map_vrma on the first VCPU_RUN ioctl. With this, kvmppc_map_vrma instead calls kvmppc_virtmode_do_h_enter with the address of a dummy word as the place to store the HPTE index, thus avoiding corrupting the guest R4. Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-06KVM: PPC: Support eventfdAlexander Graf
In order to support the generic eventfd infrastructure on PPC, we need to call into the generic KVM in-kernel device mmio code. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-05x86: Use PCI setup dataMatthew Garrett
EFI can provide PCI ROMs out of band via boot services, which may not be available after boot. Add support for using the data handed off to us by the boot stub or bootloader. [bhelgaas: added Seth's boot_params section mismatch fix] [bhelgaas: drop "boot_params.hdr.version < 0x0209" test] Signed-off-by: Matthew Garrett <mjg@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Tested-by: Seth Forshee <seth.forshee@canonical.com>
2012-12-05EFI: Stash ROMs if they're not in the PCI BARMatthew Garrett
EFI provides support for providing PCI ROMs via means other than the ROM BAR. This support vanishes after we've exited boot services, so add support for stashing copies of the ROMs in setup_data if they're not otherwise available. Signed-off-by: Matthew Garrett <mjg@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Tested-by: Seth Forshee <seth.forshee@canonical.com>
2012-12-05MIPS: Fix endless loop when processing signals for kernel tasksDmitry Adamushko
The problem occurs [1] when a kernel-mode task returns from a system call with a pending signal. A real-life scenario is a child of 'khelper' returning from a failed kernel_execve() in ____call_usermodehelper() [ kernel/kmod.c ]. kernel_execve() fails due to a pending SIGKILL, which is the result of "kill -9 -1" (at least, busybox's init does it upon reboot). The loop is as follows: * syscall_exit_work: - work_pending: // start_of_the_loop - work_notifysig: - do_notify_resume() - do_signal() - if (!user_mode(regs)) return; - resume_userspace // TIF_SIGPENDING is still set - work_pending // so we call work_pending => goto // start_of_the_loop More information can be found in another LKML thread: http://www.serverphorums.com/read.php?12,457826 [1] The problem was also reproduced on !CONFIG_VM86 x86, and the following fix was accepted. http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=29a2e2836ff9ea65a603c89df217f4198973a74f Signed-off-by: Dmitry Adamushko <dmitry.adamushko@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3571/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-12-05MIPS: R3000/R3081: Fix CPU detection.Ralf Baechle
Broken since e05ea74fc56f347f872ef9946d27c53e8bf20864 (lmo) rsp. cea7e2dfdef53fe55f359d00da562a268be06fd2 (kernel.org) [MIPS: Sort out CPU type to name translation.] These CPUs are no longer very popular to say the least ... Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Reported-by: Murphy McCauley <murphy.mccauley@gmail.com>
2012-12-05MIPS: N32: Fix signalfd4 syscall entry pointRalf Baechle
This needs to use the compat entry point or it's going to fail on big endian systems. Noticed by Al Viro. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-12-05s390/pci: enable NEED_DMA_MAP_STATEJan Glauber
The DMA API allows to avoid DMA unmaps because they are NOPs on some plattforms. But not on s390, so force them. Signed-off-by: Jan Glauber <jang@linux.vnet.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2012-12-05KVM: x86: Make register state after reset conform to specificationJulian Stecklina
VMX behaves now as SVM wrt to FPU initialization. Code has been moved to generic code path. General-purpose registers are now cleared on reset and INIT. SVM code properly initializes EDX. Signed-off-by: Julian Stecklina <jsteckli@os.inf.tu-dresden.de> Signed-off-by: Gleb Natapov <gleb@redhat.com>
2012-12-05kvm: don't use bit24 for detecting address-specific invalidation capabilityZhang Xiantao
Bit24 in VMX_EPT_VPID_CAP_MASI is not used for address-specific invalidation capability reporting, so remove it from KVM to avoid conflicts in future. Signed-off-by: Zhang Xiantao <xiantao.zhang@intel.com> Signed-off-by: Gleb Natapov <gleb@redhat.com>
2012-12-05kvm: remove unnecessary bit checking for ept violationZhang Xiantao
Bit 6 in EPT vmexit's exit qualification is not defined in SDM, so remove it. Signed-off-by: Zhang Xiantao <xiantao.zhang@intel.com> Signed-off-by: Gleb Natapov <gleb@redhat.com>
2012-12-05s390/pci: no msleep in potential IRQ contextJan Glauber
The PCI instructions may be used in IRQ context so scheduling is forbidden. Use udelay and shorten the delay since we are now polling. Signed-off-by: Jan Glauber <jang@linux.vnet.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2012-12-05arm64: compat for clock_adjtime(2) is miswiredAl Viro
struct timex is different on arm and arm64; adjtimex(2) takes care to convert, clock_adjtime(2) doesn't... Signed-off-by: Al Viro <viro@ZenIV.linux.org.uk> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Cc: <stable@vger.kernel.org>
2012-12-05arm64: move FP-SIMD save/restore code to a macroMarc Zyngier
In order to be able to reuse the save-restore code in KVM, move it to a pair of macros, similar to what the 32bit code does. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2012-12-05arm64: hyp: initialize vttbr_el2 to zeroMarc Zyngier
The architecture doesn't mandate any reset value for vttbr_el2. Better set it to a known value before some HYP code gets confused. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2012-12-05arm64: add hypervisor stubMarc Zyngier
If booted in EL2, install an dummy hypervisor whose only purpose is to be replaced by a full fledged one. A minimal API allows to: - obtain the current HYP vectors (__hyp_get_vectors) - set new HYP vectors (__hyp_set_vectors) Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2012-12-05arm64: record boot mode when entering the kernelMarc Zyngier
To be able to signal the availability of EL2 to other parts of the kernel, record the boot mode. Once booted, two predicates indicate if HYP mode is available, and if not, whether this is due to a boot mode mismatch or not. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2012-12-05arm64: move vector entry macro to assembler.hMarc Zyngier
This macro is also useful to other bits defining vectors (hypervisor stub, KVM...). Move it to a common location. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2012-12-05arm64: add AArch32 execution modes to ptrace.hMarc Zyngier
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2012-12-05arm64: expand register mapping between AArch32 and AArch64Marc Zyngier
The general purpose registers in AArch32 are mapped in an architecturally defined manner into the AArch64 registers. It allows the AArch32 registers of an application or a virtual machine to be inspected by the OS or an hypervisor. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2012-12-05arm64: generic timer: use virtual counter instead of physical at EL0Will Deacon
We want to use the virtual counter at EL0, as the physical counter may not track the current clocksource for guests running under a hypervisor. This patch updates the vdso and generic timer driver to use the virtual counter. The kernel EL2 entry code is also updated to ensure that the virtual offset is initialised to zero. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2012-12-05arm64: vdso: defer shifting of nanosecond component of timespecWill Deacon
Shifting the nanosecond component of the computed timespec early can lead to sub-ns inaccuracies when using the truncated value as input to further arithmetic for things like conversions to monotonic time. This patch defers the timespec shifting until after the final value has been computed. Reported-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2012-12-05arm64: vdso: rework __do_get_tspec register allocation and return shiftWill Deacon
In preparation for sub-ns precision in the vdso timespec maths, change the __do_get_tspec register allocation so that we return the clocksource shift value instead of the unused xtime tspec. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2012-12-05arm64: vdso: check sequence counter even for coarse realtime operationsWill Deacon
When returning coarse realtime values from clock_gettime, we must still check the sequence counter to ensure that the kernel does not update the vdso datapage whilst we are loading the coarse timespec as this could potentially result in time appearing to go backwards. This patch delays the coarse realtime check until after we have loaded successfully from the vdso datapage. This does mean that we always load the wtm timespec, but conditionalising the load and adding an extra sequence test is unlikely to buy us anything other than messy code, particularly as the sequence test implies a read barrier. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2012-12-05arm64: vdso: fix clocksource mask when extracting bottom 56 bitsWill Deacon
The generic timer clocksource has 56 bits of precision and as such must be masked appropriately after we have read it. The current mask generated by a movn instruction is off by 4 bits, so we accidentally include the top 4 bits in the final value. This patch fixes the broken mask. Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2012-12-05m68knommu: modify clock code so it can be used by all ColdFire CPU typesGreg Ungerer
The existing clk.c code for ColdFire CPUs has one set of functions to support those CPU types that have selectable clocks (those with a PPMCR register), and a duplicate simpler set for those with static clocks. Modify the clk.c code so there is just one set of support functions. All CPU types now define a list of clocks (in "struct clk"s), so we only need a single set of clock functions. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-12-05m68knommu: add clock definitions for 54xx ColdFire CPU typesGreg Ungerer
Add a base set of clocks for the 54xx ColdFire CPU types. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-12-05m68knommu: add clock definitions for 5407 ColdFire CPU typesGreg Ungerer
Add a base set of clocks for the 5407 ColdFire CPU types. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-12-05m68knommu: add clock definitions for 5307 ColdFire CPU typesGreg Ungerer
Add a base set of clocks for the 5307 ColdFire CPU types. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-12-05m68knommu: add clock definitions for 528x ColdFire CPU typesGreg Ungerer
Add a base set of clocks for the 528x ColdFire CPU types. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-12-05m68knommu: add clock definitions for 527x ColdFire CPU typesGreg Ungerer
Add a base set of clocks for the 527x ColdFire CPU types. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-12-05m68knommu: add clock definitions for 5272 ColdFire CPU typesGreg Ungerer
Add a base set of clocks for the 5272 ColdFire CPU types. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-12-05m68knommu: add clock definitions for 525x ColdFire CPU typesGreg Ungerer
Add a base set of clocks for the 525x ColdFire CPU types. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-12-05m68knommu: add clock definitions for 5249 ColdFire CPU typesGreg Ungerer
Add a base set of clocks for the 5249 ColdFire CPU types. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-12-05m68knommu: add clock definitions for 523x ColdFire CPU typesGreg Ungerer
Add a base set of clocks for the 523x ColdFire CPU types. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-12-05m68knommu: add clock definitions for 5206 ColdFire CPU typesGreg Ungerer
Add a base set of clocks for the 5206 ColdFire CPU types. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-12-05m68knommu: add clock creation support macro for other ColdFire CPUsGreg Ungerer
The clock support code for ColdFire CPUs currently supports those that have the clock control register PPMCR. Expose the struct clk for all CPU types and add a definition for all other ColdFire CPU types. With this we will be able to define simple clock trees for all ColdFire CPU types, even though they will not be able to be enabled or disabled. They will be able to report the clock rate. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-12-05m68k: fix unused variable warning in mempcy.cGreg Ungerer
When compiling for original 68000 or ColdFire targets you will get the following warning when compiling arch/m68k/lib/memcpy.c: CC arch/m68k/lib/memcpy.o arch/m68k/lib/memcpy.c: In function ‘__builtin_memcpy’: arch/m68k/lib/memcpy.c:13:15: warning: unused variable ‘temp1’ This is easily fixed by moving the definition of temp1 into the code block where it is used. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-12-05m68knommu: make non-MMU page_to_virt() return a void *Greg Ungerer
The page_to_virt() macro for m68knommu is currently effectively returning an int type. But the equivilent m68k macro returns a void * virtual address. Modify the non-MMU macro to return a void * as well (using the __va macro). This change will remove compiler warnings in common m68k code that use this macro. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-12-05m68knommu: merge ColdFire 5249 and 525x definitionsGreg Ungerer
The ColdFire 5249 and 525x family of SoCs are very similar. Most of the internals are the same, and are mapped the same. We can use a single set of peripheral definitions for all of them. So merge the current m5249sim.h and m525xsim.h definitions into a single file. The 5249 is now obsolete, and the 525x parts are current, so I have chosen to move everything into the existing m525xsim.h file. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-12-05m68knommu: disable MC68000 cpu target when MMU is selectedLuis Alves
As pointed out by Geert, MC68000 target needs to be disabled when MMU support is enabled. From Geert: This needs a "depends on !MMU". Else allmodconfig will select it, causing -m68000 to be passed to the assembler, which may break the build depending on your version of binutils, a.o. arch/m68k/kernel/entry.S:186: Error: invalid instruction for this architecture; needs 68020 or higher (68020 [68k, 68ec020], 68030 [68ec030], 68040 [68ec040], 68060 [68ec060]) -- statement `bfextu %sp@(50){#0,#4},%d0' ignored arch/m68k/kernel/entry.S:211: Error: invalid operand mode for this architecture; needs 68020 or higher -- statement `jbsr @(sys_call_table,%d0:l:4)@(0)' ignored Cfr. http://kisskb.ellerman.id.au/kisskb/buildresult/7416877/ Signed-off-by: Luis Alves <ljalvs@gmail.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-12-05m68knommu: allow for configuration of true 68000 based systemsLuis Alves
Allow the M68000 option to be user configurable, for systems based on the original stand alone 68000 CPU. Signed-off-by: Luis Alves <ljalvs@gmail.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-12-05m68knommu: platform code merge for 68000 core cpusLuis Alves
This patch merges all 68000 core cpus into one directory. There is a lot of common code in the 68328, 68EZ328 and 68VZ328 directories. This will also facilitate easy development of support for original stand alone MC68000 CPU machines. Signed-off-by: Luis Alves <ljalvs@gmail.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
2012-12-04MIPS: N32: Fix preadv(2) and pwritev(2) entry points.Ralf Baechle
By using the native syscall entry point the kernel was also expecting 64-bit iovec structures. This is broken since ddd9e91b71072b8ebe89311c3a44b077defa1756 [preadv/ pwritev: MIPS: Add preadv(2) and pwritev(2) syscalls.] which originally added these two syscalls. I walked through piles of code, including libc and couldn't find anything that would have worked around the issue so this change the API to what it should always have been. Noticed and patch suggested by Al Viro. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-12-04Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparcLinus Torvalds
Pull sparc fixes from David Miller: "Two small fixes for Sparc, nobody uses sparc, so these are low risk :-) 1) Piggyback is too picky about the symbol types that _start and _end have in the final kernel image, and it thus breaks with newer binutils. Future proof by getting rid of the symbol type checks. 2) exit_group() should kill register windows on sparc64 the same way we do for plain exit(). Thanks to Al Viro for spotting this." * git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc: sparc: Fix piggyback with newer binutils. sparc64: exit_group should kill register windows just like plain exit.
2012-12-04Merge remote-tracking branch 'robherring/for-next' into devicetree/nextGrant Likely
2012-12-04MIPS: Avoid mcheck by flushing page range in huge_ptep_set_access_flags()David Daney
Problem: 1) Huge page mapping of anonymous memory is initially invalid. Will be faulted in by copy-on-write mechanism. 2) Userspace attempts store at the end of the huge mapping. 3) TLB Refill exception handler fill TLB with a normal (4K sized) invalid page at the end of the huge mapping virtual address range. 4) Userspace restarted, and re-attempts the store at the end of the huge mapping. 5) Page from #3 is invalid, we get a fault and go to the hugepage fault handler. This tries to map a huge page and calls huge_ptep_set_access_flags() to install the mapping. 6) We just call the generic ptep_set_access_flags() to set up the page tables, but the flush there assumes a normal (4K sized) page and only tries to flush the first part of the huge page virtual address out of the TLB, since the existing entry from step #3 doesn't conflict, nothing is flushed. 7) We attempt to load the mapping into the TLB, but because it conflicts with the entry from step #3, we get a Machine Check exception. The fix: Flush the entire rage covered by the huge page in huge_ptep_set_access_flags(), and remove the optimization in local_flush_tlb_range() so that the flush actually does the correct thing. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: Hillf Danton <dhillf@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/4661/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit dd617f258cc39d36be26afee9912624a2d23112c)
2012-12-03microblaze: use new common dtc ruleStephen Warren
The current rules have the .dtb files build in a different directory from the .dts files. This patch changes microblaze to use the generic dtb rule which builds .dtb files in the same directory as the source .dts. This requires moving parts of arch/microblaze/boot/Makefile into newly created arch/microblaze/boot/dts/Makefile, and updating arch/microblaze/Makefile to call the new Makefile. linked_dtb.S is also moved into boot/dts/ since it's used by rules that were moved. Cc: Michal Simek <monstr@monstr.eu> Cc: microblaze-uclinux@itee.uq.edu.au Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2012-12-03c6x: use new common dtc ruleStephen Warren
The current rules have the .dtb files build in a different directory from the .dts files. This patch changes c6x to use the generic dtb rule which builds .dtb files in the same directory as the source .dts. This requires moving parts of arch/c6x/boot/Makefile into newly created arch/c6x/boot/dts/Makefile, and updating arch/c6x/Makefile to call the new Makefile. linked_dtb.S is also moved into boot/dts/ since it's used by rules that were moved. Acked-by: Mark Salter <msalter@redhat.com> Cc: Aurelien Jacquiot <a-jacquiot@ti.com> Cc: linux-c6x-dev@linux-c6x.org Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2012-12-03openrisc: use new common dtc ruleStephen Warren
The current rules have the .dtb files build in a different directory from the .dts files. This patch changes openrisc to use the generic dtb rule which builds .dtb files in the same directory as the source .dts. This requires renaming arch/openrisc/boot/Makefile to arch/openrisc/boot/dts/Makefile, and updating arch/openrisc/Makefile to call the new Makefile. Cc: Jonas Bonn <jonas@southpole.se> Cc: linux@lists.openrisc.net Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Rob Herring <rob.herring@calxeda.com>