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This patch activates every USB port provided by each SoC.
Except for Armada XP Openblocks AX3-4 board,
where we enable only the first two USB ports
until we have more information on the third one usage.
Cc: Lior Amsalem <alior@marvell.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Tested-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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The Armada 370 and Armada XP SoC has an Orion EHCI USB controller.
This patch adds support for this controller in Armada 370
and Armada XP SoC common device tree files.
Cc: Lior Amsalem <alior@marvell.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Tested-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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The OpenBlocks AX3-4 board has one software-controlled button on the
front side, labeled "INIT", so we add minimal support for this button
in the kernel.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Remove C code and add a Device Tree node in its place.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Simon Guinot <simon.guinot@sequanux.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Add a sub-node into the I2C node to represent the adt7476 device.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Remove the C code and add a Device Tree node for gpio-poweroff.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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CuBox needs to enable USB power on a gpio pin. Add a fixed regulator
to always enable usb power on boot.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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gpio-leds has support for pinctrl allocation, make use of it.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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The 88f6282 has one more TWSI(TWSI1). This add the information to enable
pinctl of TWSI1.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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This commit adds a pinmux option, pmx_sdio, to enable the muxing of
the SDIO interface on the 88F6282 SoC from Marvell.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Now that the mvsdio driver has a Device Tree binding, and the SDIO
controller is declared in kirkwood.dtsi, migrate the mplcec4 board to
use the Device Tree to probe the SDIO controller and to mux the pins
of the SDIO interface correctly.
This patch has not been tested, it remains to be tested by a person
having access to the hardware.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Stefan Peter <s.peter@mpl.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Now that the mvsdio driver has a Device Tree binding, and the SDIO
controller is declared in kirkwood.dtsi, migrate the dreamplug board
to use the Device Tree to probe the SDIO controller and to mux this
interface properly.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Now that the SDIO controller has a Device Tree binding, let's use it
in kirkwood.dtsi.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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The Globalscale Mirabox uses the SDIO interface of the Armada 370 to
connect to a Wifi/Bluetooth SD8787 chip, so we enable the SDIO
interface of this board in its Device Tree file.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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The Armada XP DB evaluation board has one SD card slot, directly
connected to the SDIO IP of the SoC, so we add a device tree
description for it.
However, in the default configuration of the board, the SD card slot
is not usable: the connector plugged into CON40 must be changed
against a different one, provided with the board by the
manufacturer. Since such a manual modification of the hardware is
needed, we did not enable the SDIO interface by default, and left it
to the board user to modify the Device Tree if needed. Since this
board is really only an evaluation board for developers and not a
final product, it is not too bad.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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The Armada XP DB evaluation board has one SD card slot, directly
connected to the SDIO IP of the SoC, so we enable this
IP. Unfortunately, there are no GPIOs for card-detect and
write-protect.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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The SDIO interface is only available on pins MPP30/31/32/33/34/35 on
the various Armada XP variants, so we provide a pin muxing option for
this in the Armada XP .dtsi files.
Even though those muxing options are the same for MV78230, MV78260 and
MV78460, we keep them in each .dtsi file, because the number of pins,
and therefore the declaration of the pinctrl node, is different for
each SoC variant.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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The SDIO interface is available either on pins MPP9/11/12/13/14/15 or
MPP47/48/49/50/51/52 on the Armada 370. Even though all combinations
are potentially possible, those two muxing options are the most
probable ones, so we provide those at the SoC level .dtsi file.
In practice, in turns out the Armada 370 DB board uses the former,
while the Armada 370 Mirabox uses the latter.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Now that the mvsdio MMC driver has a Device Tree binding, we add the
Device Tree informations to describe the SDIO interface available in
the Armada 370/XP SoCs.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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The Armada 370 and Armada XP Socs have the same controller that the
one used in the orion platforms. This patch updates the device tree
for these SoCs.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Florian Fainelli <florian@openwrt.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Some of the mvebu boards (mainly the development board) come with
plug-in RAM modules. This patch allows to let the bootloaders which
have no support for DTS to give the real amount of memory available on
the board.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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The Armada XP DB-MV784MP-GP board has an SPI flash device.
These options allow to access that device over MTD.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Lior Amsalem <alior@marvell.com>
Acked-by: Gregory Clement <gregory.clement@free-electrons.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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This is the new Armada XP evaluation board from Marvell. It comes with
a RS232 port over USB, a SATA link, an internal SSD, 4 Ethernet
Gigabit links.
Support for USB (Host and device), SDIO, PCIe will be added as drivers
when they become available for Armada XP in mainline.
Tested-by: Simon Guinot <simon.guinot@sequanux.org>
Tested-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Now that we have support for local timers, enable it by default
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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MPIC allows the use of private interrupt for each CPUs. The 28th first
interrupts are per-cpu. This patch adds support to use them.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Cc: Lior Amsalem <alior@marvell.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Tested-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Add a device tree entry for the Guruplug Server Plus board. This port
was based both on the work done on the dreamplug and the dockstar.
It builds, boots and works on my Guruplug Server Plus.
Signed-off-by: Willy Tarreau <w@1wt.eu>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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This patch adds the DTS file to support the Marvell RD-A370-A1
(Reference Design board) also known as RD-88F6710 board. It is almost
entirely similar to the DB-A370 board except that the first Ethernet PHY
is SGMII-wired and the second is a switch which is RGMII-wired.
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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This patch makes the interrupt controller driver more SMP aware for
the Armada XP SoCs. It adds the support for the per-CPU irq. It also
adds the implementation for the set_affinity hook.
Patch initialy wrote by Yehuda Yitschak and reworked by Gregory
CLEMENT.
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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In the beginning of DT for Dove it was reasonable to have it close to
non-DT code. With improved DT support, it became more and more difficult
to not break non-DT while changing DT code.
This patch splits up DT board setup and introduces a DOVE_LEGACY config
to allow to remove legacy code for DT-only kernels.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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This refreshes the dove_defconfig, and adds:
PRINTK_TIME
DEVTMPFS
EXT4
They're quite useful, and allows booting a cubox ubuntu rootfs on SD card,
since that by default uses ext4.
The rest of the churn is due to options and defaults moving around, no
functional difference.
Signed-off-by: Olof Johansson <olof@lixom.net>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Now that SDIO is instantiated via DT, and the SDIO DT node has a clocks
property, we no longer need a C coded clock alias. Remove it.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Now that USB is instantiated via DT, and the USB DT node has a clocks
property, we no longer need a C coded clock alias. Remove it.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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The OpenBlocks AX3-4 platform has several LEDs, so it sounds wise to
enable LED support in mvebu_defconfig. We anticipate that more
platforms using Marvell EBU SoCs will have LEDs in the future.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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The Globalscale Mirabox platform, based on the Armada 370 from
Marvell, has a SD8787 Wireless/Bluetooth chip connected on the SDIO
interface. Now that the mvsdio has a Device Tree binding, and the
necessary Device Tree informations have been added at the SoC and
board level, let's enable the btmrvl driver for the Bluetooth part of
the SD8787 chip.
For now, the driver gets probed correctly, detects the device but
apparently fails to push the firmware to the device:
Bluetooth: vendor=0x2df, device=0x911a, class=255, fn=2
Bluetooth: FW failed to be active in time!
Bluetooth: Downloading firmware failed!
Bluetooth: vendor=0x2df, device=0x911b, class=255, fn=3
Bluetooth: FW failed to be active in time!
Bluetooth: Downloading firmware failed!
This will have to be investigated separately.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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The Globalscale Mirabox platform, based on the Armada 370 from
Marvell, has a SD8787 Wireless chip connected on the SDIO
interface. Now that the mvsdio has a Device Tree binding, and the
necessary Device Tree informations have been added at the SoC and
board level, let's enable the mwifiex driver for the Wireless part of
the SD8787 chip.
For now, the driver gets probed correctly, detects a device and shows
the network interfaces. However, scanning Wifi networks doesn't work
for now, with a 'CMD_RESP: cmd 0x6 error, result=0x1' message. This
will have to be investigated separately.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Now that the mvsdio driver has gained Device Tree support and the
necessary Device Tree informations has been added for Armada 370 and
Armada XP platforms, we enable the MMC subsystem and the mvsdio driver
in mvebu_defconfig.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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The RTC class driver is already part of the mvebu_defconfig but the
Marvell internal RTC not yet. Now that its support is added for mvebu
let's update the config file.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Florian Fainelli <florian@openwrt.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Basing the mvebu patches on top of the timer cleanup
avoids some nasty merges.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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These patches from the mmc tree were merged into v3.9 already
and the later mvebu patches depend on them.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Pull MIPS updates from Ralf Baechle:
"A number of fixes all across the MIPS tree. No area is particularly
standing out and things have cooled down quite nicely for a release."
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
MIPS: Function tracer: Fix broken function tracing
mips: Move __virt_addr_valid() to a place for MIPS 64
MIPS: Netlogic: Fix UP compilation on XLR
MIPS: AR71xx: Fix AR71XX_PCI_MEM_SIZE
MIPS: AR724x: Fix AR724X_PCI_MEM_SIZE
MIPS: Lantiq: Fix cp0_perfcount_irq mapping
MIPS: DSP: Fix DSP mask for registers.
MIPS: Fix build failure by adding definition of pfn_pmd().
MIPS: Octeon: Fix warning.
MIPS: delay.c: Check BITS_PER_LONG instead of __SIZEOF_LONG__
MIPS: PNX833x: Fix comment.
MIPS: Add struct p_format to union mips_instruction.
MIPS: Export <asm/break.h>.
MIPS: BCM47xx: Enable SSB prerequisite SSB_DRIVER_PCICORE.
MIPS: BCM47xx: Select GPIOLIB for BCMA on bcm47xx platform
MIPS: vpe.c: Fix null pointer dereference in print arguments.
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mvebu drivers for v3.9
- use rtc-mv in mvebu armv7 SoCs
- add pci-e hotplug for kirkwood
Depends on:
- tags/mvebu_fixes_for_v3.8-rc6
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cleanup for v3.9 round2
- remove unneeded #includes for mach-dove
- remove unneeded #includes and code for the nsa310
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fixes for v3.8-rc6
- add missing gpio interrupt lines to dove dt
- fix bad logic for printing MPP error message on orion boards
- build proper serial port driver after changing mvebu DT compatible property
- This is a change to mvebu_defconfig that I wouldn't usually push out as a
fix. However, the commit
b24212f arm: mvebu: Use dw-apb-uart instead of ns16650 as UART driver
changed the serial driver for the board in the dts file. without the patch
I've included in this pull, users won't see any log messages.
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Move the Kirkwood cpuidle driver out of arch/arm/mach-kirkwood and
into drivers/cpuidle. Convert the driver into a platform driver.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Function tracing is currently broken for all 32 bit MIPS platforms.
When tracing is enabled, the kernel immediately hangs on boot.
This is a result of commit b732d439cb43336cd6d7e804ecb2c81193ef63b0
that changes the kernel/trace/Kconfig file so that is no longer
forces FRAME_POINTER when FUNCTION_TRACING is enabled.
MIPS frame pointers are generally considered to be useless because
they cannot be used to unwind the stack. Unfortunately the MIPS
function tracing code has bugs that are masked by the use of frame
pointers. This commit fixes the bugs so that MIPS frame pointers
don't need to be enabled.
The bugs are a result of the odd calling sequence used to call the trace
routine. This calling sequence is inserted into every traceable function
when the tracing CONFIG option is enabled. This sequence is generated
for 32bit MIPS platforms by the compiler via the "-pg" flag.
Part of the sequence is "addiu sp,sp,-8" in the delay slot after every
call to the trace routine "_mcount" (some legacy thing where 2 arguments
used to be pushed on the stack). The _mcount routine is expected to
adjust the sp by +8 before returning. So when not disabled, the original
jalr and addiu will be there, so _mcount has to adjust sp.
The problem is that when tracing is disabled for a function, the
"jalr _mcount" instruction is replaced with a nop, but the
"addiu sp,sp,-8" is still executed and the stack pointer is left
trashed. When frame pointers are enabled the problem is masked
because any access to the stack is done through the frame
pointer and the stack pointer is restored from the frame pointer when
the function returns.
This patch writes two nops starting at the address of the "jalr _mcount"
instruction whenever tracing is disabled. This means that the
"addiu sp,sp.-8" will be converted to a nop along with the "jalr". When
disabled, there will be two nops.
This is SMP safe because the first time this happens is during
ftrace_init() which is before any other processor has been started.
Subsequent calls to enable/disable tracing when other CPUs ARE running
will still be safe because the enable will only change the first nop
to a "jalr" and the disable, while writing 2 nops, will only be changing
the "jalr". This patch also stops using stop_machine() to call the
tracer enable/disable routines and calls them directly because the
routines are SMP safe.
When the kernel first boots we have to be able to handle the gcc
generated jalr, addui sequence until ftrace_init gets a chance to run
and change the sequence. At this point mcount just adjusts the stack
and returns. When ftrace_init runs, we convert the jalr/addui to nops.
Then whenever tracing is enabled we convert the first nop to a "jalr
mcount+8". The mcount+8 entry point skips the stack adjust.
[ralf@linux-mips.org: Folded in Steven Rostedt's build fix.]
Signed-off-by: Al Cooper <alcooperx@gmail.com>
Cc: rostedt@goodmis.org
Cc: ddaney.cavm@gmail.com
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/4806/
Patchwork: https://patchwork.linux-mips.org/patch/4841/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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