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2010-10-21Merge branch 'x86-amd-nb-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'x86-amd-nb-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86, amd_nb: Enable GART support for AMD family 0x15 CPUs x86, amd: Use compute unit information to determine thread siblings x86, amd: Extract compute unit information for AMD CPUs x86, amd: Add support for CPUID topology extension of AMD CPUs x86, nmi: Support NMI watchdog on newer AMD CPU families x86, mtrr: Assume SYS_CFG[Tom2ForceMemTypeWB] exists on all future AMD CPUs x86, k8: Rename k8.[ch] to amd_nb.[ch] and CONFIG_K8_NB to CONFIG_AMD_NB x86, k8-gart: Decouple handling of garts and northbridges x86, cacheinfo: Fix dependency of AMD L3 CID x86, kvm: add new AMD SVM feature bits x86, cpu: Fix allowed CPUID bits for KVM guests x86, cpu: Update AMD CPUID feature bits x86, cpu: Fix renamed, not-yet-shipping AMD CPUID feature bit x86, AMD: Remove needless CPU family check (for L3 cache info) x86, tsc: Remove CPU frequency calibration on AMD
2010-10-13Merge branch 'amd-iommu/2.6.37' of ↵Ingo Molnar
git://git.kernel.org/pub/scm/linux/kernel/git/joro/linux-2.6-iommu into core/iommu
2010-09-20x86, k8: Rename k8.[ch] to amd_nb.[ch] and CONFIG_K8_NB to CONFIG_AMD_NBAndreas Herrmann
The file names are somehow misleading as the code is not specific to AMD K8 CPUs anymore. The files accomodate code for other AMD CPU northbridges as well. Same is true for the config option which is valid for AMD CPU northbridges in general and not specific to K8. Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com> LKML-Reference: <20100917160343.GD4958@loge.amd.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2010-09-17x86, k8-gart: Decouple handling of garts and northbridgesAndreas Herrmann
So far we only provide num_k8_northbridges. This is required in different areas (e.g. L3 cache index disable, GART). But not all AMD CPUs provide a GART. Thus it is useful to split off the GART handling from the generic caching of AMD northbridge misc devices. Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com> LKML-Reference: <20100917160254.GC4958@loge.amd.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2010-09-17drm/i915,agp/intel: Add second set of PCI-IDs for B43Chris Wilson
There is a second revision of B43 (a desktop gen4 part) floating around, functionally equivalent to the original B43, so simply add the new PCI-IDs. Bugzilla: https://bugs.freedesktop.org/show_bugs.cgi?id=30221 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
2010-09-07intel_agp,i915: Add more sandybridge graphics device idsZhenyu Wang
New pci ids for GT2 and GT2+ on desktop and mobile sandybridge, and graphics device ids for server sandybridge. Also rename original ids string to reflect GT1 version. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-07agp/intel: Fix cache control for SandybridgeZhenyu Wang
Sandybridge GTT has new cache control bits in PTE, which controls graphics page cache in LLC or LLC/MLC, so we need to extend the mask function to respect the new bits. And set cache control to always LLC only by default on Gen6. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-07agp/intel: use #ifdef idiom for intel-agp.hZhenyu Wang
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-07agp/intel: fix physical address mask bits for sandybridgeZhenyu Wang
It should shift bit 39-32 into pte's bit 11-4. Reported-by:Takashi Iwai <tiwai@suse.de> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-06agp/intel: Promote warning about failure to setup flush to error.Chris Wilson
Make sure we always detect when we fail to correctly allocate the Isoch Flush Page and print an error to warn the user about the likely memory corruption that will result in invalid rendering or worse. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
2010-09-05AGP: Warn when GATT memory cannot be set to UCBorislav Petkov
This is one of those paranoid checks which should at least tell us that something is about to go haywire after we've disabled GART table walk probes which is done by default now on AMD. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com> Cc: Dave Airlie <airlied@redhat.com> Cc: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> LKML-Reference: <1283531981-7495-4-git-send-email-bp@amd64.org> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-09-05x86, GART: Disable GART table walk probesBorislav Petkov
Current code tramples over bit F3x90[6] which can be used to disable GART table walk probes. However, this bit should be set for performance reasons (speed up GART table walks). We are allowed to do that since we put GART tables in UC memory later anyway. Make it so. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com> Cc: Dave Airlie <airlied@redhat.com> Cc: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> LKML-Reference: <1283531981-7495-3-git-send-email-bp@amd64.org> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-09-05x86, GART: Remove superfluous AMD64_GARTENBorislav Petkov
There is a GARTEN so use that and drop the duplicate. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com> Cc: Dave Airlie <airlied@redhat.com> Cc: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> LKML-Reference: <1283531981-7495-2-git-send-email-bp@amd64.org> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-08-21drm/i915,intel_agp: Add support for Sandybridge D0Zhenyu Wang
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-21agp/intel: set 40-bit dma mask on SandybridgeZhenyu Wang
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-05agp: intel-agp: do not use PCI resources before pci_enable_device()Kulikov Vasiliy
IRQ and resource[] may not have correct values until after PCI hotplug setup occurs at pci_enable_device() time. The semantic match that finds this problem is as follows: // <smpl> @@ identifier x; identifier request ~= "pci_request.*|pci_resource.*"; @@ ( * x->irq | * x->resource | * request(x, ...) ) ... *pci_enable_device(x) // </smpl> Signed-off-by: Kulikov Vasiliy <segooon@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-08-05agp: efficeon-agp: do not use PCI resources before pci_enable_device()Kulikov Vasiliy
IRQ and resource[] may not have correct values until after PCI hotplug setup occurs at pci_enable_device() time. The semantic match that finds this problem is as follows: // <smpl> @@ identifier x; identifier request ~= "pci_request.*|pci_resource.*"; @@ ( * x->irq | * x->resource | * request(x, ...) ) ... *pci_enable_device(x) // </smpl> Signed-off-by: Kulikov Vasiliy <segooon@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-08-01drm/agp/i915: trim stolen space to 32MJesse Barnes
Some BIOSes will claim a large chunk of stolen space. Unless we reclaim it, our aperture for remapping buffer objects will be constrained. So clamp the stolen space to 32M and ignore the rest. Fixes https://bugzilla.kernel.org/show_bug.cgi?id=15469 among others. Adding the ignored stolen memory back into the general pool using the memory hotplug code is left as an exercise for the reader. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Simon Farnsworth <simon.farnsworth@onelan.com> Tested-by: Artem S. Tashkinov <t.artem@mailcity.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-01agp/intel: Destroy the scatterlist on allocation failureChris Wilson
A side-effect of being able to use custom page allocations with the sg_table is that it cannot reap the partially constructed scatterlist if fails to allocate a page. So we need to call sg_free_table() ourselves if sg_alloc_table() fails. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc Dave Airlie <airlied@redhat.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-01Merge remote branch 'origin/master' into drm-intel-nextEric Anholt
This resolves the conflict in the EDP code, which has been rather popular to hack on recently. Conflicts: drivers/gpu/drm/i915/intel_dp.c
2010-08-01agp/intel: Add actual definitions of the Sandybridge PTE caching bits.Zhenyu Wang
2010-08-01agp/intel: Support the extended physical addressing bits on Sandybridge.Zhenyu Wang
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> [anholt: Split this patch out of a larger patch for Sandybridge fixes] Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-01intel_agp: Don't oops with zero stolen memoryOndrej Zary
When "onboard video memory" is set do "disabled" in BIOS on Asus P4P800-VM board (i865G), kernel oopses with memory corruption: https://bugs.freedesktop.org/show_bug.cgi?id=28430 Fix that by cleanly aborting the initialization. Signed-off-by: Ondrej Zary <linux@rainbow-software.org> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-07-26agp/intel: Use the correct mask to detect i830 aperture size.Tim Gardner
BugLink: https://bugs.launchpad.net/bugs/597075 commit f1befe71fa7a79ab733011b045639d8d809924ad introduced a regression when detecting aperture size of some i915 adapters, e.g., those on the Intel Q35 chipset. The original report: https://bugzilla.kernel.org/show_bug.cgi?id=15733 The regression report: https://bugzilla.kernel.org/show_bug.cgi?id=16294 According to the specification found at http://intellinuxgraphics.org/VOL_1_graphics_core.pdf, the PCI config space register I830_GMCH_CTRL is a mirror of GMCH Graphics Control. The correct macro for isolating the aperture size bits is therefore I830_GMCH_GMS_MASK along with the attendant changes to the case statement. Signed-off-by: Tim Gardner <tim.gardner@canonical.com> Tested-by: Kees Cook <kees.cook@canonical.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Eric Anholt <eric@anholt.net> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-06-15agp: add no warn since we have a fallback to vmalloc pathsDave Airlie
also drop the NORETRY we can probably nearly always satisfy order 1 allocs now, and again the vmalloc path is there. Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-06-15agp: drop vmalloc flag.Dave Airlie
Since the code that was too ugly to live is upstream, we can use it now, instead of rolling our own. Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-06-02agp/uninorth: Fix oops caused by flushing too muchPaul Mackerras
This fixes a sporadic oops at boot on G5 Power Macs. The table_end variable has the address of the last byte of the table. Adding on PAGE_SIZE means we flush too much, and if the page after the table is not mapped for any reason, the kernel will oops. Instead we add on 1 because flush_dcache_range() interprets its second argument as the first byte past the range to be flushed. Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2010-06-01Merge branch 'drm-intel-next' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel * 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel: (41 commits) drm/i915: add HAS_BSD check to i915_getparam drm/i915: Honor sync polarity from VBT panel timing descriptors drm/i915: Unmask interrupt for render engine on Sandybridge drm/i915: Fix PIPE_CONTROL command on Sandybridge drm/i915: Fix up address spaces in slow_kernel_write() drm/i915: Use non-atomic kmap for slow copy paths drm/i915: Avoid moving from CPU domain during pwrite drm/i915: Cleanup after failed initialization of ringbuffers drm/i915: Reject bind_to_gtt() early if object > aperture drm/i915: Check error code whilst moving buffer to GTT domain. drm/i915: Remove spurious warning "Failure to install fence" drm/i915: Rebind bo if currently bound with incorrect alignment. drm/i915: Include pitch in set_base debug statement. drm/i915: Only print "nothing to do" debug message as required. drm/i915: Propagate error from unbinding an unfenceable object. drm/i915: Avoid nesting of domain changes when setting display plane drm/i915: Hold the spinlock whilst resetting unpin_work along error path drm/i915: Only print an message if there was an error drm/i915: Clean up leftover bits from hws move to ring structure. drm/i915: Add CxSR support on Pineview DDR3 ...
2010-05-26agp/intel: Restrict GTT mapping to valid range on i915 and i945Chris Wilson
References: Bug 15733 - Crash when accessing nonexistent GTT entries in i915 https://bugzilla.kernel.org/show_bug.cgi?id=15733 On G33 and above, the size of the GTT space is determined by the GMCH control register. Prior to this revision, the size is determined by the size of the aperture. So we must careful to map and fill the appropriate range depending on chipset. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-05-26Merge branch 'drm-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6 * 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: agp: amd64, fix pci reference leaks drm/edid: Allow non-fatal checksum errors in CEA blocks drm/radeon/kms: suppress a build warning (unused variable) drm: Fixes linux-next & linux-2.6 checkstack warnings: nouveau: fix acpi_lid_open undefined drm/radeon/kms: release AGP bridge at suspend
2010-05-26agp: amd64, fix pci reference leaksJiri Slaby
Stanse found pci reference leaks in uli_agp_init and nforce3_agp_init initialization functions. The PCI devices are bridges, so it's not critical, but still worth fixing. Signed-off-by: Jiri Slaby <jirislaby@gmail.com> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-05-21Merge branch 'drm-for-2.6.35' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6 * 'drm-for-2.6.35' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (207 commits) drm/radeon/kms/pm/r600: select the mid clock mode for single head low profile drm/radeon: fix power supply kconfig interaction. drm/radeon/kms: record object that have been list reserved drm/radeon: AGP memory is only I/O if the aperture can be mapped by the CPU. drm/radeon/kms: don't default display priority to high on rs4xx drm/edid: fix typo in 1600x1200@75 mode drm/nouveau: fix i2c-related init table handlers drm/nouveau: support init table i2c device identifier 0x81 drm/nouveau: ensure we've parsed i2c table entry for INIT_*I2C* handlers drm/nouveau: display error message for any failed init table opcode drm/nouveau: fix init table handlers to return proper error codes drm/nv50: support fractional feedback divider on newer chips drm/nv50: fix monitor detection on certain chipsets drm/nv50: store full dcb i2c entry from vbios drm/nv50: fix suspend/resume with DP outputs drm/nv50: output calculated crtc pll when debugging on drm/nouveau: dump pll limits entries when debugging is on drm/nouveau: bios parser fixes for eDP boards drm/nouveau: fix a nouveau_bo dereference after it's been destroyed drm/nv40: remove some completed ctxprog TODOs ...
2010-05-19amd64-agp: Probe unknown AGP devices the right wayBen Hutchings
The current initialisation code probes 'unsupported' AGP devices simply by calling its own probe function. It does not lock these devices or even check whether another driver is already bound to them. We must use the device core to manage this. So if the specific device id table didn't match anything and agp_try_unsupported=1, switch the device id table and call driver_attach() again. Signed-off-by: Ben Hutchings <ben@decadent.org.uk> Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-05-19sis-agp: Remove SIS 760, handled by amd64-agpBen Hutchings
SIS 760 is listed in the device tables for both amd64-agp and sis-agp. amd64-agp is apparently preferable since it has workarounds for some BIOS misconfigurations that sis-agp doesn't handle. Signed-off-by: Ben Hutchings <ben@decadent.org.uk> Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-05-11agp: use NULL instead of 0 when pointer is neededBill Pemberton
Fixes sparse warning: drivers/char/agp/generic.c:1217:33: warning: Using plain integer as NULL pointer Signed-off-by: Bill Pemberton <wfp5p@virginia.edu> CC: linux-kernel@vger.kernel.org Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2010-04-23agp: use scratch page on memory remove and at GATT creation V4Jerome Glisse
Convert most AGP chipset to use scratch page as default entries. This help avoiding GPU querying 0 address and trigger computer fault. With KMS and memory manager we bind/unbind AGP memory constantly and it seems that some GPU are still doing AGP traffic even after GPU report being idle with the memory segment. Tested (radeon GPU KMS + Xorg + compiz + glxgears + quake3) on : - SIS 1039:0001 & 1039:0003 - Intel 865 8086:2571 Compile tested for other bridges V2 enable scratch page on uninorth V3 fix unbound check in uninorth insert memory (Michel Dänzer) V4 rebase on top of drm-next branch with the lastest intel AGP changeset (stable should use version V3 of the patch) Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Michel Dänzer <michel@daenzer.net> Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-04-20agp/intel: put back check that we have a driver for the bridge.Dave Airlie
On my 945 laptop + radeon GPU, I was getting an oops on boot without this check which seems to have gotten dropped in the rework. Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-04-20Merge remote branch 'anholt/drm-intel-next' of /home/airlied/kernel/drm-next ↵Dave Airlie
into drm-core-next * 'anholt/drm-intel-next' of /home/airlied/kernel/drm-next: (48 commits) agp/intel-gtt: kill previous_size assignments agp/intel-gtt: kill intel_i830_tlbflush agp/intel: split out gmch/gtt probe, part 1 agp/intel: kill mutli_gmch_chip agp/intel: uncoditionally reconfigure driver on resume agp/intel: split out the GTT support agp/intel: introduce intel-agp.h header file drm/i915: Don't touch PORT_HOTPLUG_EN in intel_dp_detect() drm/i915/pch: Use minimal number of FDI lanes (v2) drm/i915: Add the support of memory self-refresh on Ironlake drm/i915: Move Pineview CxSR and watermark code into update_wm hook. drm/i915: Only save/restore FBC on the platform that supports FBC drm/i915: Fix the incorrect argument for SDVO SET_TV_format command drm/i915: Add support of SDVO on Ibexpeak PCH drm/i915: Don't enable pipe/plane/VCO early (wait for DPMS on). drm/i915: do not read uninitialized ->dev_private Revert "drm/i915: Use a dmi quirk to skip a broken SDVO TV output." drm/i915: implement multifunction SDVO device support drm/i915: remove unused intel_pipe_get_connector() drm/i915: remove connector object in old output structure ...
2010-04-18agp/intel-gtt: kill previous_size assignmentsDaniel Vetter
Not needed for the GTT and inconsistent: Sometimes the _new_ size was stored there ... Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-04-18agp/intel-gtt: kill intel_i830_tlbflushDaniel Vetter
We don't use the generic insert/remove_memory functions that require this. So kill this useless code. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-04-18agp/intel: split out gmch/gtt probe, part 1Daniel Vetter
This is essentially the last piece of code that's tying intel-gtt.c to intel-agp.c. Extract the probe code into it's own function so that it can be moved to intel-gtt.c. This requires some slight changes in the ordering of device probe function. This patch just implements that for better bisectability in case this introduces bugs. The biggest change is that the gmch/gtt code doesn't execute a pci resource fixup anymore. I've dug around in historical git trees, and this change is to support the agp port on an old HP server with the i440 intel chipset. So only needed for the agp driver. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-04-18agp/intel: kill mutli_gmch_chipDaniel Vetter
Always zero, i.e. unused. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-04-18agp/intel: uncoditionally reconfigure driver on resumeDaniel Vetter
Only two drivers were not in this table (7505 and g33), both non-mobile chipsets. So they were most likely just missing. This is another step to untangle the gtt from the agp driver. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-04-18agp/intel: split out the GTT supportDaniel Vetter
intel-agp.c contains actually two different drivers: An agp driver for _physical_ agp slots an the gtt driver that is used by the intel drm modules. Split them to prevent any further confusion. This patch just moves the code and includes intel-gtt.c in intel-agp.c Later patches will untangle these two drivers further. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-04-18agp/intel: introduce intel-agp.h header fileDaniel Vetter
Intel definitions have spilled into agp.h. Create a header file for them and also include it in efficion-agp.c 'cause it needs a few of them. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-04-17Merge branch 'for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel: drm/i915: Ignore LVDS EDID when it is unavailabe or invalid drm/i915: Add no_lvds entry for the Clientron U800 drm/i915: Rename many remaining uses of "output" to encoder or connector. drm/i915: Rename intel_output to intel_encoder. agp/intel: intel_845_driver is an agp driver! drm/i915: introduce to_intel_bo helper drm/i915: Disable FBC on 915GM and 945GM.
2010-03-30include cleanup: Update gfp.h and slab.h includes to prepare for breaking ↵Tejun Heo
implicit slab.h inclusion from percpu.h percpu.h is included by sched.h and module.h and thus ends up being included when building most .c files. percpu.h includes slab.h which in turn includes gfp.h making everything defined by the two files universally available and complicating inclusion dependencies. percpu.h -> slab.h dependency is about to be removed. Prepare for this change by updating users of gfp and slab facilities include those headers directly instead of assuming availability. As this conversion needs to touch large number of source files, the following script is used as the basis of conversion. http://userweb.kernel.org/~tj/misc/slabh-sweep.py The script does the followings. * Scan files for gfp and slab usages and update includes such that only the necessary includes are there. ie. if only gfp is used, gfp.h, if slab is used, slab.h. * When the script inserts a new include, it looks at the include blocks and try to put the new include such that its order conforms to its surrounding. It's put in the include block which contains core kernel includes, in the same order that the rest are ordered - alphabetical, Christmas tree, rev-Xmas-tree or at the end if there doesn't seem to be any matching order. * If the script can't find a place to put a new include (mostly because the file doesn't have fitting include block), it prints out an error message indicating which .h file needs to be added to the file. The conversion was done in the following steps. 1. The initial automatic conversion of all .c files updated slightly over 4000 files, deleting around 700 includes and adding ~480 gfp.h and ~3000 slab.h inclusions. The script emitted errors for ~400 files. 2. Each error was manually checked. Some didn't need the inclusion, some needed manual addition while adding it to implementation .h or embedding .c file was more appropriate for others. This step added inclusions to around 150 files. 3. The script was run again and the output was compared to the edits from #2 to make sure no file was left behind. 4. Several build tests were done and a couple of problems were fixed. e.g. lib/decompress_*.c used malloc/free() wrappers around slab APIs requiring slab.h to be added manually. 5. The script was run on all .h files but without automatically editing them as sprinkling gfp.h and slab.h inclusions around .h files could easily lead to inclusion dependency hell. Most gfp.h inclusion directives were ignored as stuff from gfp.h was usually wildly available and often used in preprocessor macros. Each slab.h inclusion directive was examined and added manually as necessary. 6. percpu.h was updated not to include slab.h. 7. Build test were done on the following configurations and failures were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my distributed build env didn't work with gcov compiles) and a few more options had to be turned off depending on archs to make things build (like ipr on powerpc/64 which failed due to missing writeq). * x86 and x86_64 UP and SMP allmodconfig and a custom test config. * powerpc and powerpc64 SMP allmodconfig * sparc and sparc64 SMP allmodconfig * ia64 SMP allmodconfig * s390 SMP allmodconfig * alpha SMP allmodconfig * um on x86_64 SMP allmodconfig 8. percpu.h modifications were reverted so that it could be applied as a separate patch and serve as bisection point. Given the fact that I had only a couple of failures from tests on step 6, I'm fairly confident about the coverage of this conversion patch. If there is a breakage, it's likely to be something in one of the arch headers which should be easily discoverable easily on most builds of the specific arch. Signed-off-by: Tejun Heo <tj@kernel.org> Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-25agp/intel: intel_845_driver is an agp driver!Daniel Vetter
... not a GTT driver. So the additional chipset flush introduced in commit 2162e6a2b0cd5acbb9bd8a3c94e1c1269b078295 Author: Dave Airlie <airlied@redhat.com> Date: Wed Nov 21 16:36:31 2007 +1000 agp/intel: Add chipset flushing support for i8xx chipsets. to fix a GTT problem makes absolutely no sense. If this would really be needed for AGP chipsets, too, we should add it to all i8xx agp drivers, not just one. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-03-18agp/intel: Don't do the chipset flush on Sandybridge.Eric Anholt
This CPU should be coherent with graphics in this direction, though flushing graphics caches are still required. Fixes a system reset on module load on Sandybridge with 4G+ memory. Signed-off-by: Eric Anholt <eric@anholt.net>
2010-03-18agp/intel: Respect the GTT size on Sandybridge for scratch page setup.Eric Anholt
This is similar to 14bc490bbdf1b194ad1f5f3d2a0a27edfdf78986 which respected it for how much of the GTT we would actually use. Now we won't clear beyond allocated memory when filling the GTT with scratch page addresses. Signed-off-by: Eric Anholt <eric@anholt.net>