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There is currently a race condition in the device tree part of clk_get()
function, since the pointer returned from of_clk_get_by_name() may become
invalid before __clk_get() call. E.g. due to the clock provider driver
remove() callback being called in between of_clk_get_by_name() and
__clk_get().
Fix this by doing both the look up and __clk_get() operations with the
clock providers list mutex held. This ensures that the clock pointer
returned from __of_clk_get_from_provider() call and passed to __clk_get()
is valid, as long as the clock supplier module first removes its clock
provider instance and then does clk_unregister() on the corresponding
clocks.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Add helper functions for the of_clk_providers list locking and
an unlocked variant of of_clk_get_from_provider().
These functions are intended to be used in the clkdev to avoid
race condition in the device tree based clock look up in clk_get().
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Enable common clock driver of Hi3620 SoC. clkgate-seperated driver is
used to support the clock gate that enable/disable/status registers
are seperated.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
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git://nv-tegra.nvidia.com/user/pdeschrijver/linux into clk-next-tegra
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This patch adds at91 smd (Soft Modem) clock implementation using common clk
framework.
Not used by any driver right now.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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This patch adds new at91 usb clock implementation using common clk framework.
This clock is used to clock usb ports (ohci, ehci and udc).
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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This adds new at91 utmi clock implementation using common clk framework.
This clock is a pll with a fixed factor (x40).
It is used as a source for usb clock.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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This patch adds new at91 programmable clocks implementation using common clk
framework.
A programmable clock is a clock which can be exported on a given pin to clock
external devices.
Each programmable clock is given an id (from 0 to 8).
The number of available programmable clocks depends on the SoC you're using.
Programmable clock driver only implements the clock setting (clock rate and
parent setting). It must be chained to a system clock in order to
enable/disable the generated clock.
The PCKX pins used to output the clock signals must be assigned to the
appropriate peripheral (see atmel's datasheets).
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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This patch adds new at91 peripheral clock implementation using common clk
framework.
Almost all peripherals provided by at91 SoCs need a clock to work properly.
This clock is enabled/disabled using PCER/PCDR resgisters.
Each peripheral is given an id (see atmel's datasheets) which is used to
define and reference peripheral clocks.
Some new SoCs (at91sam9x5 and sama5d3) provide a new register (PCR) where you
can configure the peripheral clock as a division of the master clock.
This will help reducing the peripherals power comsumption.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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This patch adds new at91 system clock implementation using common clk
framework.
Some peripherals need to enable a "system" clock in order to work properly.
Each system clock is given an id based on the bit position in SCER/SCDR
registers.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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This patch adds new at91 master clock implementation using common clk
framework.
The master clock layout describe the MCKR register layout.
There are 2 master clock layouts:
- at91rm9200
- at91sam9x5
Master clocks are given characteristics:
- min/max clock output rate
These characteristics are checked during rate change to avoid
over/underclocking.
These characteristics are described in atmel's SoC datasheet in
"Electrical Characteristics" paragraph.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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This patch adds new at91 pll clock implementation using common clk framework.
The pll clock layout describe the PLLX register layout.
There are four pll clock layouts:
- at91rm9200
- at91sam9g20
- at91sam9g45
- sama5d3
PLL clocks are given characteristics:
- min/max clock source rate
- ranges of valid clock output rates
- values to set in out and icpll fields for each supported output range
These characteristics are checked during rate change to avoid
over/underclocking.
These characteristics are described in atmel's SoC datasheet in
"Electrical Characteristics" paragraph.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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This patch adds new at91 main oscillator clock implementation using common
clk framework.
If rate is not provided during clock registration it is calculated using
the slow clock (main clk parent in this case) rate and MCFR register.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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This patch adds at91 PMC (Power Management Controller) base support.
All at91 clocks managed by the PMC unit will use this framework.
This framework provides the following fonctionalities:
- define a new struct at91_pmc to hide PMC internals (lock, PMC memory
mapping, irq domain, ...)
- read/write helper functions (pmc_read/write) to access PMC registers
- lock/unlock helper functions (pmc_lock/unlock) to lock/unlock access to
pmc registers
- a new irq domain and its associated irq chip to request PMC specific
interrupts (useful for clk prepare callbacks)
The PMC unit is declared as a dt clk provider (CLK_OF_DECLARE), and every
clk using this framework will declare a table of of_at91_clk_init_cb_t
and add it to the pmc_clk_ids table.
When the pmc dt clock setup function is called (by of_clk_init function),
it triggers the registration of every supported child clk (those matching
the definitions in pmc_clk_ids).
This patch copies at91_pmc_base (memory mapping) and at91sam9_idle
(function) from arch/arm/mach-at91/clock.c (which is not compiled if
COMMON_CLK_AT91 is enabled).
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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clk-next-sunxi-rebase
Allwinner sunXi SoCs clock changes
Those are mostly random fixes, except for one patch to the composite
clock that adds support for automatic reparenting.
Conflicts:
drivers/clk/sunxi/clk-sunxi.c
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In case of error, the function __clk_lookup() returns NULL pointer
not ERR_PTR(). The IS_ERR() test in the return value check should
be replaced with NULL test.
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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clk_round_rate() can be used by drivers to determine whether or not a
frequency is supported by the clock. The current Tegra clock driver
outputs an error message and a stacktrace when the requested rate isn't
supported. That's fine for clk_set_rate(), but it's confusing when all
the driver does is query whether or not a frequency is supported.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The function socfpga_clk_init() can support clocks that do not have a divider
register, but a fixed-divider that can be read from DTS. Therefore, the "reg"
property is not a failing condition for socfpga_clk_init().
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
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[Maybe the third time will be the charm. -Alex]
If CONFIG_COMMON_CLK_DEBUG is defined, clk_debug_create_one() is
called to populate a debugfs directory with a few entries that are
common for all clock types.
If an error happens after creating the first one debugfs_remove() is
called on the clock's directory. The problem with this is that no
cleanup is done on the debugfs files already created in that
directory, so the directory never actually gets removed. This
problem is silently ignored.
Fix this by calling debugfs_remove_recursive() instead. Reset the
clk->dentry field to null afterward, to ensure it can't be mistaken
as a valid pointer.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
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The low-power DSI clocks are used during host-driven transactions on the
DSI bus. Documentation recommends that they be children of PLLP and run
at a frequency of at least 52 MHz.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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This clock is needed to ensure the FUSE registers can be accessed
without freezing the system.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
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The clock for the PWM controller is slightly different from other
peripheral clocks on Tegra30. The clock source mux field start at
bit position 28 rather than 30.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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There are two GPUs on Tegra30 and each of them uses a separate clock, so
the secondary clock needs to be initialized in order for the gr3d module
to work properly.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Add disp1 and disp2 clocks to the clock initialization table. These
clocks are required for display and HDMI support.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Adding suspend/resume function for tegra_cpu_car_ops. We only save and
restore the setting of the clock of CoreSight. Other clocks still need
to be taken care by clock driver.
Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
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Hook the functions for CPU hotplug support. After the CPU is hot
unplugged, the flow controller will handle to clock gate the CPU clock.
But still need to implement an empty function to avoid warning message.
Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
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Implement clock support for Tegra124.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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Tegra124 introduces a number of new peripheral clocks. This patch adds those
to the common peripheral clock code.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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Tegra124 introduces a number of a new clocks. Introduce the corresponding
the IDs for them.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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Tegra124 has a clock which consists of a mux and a fractional divider.
Add support for this.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Tegra124 has periph clocks which share the hw register. Hence locking is
required.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Tegra124 has an extra bank of peripheral clock registers. Add it to the
generic peripheral clock code.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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Tegra124 introduces a new PLL type, PLLSS. Add support for it.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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Move tegra20 to common tegra clock infrastructure.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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Move tegra30 to common tegra clock infrastructure.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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Introduce a common function which performs super clock initialization for
Tegra114 and beyond.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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Introduce new files for fixed and PMC clocks common between several Tegra
SoCs and move Tegra114 to this new infrastructure.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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Introduce a new file for peripheral clocks common between several Tegra
SoCs and move Tegra114 to this new infrastructure. Also PLLP and the PLLP_OUT
clocks will be initialized here.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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Move audio clocks and PLLA initialization to a common file so it can be used by
multiple Tegra SoCs. Also a new array tegra114_clks is introduced for Tegra114
which specifies which common clocks are available on Tegra114 and what their
DT IDs are.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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Add a common infra for registering clkdev. This allows decoupling clk
registration from clkdev registration.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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Introduce a common infrastructure for sharing clock initialization between
SoCs.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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Many clocks are common between several Tegra SoCs. Define an enum to list
them so we can move them to separate files which can be shared between
SoCs. Each SoC specific file will provide an array with the common clocks
which are present on the SoC and their DT binding ID.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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Move some fields related to the PLL HW description to the tegra_clk_pll_params.
This allows some PLL code to be moved to common files later.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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Use pll_ref instead of pll_re_vco as the pll_e parent on Tegra114. Also
add a 12Mhz pll_ref table entry for pll_e for Tegra114. This prevents
the system from crashing at bootup because of an unsupported pll_re_vco
rate.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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VCO min clipping, dynamic ramp setup and IDDQ init can be done in the
respective PLL clk_register functions if the parent is already registered.
This is done for other some PLLs already.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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This flag indicates the peripheral clock does not have a divider. It will
simplify the initialization tables and avoids some very similar code.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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This patch makes periph_clk_enb_refcnt a global array, dynamically allocated
at boottime. It simplifies the macros somewhat and allows clocks common to
several Tegra SoCs to be defined in a separate files. Also the clks array
becomes global and dynamically allocated which allows the DT registration to
be moved to a generic funcion.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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This patch determines the register bank for clock enable/disable and reset
based on the clock ID instead of hardcoding it in the tables describing the
clocks. This results in less data to be maintained in the tables, making the
code easier to understand. The full benefit of the change will be realized once
also other clocktypes will be table based.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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The PLL output frequency is multiplied during the P-divider computation,
so it needs to be divided by the P-divider again before returning.
This fixes an issue where clk_round_rate() would return the multiplied
frequency instead of the real one after the P-divider.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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These clocks were named gr2d and gr3d on Tegra20 and Tegra30, so use the
same names on Tegra114 for consistency.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
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