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2013-06-16ARM: tegra30: clocks: Fix pciex clock registrationJay Agarwal
Registering pciex as peripheral clock instead of fixed clock as tegra_perih_reset_assert(deassert) api of this clock api gives warning and ultimately does not succeed to assert(deassert) Signed-off-by: Jay Agarwal <jagarwal@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-15clk: gate: add CLK_GATE_HIWORD_MASKHaojian Zhuang
In Rockchip Cortex-A9 based chips, they don't use paradigm of reading-changing-writing the register contents. Instead they use a hiword mask to indicate the changed bits. When b1 should be set as gate, it also needs to indicate the change by setting hiword mask (b1 << 16). The patch adds gate flag for this usage. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-15clk: divider: add CLK_DIVIDER_HIWORD_MASK flagHaojian Zhuang
In both Hisilicon & Rockchip Cortex-A9 based chips, they don't use the paradigm of reading-changing-writing the register contents. Instead they use a hiword mask to indicate the changed bits. When b01 should be set as setting divider, it also needs to indicate the change by setting hiword mask (b11 << 16). The patch adds divider flag for this usage. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-15clk: mux: add CLK_MUX_HIWORD_MASKHaojian Zhuang
In both Hisilicon & Rockchip Cortex-A9 based chips, they don't use the paradigm of reading-changing-writing the register contents. Instead they use a hiword mask to indicate the changed bits. When b01 should be set as switching mux, it also needs to indicate the change by setting hiword mask (b11 << 16). The patch adds mux flag for this usage. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-15clk: Always notify whole subtree when reparentingSoren Brinkmann
A clock's notifier count only reflects notifiers which are registered directly for that clock. A reparent operation though affects the whole subtree because of a potential rate change. When issuing the pre rate change notifications only the notifier count for the clock to be changed is considered and notifiers for subclocks may never be called. Resulting in clocks in the subtree which have registered notifiers, may receive a POST_- or ABORT_RATE_CHANGE notification, without a PRE_RATE_CHANGE_NOTIFICATION. Therefore always traverse the whole subtree when issueing pre rate change notifications during a reparent operation. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-14Merge tag 'tegra-for-3.11-soc' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc From Stephen Warren: ARM: tegra: core SoC support enhancements This branch contains fixes and enhancement for core Tegra Soc support: * CPU hotplug support for Tegra114. * Some preliminary work on Tegra114 CPU sleep modes. * Minor fix for EMC table DT parsing. * tag 'tegra-for-3.11-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: ARM: tegra: don't pass CPU ID to tegra_{set,clear}_cpu_in_lp2 ARM: tegra: cpuidle: using IS_ENABLED for multi SoCs management in init func ARM: tegra: hook tegra_tear_down_cpu function in the PM suspend init function ARM: tegra: cpuidle: move the init function behind the suspend init function ARM: tegra: remove ifdef in the tegra_resume ARM: tegra: add cpu_disable for hotplug ARM: tegra114: add CPU hotplug support clk: tegra114: implement wait_for_reset and disable_clock for tegra_cpu_car_ops ARM: tegra114: add power up sequence for warm boot CPU ARM: tegra: make tegra_resume can work for Tegra114 ARM: tegra: skip SCU and PL310 code when CPU is not Cortex-A9 ARM: tegra: add an assembly marco to check Tegra SoC ID ARM: tegra: emc: correction of ram-code parsing from dt Signed-off-by: Olof Johansson <olof@lixom.net>
2013-06-12Merge tag 'exynos-dt-1' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/dt From Kukjin Kim: Update exynos DT for - usb3phy and dwc3 for exynos5250 - keypad for exynos4412 - TMU clock for exynos4210 - MFC clock for exynos4 - DP controller for exynos5250 - G2D clock for exynos4 - some exynos boards * tag 'exynos-dt-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (456 commits) ARM: dts: add ohci and ehci controller nodes for EXYNOS5440 ARM: dts: Update G2D documentation for clock entries ARM: dts: Add clock entries to G2D node for exynos4x12 ARM: dts: Add clock entries to G2D node for exynos4210 ARM: dts: Remove duplicate and add missing G2D nodes clk: exynos4: Add additional G2D clocks ARM: dts: Document DP clock in samsung,exynos5-dp binding ARM: dts: add pin state information for DP HPD support to Exynos5250 ARM: dts: add dts node for the ahci sata exynos5440 ARM: dts: add vmmc regulator support for ODROID-X ARM: dts: add max77686 node entry for ODROID-X ARM: dts: Enable RTC by default on EXYNOS5440 ARM: dts: Add display timing node to exynos5250-arndale.dts ARM: dts: Add clock provider information for DP controller in Exynos5250 SoC ARM: dts: Add DT node for DP controller for Arndale Board ARM: dts: Remove combiner IRQ node from exynos4x12.dtsi ARM: dts: add max8997 device node for exynos4210-origen board ARM: dts: Enable TMU on Origen4210 board ARM: dts: Add TMU clock entries to exynos4210.dtsi ARM: dts: Update MFC documentation for clock entries ... Signed-off-by: Olof Johansson <olof@lixom.net>
2013-06-11clk: exynos5250: Add CLK_IGNORE_UNUSED flag for pmu clockTushar Behera
Currently 'pmu' clock is not handled by any of the drivers. Also before the introduction of CCF, this clock was not defined, hence was left enabled always. When this clock is disabled, software reset register becomes inaccessible and system reboot doesn't work. Upon restoring the default behaviour, system reboot starts working. Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-11clk: honor CLK_GET_RATE_NOCACHE in clk_set_ratePeter De Schrijver
clk_set_rate() uses clk->rate directly. This causes problems if the clock is marked as CLK_GET_RATE_NOCACHE. Hence call clk_get_rate() to get the current rate. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-11clk: use clk_get_rate() for debugfsPeter De Schrijver
debugfs uses the rate field directly. However this ignores the CLK_GET_RATE_NOCACHE flag. Call clk_get_rate() instead. Tested-by: Mark Zhang <markz@nvidia.com> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-11clk: tegra: Use override bits when neededPeter De Schrijver
PLLM has override bits in the PMC. Use those when PLLM_OVERRIDE_ENABLE is set. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-11clk: tegra: override bits for Tegra30 PLLMPeter De Schrijver
Define override bits for Tegra30 PLLM. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-11clk: tegra: override bits for Tegra114 PLLMPeter De Schrijver
Define override bits for Tegra114 PLLM. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: fixed up trivial merge conflict]
2013-06-11clk: tegra: Add fields for override bitsPeter De Schrijver
PLLM can have override bits in the PMC. Describe those in the PLL parameters. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-11clk: tegra: fix sclk_parentsPeter De Schrijver
Use the correct parents for sclk according to the TRM. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-11clk: tegra: fix pllre initilizationPeter De Schrijver
The PLLRE flags weren't set correctly. Fixed in this patch. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-11clk: tegra: PLL m,n,p init for Tegra114Peter De Schrijver
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-11clk: tegra: allow PLL m,n,p init from SoC filesPeter De Schrijver
The m,n,p fields don't have the same bit offset and width across all PLLs. This patch allows SoC specific files to indicate the offset and width. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-11clk: tegra: pllp_out2 divider is int onlyPeter De Schrijver
The pllp_out2 should be integer only, the fractional bit should always be 0. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-11ARM: socfpga: Add support to gate peripheral clocksDinh Nguyen
Add support to gate the clocks that directly feed peripherals. For clocks with multiple parents, add the ability to determine the correct parent, and also set parents. Also add support to calculate and set the clocks' rate. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Reviewed-by: Pavel Machek <pavel@denx.de> Acked-by: Mike Turquette <mturquette@linaro.org> Cc: Mike Turquette <mturquette@linaro.org> CC: Arnd Bergmann <arnd@arndb.de> CC: Olof Johansson <olof@lixom.net> Cc: Pavel Machek <pavel@denx.de> CC: <linux@arm.linux.org.uk> v4: - Add Acked-by: Mike Turquette v3: - Addressed comments from Pavel v2: - Fix space/indent errors - Add streq for strcmp == 0 Signed-off-by: Olof Johansson <olof@lixom.net>
2013-06-11clk: tegra: pllc and pllxc should use pdiv_mapPeter De Schrijver
The pllc and pllxc code weren't always using the correct pdiv_map to map between the post divider value and the hw p field. This could result in illegal values being programmed in the hw. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-11Merge branch 'clps711x/soc' into next/socOlof Johansson
From Alexander Shiyan, this is a series of cleanups of clps711x, movig it closer to multiplatform and cleans up a bunch of old code. * clps711x/soc: ARM: clps711x: Update defconfig ARM: clps711x: Add support for SYSCON driver ARM: clps711x: edb7211: Control LCD backlight via PWM ARM: clps711x: edb7211: Add support for I2C ARM: clps711x: Optimize interrupt handling ARM: clps711x: Add clocksource framework ARM: clps711x: Replace "arch_initcall" in common code with ".init_early" ARM: clps711x: Move specific definitions from hardware.h to boards files ARM: clps711x: p720t: Define PLD registers as GPIOs ARM: clps711x: autcpu12: Move remaining specific definitions to board file ARM: clps711x: autcpu12: Special driver for handling memory is removed ARM: clps711x: autcpu12: Add support for NOR flash ARM: clps711x: autcpu12: Move LCD DPOT definitions to board file ARM: clps711x: Set PLL clock to zero if we work from 13 mHz source ARM: clps711x: Remove NEED_MACH_MEMORY_H dependency ARM: clps711x: Re-add GPIO support GPIO: clps711x: Add DT support GPIO: clps711x: Rewrite driver for using generic GPIO code + Linux 3.10-rc4 Signed-off-by: Olof Johansson <olof@lixom.net>
2013-06-11clk: spear: fix build error for spear3xxArnd Bergmann
This patch is required to be able to disable spear320 support after the spear320_clk_init() prototype changed for the real function but not for the dummy. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-12clk: exynos4: Add additional G2D clocksSachin Kamat
Add G2D clocks for Exynos4x12 SoC and sclk_fimg2d required by G2D IP. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Cc: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-06-11clk: samsung: Fix pll36xx_recalc_rate to handle kdiv properlyDoug Anderson
The KDIV value is often listed as unsigned but it needs to be treated as a 16-bit signed value when using it in calculations. Fix our rate recalculation to do this correctly. Before doing this, I tried setting EPLL on exynos5250 to: rate, m, p, s, k = 80000000, 107, 2, 4, 43691 This rate is exactly from the table in the exynos5250 user manual. I read this back as 80750003 with: cat /sys/kernel/debug/clk/fin_pll/fout_epll/clk_rate After this patch, it reads back as 80000003 Signed-off-by: Doug Anderson <dianders@chromium.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Reviewed-by: Vikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-10clk: divider: do not propagate rate change request when unnecessaryShawn Guo
If the current rate of parent clock is sufficient to provide child a requested rate with a proper divider setting, the rate change request should not be propagated. Instead, changing the divider setting is good enough to get child clock run at the requested rate. On an imx6q clock configuration illustrated below, ahb --> ipg --> ipg_per 132M 66M 66M calling clk_set_rate(ipg_per, 22M) with the current clk_divider_bestdiv() implementation will result in the rate change up to ahb level like the following, because of the unnecessary/incorrect rate change propagation. ahb --> ipg --> ipg_per 66M 22M 22M Fix the problem by trying to see if the requested rate can be achieved by simply changing the divider value, and in that case return the divider immediately from function clk_divider_bestdiv() as the best one, so that all those unnecessary rate change propagation can be saved. Reported-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-10clk: exynos5250: Add sclk_mpll to the parent list of mout_cpu clockTushar Behera
'mout_mpll' is added the list of parent clocks for 'mout_cpu'. 'mout_mpll' is an alias to the clock 'sclk_mpll'. Hence 'sclk_mpll' should be added to the list of parent clocks. This results in an error when cpufreq driver for EXYNOS5250 tries to set 'mout_mpll' as a parent for 'mout_cpu'. clk_set_parent: clk sclk_mpll can not be parent of clk mout_cpu Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-10clk: exynos5250: Update cpufreq related clocks for EXYNOS5250Tushar Behera
cpufreq driver for EXYNOS5250 is not a platform driver, hence we cannot currently pass the clock names through a device tree node. Instead, we need to make them available through a global alias. cpufreq driver for EXYNOS5250 requires four clocks - 'armclk', 'mout_cpu', 'mout_mpll' and 'mout_apll'. 'armclk' has already been defined with an alias, 'mout_cpu', 'mout_mpll' and 'mout_apll' are now defined with an alias. Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-07Merge tag 'zynq-clk-for-3.11' of git://git.xilinx.com/linux-xlnx into next/socOlof Johansson
From Michal Simek: arm: Xilinx Zynq clock changes for v3.11 Change Xilinx Zynq DT clock description which reflects logical abstraction of Zynq's clock tree. - Refactor PLL driver - Use new clock controller driver - Change timer and uart drivers * tag 'zynq-clk-for-3.11' of git://git.xilinx.com/linux-xlnx: clk: zynq: Remove deprecated clock code arm: zynq: Migrate platform to clock controller clk: zynq: Add clock controller driver clk: zynq: Factor out PLL driver Signed-off-by: Olof Johansson <olof@lixom.net>
2013-06-06clk: remove notifier from list before freeing itLai Jiangshan
The @cn is stay in @clk_notifier_list after it is freed, it cause memory corruption. Example, if @clk is registered(first), unregistered(first), registered(second), unregistered(second). The freed @cn will be used when @clk is registered(second), and the bug will be happened when @clk is unregistered(second): [ 517.040000] clk_notif_dbg clk_notif_dbg.1: clk_notifier_unregister() [ 517.040000] Unable to handle kernel paging request at virtual address 00df3008 [ 517.050000] pgd = ed858000 [ 517.050000] [00df3008] *pgd=00000000 [ 517.060000] Internal error: Oops: 5 [#1] PREEMPT SMP ARM [ 517.060000] Modules linked in: clk_notif_dbg(O-) [last unloaded: clk_notif_dbg] [ 517.060000] CPU: 1 PID: 499 Comm: modprobe Tainted: G O 3.10.0-rc3-00119-ga93cb29-dirty #85 [ 517.060000] task: ee1e0180 ti: ee3e6000 task.ti: ee3e6000 [ 517.060000] PC is at srcu_readers_seq_idx+0x48/0x84 [ 517.060000] LR is at srcu_readers_seq_idx+0x60/0x84 [ 517.060000] pc : [<c0052720>] lr : [<c0052738>] psr: 80070013 [ 517.060000] sp : ee3e7d48 ip : 00000000 fp : ee3e7d6c [ 517.060000] r10: 00000000 r9 : ee3e6000 r8 : 00000000 [ 517.060000] r7 : ed84fe4c r6 : c068ec90 r5 : c068e430 r4 : 00000000 [ 517.060000] r3 : 00df3000 r2 : 00000000 r1 : 00000002 r0 : 00000000 [ 517.060000] Flags: Nzcv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user [ 517.060000] Control: 18c5387d Table: 2d85804a DAC: 00000015 [ 517.060000] Process modprobe (pid: 499, stack limit = 0xee3e6238) [ 517.060000] Stack: (0xee3e7d48 to 0xee3e8000) .... [ 517.060000] [<c0052720>] (srcu_readers_seq_idx+0x48/0x84) from [<c0052790>] (try_check_zero+0x34/0xfc) [ 517.060000] [<c0052790>] (try_check_zero+0x34/0xfc) from [<c00528b0>] (srcu_advance_batches+0x58/0x114) [ 517.060000] [<c00528b0>] (srcu_advance_batches+0x58/0x114) from [<c0052c30>] (__synchronize_srcu+0x114/0x1ac) [ 517.060000] [<c0052c30>] (__synchronize_srcu+0x114/0x1ac) from [<c0052d14>] (synchronize_srcu+0x2c/0x34) [ 517.060000] [<c0052d14>] (synchronize_srcu+0x2c/0x34) from [<c0053a08>] (srcu_notifier_chain_unregister+0x68/0x74) [ 517.060000] [<c0053a08>] (srcu_notifier_chain_unregister+0x68/0x74) from [<c0375a78>] (clk_notifier_unregister+0x7c/0xc0) [ 517.060000] [<c0375a78>] (clk_notifier_unregister+0x7c/0xc0) from [<bf008034>] (clk_notif_dbg_remove+0x34/0x9c [clk_notif_dbg]) [ 517.060000] [<bf008034>] (clk_notif_dbg_remove+0x34/0x9c [clk_notif_dbg]) from [<c02bb974>] (platform_drv_remove+0x24/0x28) [ 517.060000] [<c02bb974>] (platform_drv_remove+0x24/0x28) from [<c02b9bf8>] (__device_release_driver+0x8c/0xd4) [ 517.060000] [<c02b9bf8>] (__device_release_driver+0x8c/0xd4) from [<c02ba680>] (driver_detach+0x9c/0xc4) [ 517.060000] [<c02ba680>] (driver_detach+0x9c/0xc4) from [<c02b99c4>] (bus_remove_driver+0xcc/0xfc) [ 517.060000] [<c02b99c4>] (bus_remove_driver+0xcc/0xfc) from [<c02bace4>] (driver_unregister+0x54/0x78) [ 517.060000] [<c02bace4>] (driver_unregister+0x54/0x78) from [<c02bbb44>] (platform_driver_unregister+0x1c/0x20) [ 517.060000] [<c02bbb44>] (platform_driver_unregister+0x1c/0x20) from [<bf0081f8>] (clk_notif_dbg_driver_exit+0x14/0x1c [clk_notif_dbg]) [ 517.060000] [<bf0081f8>] (clk_notif_dbg_driver_exit+0x14/0x1c [clk_notif_dbg]) from [<c00835e4>] (SyS_delete_module+0x200/0x28c) [ 517.060000] [<c00835e4>] (SyS_delete_module+0x200/0x28c) from [<c000edc0>] (ret_fast_syscall+0x0/0x48) [ 517.060000] Code: e5973004 e7911102 e0833001 e2881002 (e7933101) Cc: stable@kernel.org Reported-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Lai Jiangshan <laijs@cn.fujitsu.com> Tested-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: shortened $SUBJECT]
2013-06-06clk: ux500: Clocks definition for u8540Philippe Begnic
First clocks definition version of PRCMU and PRCC clocks for u8540 platform Signed-off-by: Philippe Begnic <philippe.begnic@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-06clk: ux500: Pass clock base adresses in initcall for u8540 and u9540Philippe Begnic
Align on u8500 version, pass clock base address in clk_init functions for u8540 and u9540. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Philippe Begnic <philippe.begnic@st.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-04clk: tegra114: Fix msenc clock registerMikko Perttunen
The msenc clock's register was set to the usb3 clock's register. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-05-31Merge tag 'seb_clk-3.11' of git://git.infradead.org/users/jcooper/linux into ↵Olof Johansson
next/soc From Jason Cooper: mvebu clock restructuring for v3.11 - clk: mvebu - reorganize by SoC to remove built up #ifdefs - add clk flags per clock gate * tag 'seb_clk-3.11' of git://git.infradead.org/users/jcooper/linux: clk: mvebu: disintegrate obsolete file ARM: mvebu: move DT boards to SoC-centric clock init ARM: kirkwood: move DT boards to SoC-centric clock init ARM: dove: move DT boards to SoC-centric clock init clk: mvebu: add Armada XP SoC-centric clock init clk: mvebu: add Armada 370 SoC-centric clock init clk: mvebu: add Kirkwood SoC-centric clock init clk: mvebu: add Dove SoC-centric clock init clk: mvebu: add common clock functions for core clk and clk gating clk: mvebu: introduce per-clock-gate flags
2013-05-31Merge tag 'pcie-3.11-2' of git://git.infradead.org/users/jcooper/linux into ↵Olof Johansson
next/soc PCI-e driver for mvebu. * tag 'pcie-3.11-2' of git://git.infradead.org/users/jcooper/linux: pci: mvebu: fix return value check in mvebu_pcie_probe() arm: mvebu: PCIe support is now available on mvebu pci: PCIe driver for Marvell Armada 370/XP systems clk: mvebu: add more PCIe clocks for Armada XP clk: mvebu: create parent-child relation for PCIe clocks on Armada 370 of/pci: Add of_pci_parse_bus_range() function of/pci: Add of_pci_get_devfn() function of/pci: Provide support for parsing PCI DT ranges property Signed-off-by: Olof Johansson <olof@lixom.net>
2013-05-31clk: tegra: Use common of_clk_init functionPrashant Gaikwad
Use common of_clk_init() function for clocks initialization. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by: Thierry Reding <thierry.reding@gmail.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-05-31clk: tegra114: correctly output clk_32kAlexandre Courbot
Tegra has a blink timer register that allows to modulate the clk_32k clock before outputting it. Since clk_32k is presented to the kernel as a fixed clock, make sure this register does not tamper with the clock frequency and that clk_32k is outputted as-is, similarly to what is done on t20 and t30. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-05-31clk: tegra: fix clk_out parents listPrashant Gaikwad
Number of parents for clk_out_2 and clk_out_3 was incorrectly set to clk_out1_parents. Even though it did not break anything since the size was same better to fix. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by: Thierry Reding <thierry.reding@gmail.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-05-31clk: Add TI-Nspire clock driversDaniel Tang
This patch adds a basic clock driver for the TI-Nspire calculator series. Changes from v1: * Removed filename in header comment * Removed unnecessary #undef EXTRACT statement Signed-off-by: Daniel Tang <dt.tangr@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: fixed $SUBJECT and changelog max width]
2013-05-30clk: mxs: Include clk mxs header fileFabio Estevam
Fix the following sparse warnings: drivers/clk/mxs/clk-imx28.c:72:5: warning: symbol 'mxs_saif_clkmux_select' was not declared. Should it be static? drivers/clk/mxs/clk-imx28.c:156:12: warning: symbol 'mx28_clocks_init' was not declared. Should it be static? Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: fixed $SUBJECT line]
2013-05-30clk: use platform_{get,set}_drvdata()Jingoo Han
Use the wrapper functions for getting and setting the driver data using platform_device instead of using dev_{get,set}_drvdata() with &pdev->dev, so we can directly pass a struct platform_device. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-05-30clk: mpc85xx: Update the compatible stringTang Yuantian
The compatible string of clock is changed from *-2 to *-2.0 on chassis 2. So updated it accordingly. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: improved $SUBJECT line]
2013-05-29clk: vt8500: Fix unbalanced spinlock in vt8500_dclk_set_rate()Tony Prisk
With the addition of a DVO clock, a bug is now evident in the vt8500 clock code: [ 0.290000] WARNING: at init/main.c:698 do_one_initcall+0x158/0x18c() [ 0.300000] initcall wm8505fb_driver_init+0x0/0xc returned with disabled int This is caused by an unbalanced spinlock in vt8500_dclk_set_rate(). Replace the second call to spin_lock_irqsave() with spin_unlock_irqrestore(). Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-05-29clk: sunxi: "cpu_data" is defined in header files of some architecturesGiacomo A. Catenazzi
In some architectures, the #define cpu_data is not a "macro-function", so the compiler will substitute the identifier with probably something wrong. Signed-off-by: Giacomo A. Catenazzi <cate@cateee.net> Signed-off-by: Emilio López <emilio@elopez.com.ar> [emilio@elopez.com.ar: use cpu_mux_data instead of this_cpu_data] Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-05-29clk: exynos5250: Add sclk_mpll to the parent list of mout_cpu clockTushar Behera
'mout_mpll' is added the list of parent clocks for 'mout_cpu'. 'mout_mpll' is an alias to the clock 'sclk_mpll'. Hence 'sclk_mpll' should be added to the list of parent clocks. This results in an error when cpufreq driver for EXYNOS5250 tries to set 'mout_mpll' as a parent for 'mout_cpu'. clk_set_parent: clk sclk_mpll can not be parent of clk mout_cpu Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-05-29clk: exynos5250: Update cpufreq related clocks for EXYNOS5250Tushar Behera
cpufreq driver for EXYNOS5250 is not a platform driver, hence we cannot currently pass the clock names through a device tree node. Instead, we need to make them available through a global alias. cpufreq driver for EXYNOS5250 requires four clocks - 'armclk', 'mout_cpu', 'mout_mpll' and 'mout_apll'. 'armclk' has already been defined with an alias, 'mout_cpu', 'mout_mpll' and 'mout_apll' are now defined with an alias. Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-05-29clk: si5351: Set initial clkout rate when defined in platform data.Marek Belisko
clock-frequency property from platform data was read but never used. Apply defined rate when clock is registered. Signed-off-by: Marek Belisko <marek.belisko@streamunlimited.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: add missing changelog] Cc: stable@kernel.org Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-05-29clk: si5351: Fix clkout rate computation.Marek Belisko
Rate was incorrectly computed because we read from wrong divider register. Signed-off-by: Marek Belisko <marek.belisko@streamunlimited.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> Cc: stable@kernel.org
2013-05-29clk: vt8500: Remove unnecessary divisor adjustment in vtwm_dclk_set_rate()Tony Prisk
The divisor adjustment code to ensure that a divisor is not rounded down, thereby giving a rate higher than requested, is unnecessary and in some instances results in the actual rate being much lower than requested due to rounding errors. The test is already performed in vtwm_dclk_round_rate(), which is always called when clk_set_rate is called. Due to rounding errors in the line: divisor = parent_rate / rate (clk-vt8500.c:160) we will sometimes end up adjusting the divisor twice - first in round_rate and then again in set_rate. This patch removes the test/adjustment in vtwm_dclk_set_rate. Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-05-29clk: vt8500: Add support for clocks on the WM8850 SoCsTony Prisk
The WM8850 has a different PLL clock to the previous versions. This patch adds support for the WM8850-style PLL clocks. Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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