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2014-09-04edac: altera: Add Altera SDRAM EDAC supportThor Thayer
This patch adds support for the CycloneV and ArriaV SDRAM controllers. Correction and reporting of SBEs, Panic on DBEs. There was a discussion thread on whether this driver should be an mfd driver or just make use of syscon, which is already a mfd. Ultimately, the decision to use a simple syscon interface was reached.[1] [1] https://lkml.org/lkml/2014/7/30/514 [dinguyen] Fixed Kconfig to have EDAC_ALTERA_MC as a tristate to prevent a build failure for allmodconfig. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Acked-by: Borislav Petkov <bp@suse.de> [dinguyen] cleaned up commit message Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2014-07-04ie31200_edac: Introduce the driverJason Baron
Add a driver for the E3-1200 series of Intel DRAM controllers, based on the following E3-1200 specs: http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200v3-vol-2-datasheet.html I've tested this on bad memory hardware, and observed correlating bad reads and uncorrected memory errors as reported by the driver. Tested against: CPU E3-1270 v3 @ 3.50GHz : 8086:0c08 (haswell) CPU E3-1270 V2 @ 3.50GHz : 8086:0158 (ivy bridge) CPU E31270 @ 3.40GHz : 8086:0108 (sandy bridge) Signed-off-by: Jason Baron <jbaron@akamai.com> Link: http://lkml.kernel.org/r/95c83e80dd40b5377e8bb206285c5d95ac623872.1403818526.git.jbaron@akamai.com [ Boris: realign defines ] Signed-off-by: Borislav Petkov <bp@suse.de>
2013-02-25ghes_edac: Register at EDAC core the BIOS reportMauro Carvalho Chehab
Register GHES at EDAC MC core, in order to avoid other drivers to also handle errors and mangle with error data. The edac core will warrant that just one driver will be used, so the first one to register (BIOS first) will be the one that will be reporting the hardware errors. For now, the EDAC driver does nothing but to register at the EDAC core, preventing the hardware-driven mechanism to interfere with GHES. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
2012-12-12MIPS: Cavium: Add EDAC support.Ralf Baechle
Drivers for EDAC on Cavium. Supported subsystems are: o CPU primary caches. These are parity protected only, so only error reporting. o Second level cache - ECC protected, provides SECDED. o Memory: ECC / SECDEC if used with suitable DRAM modules. The driver will will only initialize if ECC is enabled on a system so is safe to run on non-ECC memory. o PCI: Parity error reporting Since it is very hard to test this sort of code the implementation is very conservative and uses polling where possible for now. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Reviewed-by: Borislav Petkov <borislav.petkov@amd.com>
2012-06-27edac: add support for Calxeda highbank L2 cache eccRob Herring
Add support for L2 ECC on Calxeda highbank platform. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
2012-06-27edac: add support for Calxeda highbank memory controllerRob Herring
Add support for memory controller on Calxeda Highbank platforms. Highbank platforms support a single 4GB mini-DIMM with 1-bit correction and 2-bit detection. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
2011-11-01edac: sb_edac: Add it to the building systemMauro Carvalho Chehab
Some changes on it were required due to changeset cd90cc84c6bf0, that changed the glue with the MCE logic. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
2011-11-01i7core_edac: Drop the edac_mce facilityBorislav Petkov
Remove edac_mce pieces and use the normal MCE decoder notifier chain by retaining the same functionality with considerably less code. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
2011-03-10drivers/edac: provide support for tile architectureChris Metcalf
Add tile support for the EDAC driver, which provides unified system error (memory, PCI, etc.) reporting. For now, the TILEPro port reports memory correctable error (CE) only. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2010-11-22EDAC: Remove deprecated kbuild goal definitionsTracey Dent
Change EDAC's Makefile to use <modules>-y instead of <modules>-objs because -objs is deprecated and not mentioned in Documentation/kbuild/makefiles.txt. [bp: Fixup commit message] [bp: Fixup indentation] Signed-off-by: Tracey Dent <tdent48227@gmail.com> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
2010-10-24Merge branch 'devel' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/edac * 'devel' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/edac: (25 commits) i7300_edac: Properly initialize per-csrow memory size V4L/DVB: i7300_edac: better initialize page counts MAINTAINERS: Add maintainer for i7300-edac driver i7300-edac: CodingStyle cleanup i7300_edac: Improve comments i7300_edac: Cleanup: reorganize the file contents i7300_edac: Properly detect channel on CE errors i7300_edac: enrich FBD error info for corrected errors i7300_edac: enrich FBD error info for fatal errors i7300_edac: pre-allocate a buffer used to prepare err messages i7300_edac: Fix MTR x4/x8 detection logic i7300_edac: Make the debug messages coherent with the others i7300_edac: Cleanup: remove get_error_info logic i7300_edac: Add a code to cleanup error registers i7300_edac: Add support for reporting FBD errors i7300_edac: Properly detect the type of error correction i7300_edac: Detect if the device is on single mode i7300_edac: Adds detection for enhanced scrub mode on x8 i7300_edac: Clear the error bit after reading i7300_edac: Add error detection code for global errors ...
2010-10-21EDAC, MCE: Rename filesBorislav Petkov
Drop "edac_" string from the filenames since they're prefixed with edac/ in their pathname anyway. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
2010-10-21EDAC, MCE: Rework MCE injectionBorislav Petkov
Add sysfs injection facilities for testing of the MCE decoding code. Remove large parts of amd64_edac_dbg.c, as a result, which did only NB MCE injection anyway and the new injection code supports that functionality already. Add an injection module so that MCE decoding code in production kernels like those in RHEL and SLES can be tested. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
2010-08-30i7300_edac: start a driver for i7300 chipset (Clarksboro)Mauro Carvalho Chehab
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
2010-05-10edac_mce: Add an interface driver to report mce errors via edacMauro Carvalho Chehab
edac_mce module is an interface module that gets mcelog data and forwards to any registered edac module that expects to receive data via mce. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
2010-05-10i7core_edac: Add an EDAC memory controller driver for Nehalem chipsetsMauro Carvalho Chehab
This driver is meant to support i7 core/i7core extreme desktop processors and Xeon 35xx/55xx series with integrated memory controller. It is likely that it can be expanded in the future to work with other processor series based at the same Memory Controller design. For now, it has just a few MCH status reads. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
2009-10-02x86: EDAC: carve out AMD MCE decoding logicBorislav Petkov
This converts the MCE decoding logic into a standalone config option which can be built-in or a module, the first one being the default for MCEs happening early on in the boot process. This, beyond being separated in a cleaner way, also saves RAM by making the decoding logic modular. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Andi Kleen <andi@firstfloor.org> LKML-Reference: <20091002133148.GD28682@aftab> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-10-02x86: EDAC: MCE: Fix MCE decoding callback logicIngo Molnar
Make decoding of MCEs happen only on AMD hardware by registering a non-default callback only on CPU families which support it. While looking at the interaction of decode_mce() with the other MCE code i also noticed a few other things and made the following cleanups/fixes: - Fixed the mce_decode() weak alias - a weak alias is really not good here, it should be a proper callback. A weak alias will be overriden if a piece of code is built into the kernel - not good, obviously. - The patch initializes the callback on AMD family 10h and 11h. - Added the more correct fallback printk of: No support for human readable MCE decoding on this CPU type. Transcribe the message and run it through 'mcelog --ascii' to decode. On CPUs that dont have a decoder. - Made the surrounding code more readable. Note that the callback allows us to have a default fallback - without having to check the CPU versions during the printout itself. When an EDAC module registers itself, it can install the decode-print function. (there's no unregister needed as this is core code.) version -v2 by Borislav Petkov: - add K8 to the set of supported CPUs - always build in edac_mce_amd since we use an early_initcall now - fix checkpatch warnings Signed-off-by: Borislav Petkov <borislav.petkov@amd.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Andi Kleen <andi@firstfloor.org> LKML-Reference: <20091001141432.GA11410@aftab> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-09-24edac: i3200 memory controller driverJason Uhlenkott
A driver for the Intel 3200 and 3210 memory controllers. It has only had light testing so far, and currently makes no attempt to decode error addresses at anything finer than csrow granularity. Signed-off-by: Jason Uhlenkott <juhlenko@akamai.com> Signed-off-by: Doug Thompson <dougthompson@xmission.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: "H. Peter Anvin" <hpa@zytor.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-09-14EDAC: move MCE error descriptions to EDAC coreBorislav Petkov
This is in preparation of adding AMD-specific MCE decoding functionality to the EDAC core. The error decoding macros originate from the AMD64 EDAC driver albeit in a simplified and cleaned up version here. While at it, add macros to generate the error description strings and use them in the error type decoders directly which removes a bunch of code and makes the decoding functions much more readable. Also, fix strings and shorten macro names. Remove superfluous htlink_msgs. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
2009-06-18edac: add CPC925 Memory Controller driverHarry Ciao
Introduce IBM CPC925 EDAC driver, which makes use of ECC, CPU and HyperTransport Link error detections and corrections on the IBM CPC925 Bridge and Memory Controller. [akpm@linux-foundation.org: cleanup] Signed-off-by: Harry Ciao <qingtao.cao@windriver.com> Cc: Doug Thompson <norsk5@yahoo.com> Cc: Michael Ellerman <michael@ellerman.id.au> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Kumar Gala <galak@gate.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-06-10amd64_edac: add module registration routinesDoug Thompson
Also, link into Kbuild by adding Kconfig and Makefile entries. Borislav: - Kconfig/Makefile splitting - use zero-sized arrays for the sysfs attrs if not enabled - rename sysfs attrs to more conform values - shorten CONFIG_ names - make multiple structure members assignment vertically aligned - fix/cleanup comments - fix function return value patterns - fix err labels - fix a memleak bug caught by Ingo - remove the NUMA dependency and use num_k8_northbrides for initializing a driver instance per NB. - do not copy the pvt contents into the mci struct in amd64_init_2nd_stage() and save it in the mci->pvt_info void ptr instead. - cleanup debug calls - simplify amd64_setup_pci_device() Reviewed-by: Mauro Carvalho Chehab <mchehab@redhat.com> Signed-off-by: Doug Thompson <dougthompson@xmission.com> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
2009-05-29edac: AMD8111 & AMD8131 Kconfig fixupHarry Ciao
The amd8111_edac.c driver will fail allmodconfig on architectures other than PPC, introduce Kconfig dependency to avoid this, since both AMD8111 and AMD8131 chips are only adopted on Maple so far. Signed-off-by: Harry Ciao <qingtao.cao@windriver.com> Cc: Doug Thompson <norsk5@yahoo.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-04-02edac: new ppc4xx driver moduleGrant Erickson
This adds support for an EDAC memory controller adaptation driver for the "ibm,sdram-4xx-ddr2" ECC controller realized in the AMCC PowerPC 405EX[r]. At present, this driver has been developed and tested against the controller realization in the AMCC PPC405EX[r] on the AMCC Kilauea and Haleakala boards (256 MiB w/o ECC memory soldered onto the board) and a proprietary board based on those designs (128 MiB ECC memory, also soldered onto the board). In the future, dynamic feature detection and handling needs to be added for the other realizations of this controller found in the 440SP, 440SPe, 460EX, 460GT and 460SX. Eventually, this driver will likely be evolved and adapted to the above variant realizations of this controller as well as broken apart to handle the other known ECC-capable controllers prevalent in other PPC4xx processors: - IBM SDRAM (405GP, 405CR and 405EP) "ibm,sdram-4xx" - IBM DDR1 (440GP, 440GX, 440EP and 440GR) "ibm,sdram-4xx-ddr" - Denali DDR1/DDR2 (440EPX and 440GRX) "denali,sdram-4xx-ddr2" [akpm@linux-foundation.org: coding-style fixes] Signed-off-by: Grant Erickson <gerickson@nuovations.com> Signed-off-by: Doug Thompson <dougthompson@xmission.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-01-06edac: driver for i5400 MCH (Seaburg)Mauro Carvalho Chehab
EDAC driver for i5400 MCH (Seaburg) This driver adds support for i5400 MCH chipset. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> Signed-off-by: Ben Woodard <woodard@redhat.com> Cc: Doug Thompson <norsk5@yahoo.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-10-30edac x38: new MC driver moduleHitoshi Mitake
I wrote a new module for Intel X38 chipset. This chipset is very similar to Intel 3200 chipset, but there are some different points, so I copyed i3200_edac.c and modified. This is Intel's web page describing this chipset. http://www.intel.com/Products/Desktop/Chipsets/X38/X38-overview.htm I've tested this new module with broken memory, and it seems to be working well. Signed-off-by: Hitoshi Mitake <mitake@clustcom.com> Signed-off-by: Doug Thompson <dougthompson@xmission.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-07-25edac: i5100 new intel chipset driverArthur Jones
Preliminary support for the Intel 5100 MCH. CE and UE errors are reported along with the current DIMM label information and other memory parameters. Reasons why this is preliminary: 1) This chip has 2 independent memory controllers which, for best perforance, use interleaved accesses to the DDR2 memory. This architecture does not map very well to the current edac data structures which depend on symmetric channel access to the interleaved data. Without core changes, the best I could do for now is to map both memory controllers to different csrows (first all ranks of controller 0, then all ranks of controller 1). Someone much more familiar with the edac core than I will probably need to come up with a more general data structure to handle the interleaving and de-interleaving of the two memory controllers. 2) I have not yet tackled the de-interleaving of the rank/controller address space into the physical address space of the CPU. There is nothing fundamentally missing, it is just ending up to be a lot of code, and I'd rather keep it separate for now, esp since it doesn't work yet... 3) The code depends on a particular i5100 chip select to DIMM mainboard chip select mapping. This mapping seems obvious to me in order to support dual and single ranked memory, but it is not unique and DIMM labels could be wrong on other mainboards. There is no way to query this mapping that I know of. 4) The code requires that the i5100 is in 32GB mode. Only 4 ranks per controller, 2 ranks per DIMM are supported. I do not have hardware (nor do I expect to have hardware anytime soon) for the 48GB (6 ranks per controller) mode. 5) The serial presence detect code should be broken out into a "real" i2c driver so that decode-dimms.pl can work. Signed-off-by: Arthur Jones <ajones@riverbed.com> Signed-off-by: Doug Thompson <dougthompson@xmission.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-02-07drivers-edac: add marvell mv64x60 driverDave Jiang
Marvell mv64x60 SoC support for EDAC. Used on PPC and MIPS platforms. Development and testing done on PPC Motorola prpmc2800 ATCA board. [akpm@linux-foundation.org: make mv64x60_ctl_name static] Signed-off-by: Dave Jiang <djiang@mvista.com> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk Signed-off-by: Douglas Thompson <dougthompson@xmission.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-02-07drivers-edac: add freescale mpc85xx driverDave Jiang
EDAC chip driver support for Freescale MPC85xx platforms. PPC based. Signed-off-by: Dave Jiang <djiang@mvista.com> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk Signed-off-by: Doug Thompson <dougthompson@xmission.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-02-07drivers-edac: add Cell MC driverBenjamin Herrenschmidt
Adds driver for the Cell memory controller when used without a Hypervisor such as on the IBM Cell blades. There might still be some improvements to do to this such as finding if it's possible to properly obtain more details about the address of the error but it's good enough already to report CE counts which is our main priority at the moment. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk Signed-off-by: Doug Thompson <dougthompson@xmission.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-07-19drivers/edac: new i82975x driverRanganathan Desikan
New EDAC driver for the i82975x memory controller chipset Used on ASUS motherboards [akpm@linux-foundation.org: fix multiple coding-style bloopers] Signed-off-by: <arvind@acarlab.com> Signed-off-by: Ranganathan Desikan <rdesikan@jetzbroadband.com> Signed-off-by: Doug Thompson <dougthompson@xmission.com> Cc: Greg KH <greg@kroah.com> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-07-19drivers/edac: new pasemi driverEgor Martovetsky
NEW EDAC driver for the memory controllers on PA Semi PA6T-1682M. Changes since last submission: * Rebased on top of 2.6.22-rc4-mm2 with the EDAC changes merged there. * Minor checkpatch.pl cleanups * Renamed ctl_name * Added dev_name * edac_mc.h -> edac_core.h [akpm@linux-foundation.org: make printk more informative] Cc: Alan Cox alan@lxorguk.ukuu.org.uk Signed-off-by: Egor Martovetsky <egor@pasemi.com> Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Doug Thompson <dougthompson@xmission.com Cc: Greg KH <greg@kroah.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-07-19drivers/edac: updated PCI monitoringDave Jiang
Moving PCI to a per-instance device model This should include the correct sysfs setup as well. Please review. Signed-off-by: Dave Jiang <djiang@mvista.com> Signed-off-by: Douglas Thompson <dougthompson@xmission.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-07-19drivers/edac: new inte 30x0 MC driverJason Uhlenkott
Here's a driver for the Intel 3000 and 3010 memory controllers, relative to today's Sourceforge code drop. This has only had light testing (I've yet to actually see it handle a memory error) but it detects my hardware correctly. Signed-off-by: Jason Uhlenkott <juhlenko@akamai.com> Signed-off-by: Douglas Thompson <dougthompson@xmission.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-07-19drivers/edac: add new nmi rescanDave Jiang
Provides a way for NMI reported errors on x86 to notify the EDAC subsystem pending ECC errors by writing to a software state variable. Here's the reworked patch. I added an EDAC stub to the kernel so we can have variables that are in the kernel even if EDAC is a module. I also implemented the idea of using the chip driver to select error detection mode via module parameter and eliminate the kernel compile option. Please review/test. Thx! Also, I only made changes to some of the chipset drivers since I am unfamiliar with the other ones. We can add similar changes as we go. Signed-off-by: Dave Jiang <djiang@mvista.com> Signed-off-by: Douglas Thompson <dougthompson@xmission.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-07-19drivers/edac: new i82443bxgz MC driverTim Small
This is a NEW EDAC Memory Controller driver for the 440BX chipset (I82443BXGX) created and submitted by Timm Small Signed-off-by: Tim Small <tim@buttersideup.com> Signed-off-by: Douglas Thompson <dougthompson@xmission.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-07-19drivers/edac: new intel 5000 MC driverEric Wollesen
Eric Wollesen ported the Bluesmoke Memory Controller driver (written by Doug Thompson) for the Intel 5000X/V/P (Blackford/Greencreek) chipset to the in kernel EDAC model. This patch incorporates the module for the 5000X/V/P chipset family [m.kozlowski@tuxland.pl: edac i5000 parenthesis balance fix] Signed-off-by: Eric Wollesen <ericw@xmtp.net> Signed-off-by: Doug Thompson <norsk5@xmission.com> Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-07-19drivers/edac: add edac_device classDouglas Thompson
This patch adds the new 'class' of object to be managed, named: 'edac_device'. As a peer of the 'edac_mc' class of object, it provides a non-memory centric view of an ERROR DETECTING device in hardware. It provides a sysfs interface and an abstraction for varioius EDAC type devices. Multiple 'instances' within the class are possible, with each 'instance' able to have multiple 'blocks', and each 'block' having 'attributes'. At the 'block' level there are the 'ce_count' and 'ue_count' fields which the device driver can update and/or call edac_device_handle_XX() functions. At each higher level are additional 'total' count fields, which are a summation of counts below that level. This 'edac_device' has been used to capture and present ECC errors which are found in a a L1 and L2 system on a per CORE/CPU basis. Signed-off-by: Douglas Thompson <dougthompson@xmission.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-07-19drivers/edac: split out functions to unique filesDouglas Thompson
This is a large patch to refactor the original EDAC module in the kernel and to break it up into better file granularity, such that each source file contains a given subsystem of the EDAC CORE. Originally, the EDAC 'core' was contained in one source file: edac_mc.c with it corresponding edac_mc.h file. Now, there are the following files: edac_module.c The main module init/exit function and other overhead edac_mc.c Code handling the edac_mc class of object edac_mc_sysfs.c Code handling for sysfs presentation edac_pci_sysfs.c Code handling for PCI sysfs presentation edac_core.h CORE .h include file for 'edac_mc' and 'edac_device' drivers edac_module.h Internal CORE .h include file This forms a foundation upon which a later patch can create the 'edac_device' class of object code in a new file 'edac_device.c'. Signed-off-by: Douglas Thompson <dougthompson@xmission.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2006-01-18[PATCH] EDAC: core EDAC support codeAlan Cox
This is a subset of the bluesmoke project core code, stripped of the NMI work which isn't ready to merge and some of the "interesting" proc functionality that needs reworking or just has no place in kernel. It requires no core kernel changes except the added scrub functions already posted. The goal is to merge further functionality only after the core code is accepted and proven in the base kernel, and only at the point the upstream extras are really ready to merge. From: doug thompson <norsk5@xmission.com> This converts EDAC to sysfs and is the final chunk neccessary before EDAC has a stable user space API and can be considered for submission into the base kernel. Signed-off-by: Alan Cox <alan@redhat.com> Signed-off-by: Adrian Bunk <bunk@stusta.de> Signed-off-by: Jesper Juhl <jesper.juhl@gmail.com> Signed-off-by: doug thompson <norsk5@xmission.com> Signed-off-by: Pavel Machek <pavel@suse.cz> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>