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path: root/drivers/gpu/drm/i915/i915_suspend.c
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2011-01-11drm/i915: cleanup rc6 codeJesse Barnes
Cleanup several aspects of the rc6 code: - misnamed intel_disable_clock_gating function (was only about rc6) - remove commented call to intel_disable_clock_gating - rc6 enabling code belongs in its own function (allows us to move the actual clock gating enable call back into restore_state) - allocate power & render contexts up front, only free on unload (avoids ugly lazy init at rc6 enable time) Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> [ickle: checkpatch cleanup] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-11drm/i915: fix rc6 enabling around suspend/resumeJesse Barnes
Enabling RC6 implies setting a graphics context. Make sure we do that only after the ring has been enabled, otherwise our ring commands will hang. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-11drm/i915: re-enable rc6 support for Ironlake+Jesse Barnes
Re-enable rc6 support on Ironlake for power savings. Adds a debugfs file to check current RC state, adds a missing workaround for Ironlake MI_SET_CONTEXT instructions, and renames MCHBAR_RENDER_STANDBY to RSTDBYCTL to match the docs. Keep RC6 and the power context disabled on pre-ILK. It only seems to hang and doesn't save any power. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-20drm/i915: Undo "Uncouple render/power ctx before suspending"Chris Wilson
Manaul revert of 0cdab21f9a1fca50dd27e488839f5a6578e333b2, just to remove the call to disable the clock gatings and powerctx before suspend. Peter Clifton bisected a suspend failure on his gme45 and found this to be the culprit. As this was intended to be a fix for a similar suspend failure for Ironlake (it didn't work), undoing this patch should have no other side-effects. Reported-and-tested-by: Peter Clifton <pcjc2@cam.ac.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-18drm/i915: dynamic render p-state support for Sandy BridgeJesse Barnes
Add an interrupt handler for switching graphics frequencies and handling PM interrupts. This should allow for increased performance when busy and lower power consumption when idle. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05drm/i915: Uncouple render/power ctx before suspendingChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-25drm/i915: Only save and restore fences for UMSChris Wilson
With KMS, we can simply relinquish the fence when we idle the GPU and reassign it upon first use. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-21drm/i915: Only save/restore cursor regs if !KMSChris Wilson
Under KMS, restoring the cursor is handled upon modeswitch in order to avoid enabling an undefined set of registers. At the moment, the cursor is restored before the aperture and modes are fully setup causing some invalid access during resume, such as: PGTBL_ER: 0x00040000 Invalid GTT entry during Cursor Fetch Fix this by only performing cursor register save/restore under UMS where it is done in the correct sequence. Reported-by: Arkadiusz Miskiewicz <arekm@maven.pl> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-03i915: reprogram power monitoring registers on resumeKyle McMartin
Fixes issue where i915_gfx_val was reporting values several orders of magnitude higher than physically possible (without leaving scorch marks on my thighs at least.) Signed-off-by: Kyle McMartin <kyle@redhat.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21drm/i915: INTEL_INFO->gen supercedes i8xx, i9xx, i965gChris Wilson
Avoid confusion between i965g meaning broadwater and the gen4+ chipset families. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21Merge branch 'drm-intel-fixes' into HEADChris Wilson
Conflicts: drivers/char/agp/intel-agp.c drivers/gpu/drm/i915/intel_crt.c
2010-09-18drm/i915: use GMBUS to manage i2c linksChris Wilson
Use the GMBUS interface rather than direct bit banging to grab the EDID over DDC (and for other forms of auxiliary communication with external display controllers). The hope is that this method will be much faster and more reliable than bit banging for fetching EDIDs from buggy monitors or through switches, though we still preserve the bit banging as a fallback in case GMBUS fails. Based on an original patch by Jesse Barnes. Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-17drm/i915: Fix Sandybridge fence registersChris Wilson
With 5 places to update when adding handling for fence registers, it is easy to overlook one or two. Correct that oversight, but fence management should be improved before a new set of registers is added. Bugzilla: https://bugs.freedesktop.org/show_bug?id=30199 Original patch by: Yuanhan Liu <yuanhan.liu@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
2010-08-21drm/i915/suspend: s/IS_IRONLAKE/HAS_PCH_SPLIT/Chris Wilson
For the shared paths on the next generation chipsets. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-21drm/i915/suspend: Flush register writes before busy-waiting.Chris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-01drm/i915: Add frame buffer compression support on Ironlake mobileZhao Yakui
About 0.2W power can be saved on one HP laptop. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-04-12drm/i915: Only save/restore FBC on the platform that supports FBCZhao Yakui
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2010-02-22drm/i915: Deobfuscate the render p-state obfuscationMatthew Garrett
The ironlake render p-state support includes some rather odd variable names. Clean them up in order to improve the readability of the code. Signed-off-by: Matthew Garrett <mjg@redhat.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-02-22drm/i915: add dynamic performance control support for IronlakeJesse Barnes
Ironlake (and 965GM, which this patch doesn't support) supports a hardware performance and power management feature that allows it to adjust to changes in GPU load over time with software help. The goal if this is to maximize performance/power for a given workload. This patch enables that feature, which is also a requirement for supporting Intelligent Power Sharing, a feature which allows for dynamic budgeting of power between the CPU and GPU in Arrandale platforms. Tested-by: ykzhao <yakui.zhao@intel.com> [anholt: Resolved against the irq handler loop removal] Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-01-06drm/i915: Fix RC6 suspend/resumeAndrew Lutomirski
We restored RC6 twice on resume, even with modesetting off. Instead, only restore it once and skip RC6 initialization entirely in non-KMS mode. Signed-off-by: Andy Lutomirski <luto@mit.edu> Tested-by: Jeff Chua <jeff.chua.linux@gmail.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-12-10Merge remote branch 'anholt/drm-intel-next' into drm-linusDave Airlie
Pull more Intel changes in, especially one to init the GTT properly
2009-12-08drm/i915: restore render clock gating on resumeAndrew Lutomirski
Rather than restoring just a few clock gating registers on resume, just reinitialize the whole thing. Signed-off-by: Andy Lutomirski <luto@mit.edu> [anholt: Fixed up for RC6 support landed since the patch was written] Signed-off-by: Eric Anholt <eric@anholt.net>
2009-12-08Merge remote branch 'anholt/drm-intel-next' into drm-linusDave Airlie
This merges the upstream Intel tree and fixes up numerous conflicts due to patches merged into Linus tree later in -rc cycle. Conflicts: drivers/char/agp/intel-agp.c drivers/gpu/drm/drm_dp_i2c_helper.c drivers/gpu/drm/i915/i915_irq.c drivers/gpu/drm/i915/i915_suspend.c
2009-12-07drm/i915: Fix product names and #definesAdam Jackson
IGD* isn't a useful name. Replace with the codenames, as sourced from pci.ids. Signed-off-by: Adam Jackson <ajax@redhat.com> [anholt: Fixed up for merge with pineview/ironlake changes] Signed-off-by: Eric Anholt <eric@anholt.net>
2009-12-01drm/i915: Fix DDC on some systems by clearing BIOS GMBUS setup.Eric Anholt
This is a sync of a fix I made in the old UMS code. If the BIOS uses the GMBUS and doesn't clear that setup, then our bit-banging I2C can fail, leading to monitors not being detected. Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-12drm/i915: Add more registers save/restore for Ironlake suspendZhenyu Wang
Add more display registers save/restore to fix unstable issues during S4 testing on Ironlake. And DPLL_B_MD should not be restored on Ironlake. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-05drm/i915: add render standby supportJesse Barnes
Render standy allows the GPU to power down the render unit when idle. In order for this to work, it needs a page of graphics memory to save state. This patch allocates that page and enables the feature on supported chipsets. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-10-23drm/i915: Ironlake suspend/resume supportZhenyu Wang
This adds registers save/restore for Ironlake to make suspend work. Signed-off-by: Guo, Chaohong <chaohong.guo@intel.com> [zhenyuw: some code re-orgnization, and add more save/restore for FDI link and transcoder registers, also fix palette register for Ironlake] Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-10-15drm/i915: save/restore BLC histogram control reg across suspend/resumeJesse Barnes
Turns out some machines, like the ThinkPad X40 don't come back if you don't save/restore this register. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-10-13drm/i915: Save and restore the GM45 FBC regs on suspend and resume.Jesse Barnes
This hasn't fixed the regressions we were testing against, but clearly should be required. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-09-17drm/i915: Refactor save/restore codeBen Gamari
We move the display-specific code into it's own functions, called from the general GPU state save/restore functions. This will be needed later by the GPU reset code. Signed-off-by: Ben Gamari <bgamari.foss@gmail.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2009-09-04drm/i915: add dynamic clock frequency controlJesse Barnes
There are several sources of unnecessary power consumption on Intel graphics systems. The first is the LVDS clock. TFTs don't suffer from persistence issues like CRTs, and so we can reduce the LVDS refresh rate when the screen is idle. It will be automatically upclocked when userspace triggers graphical activity. Beyond that, we can enable memory self refresh. This allows the memory to go into a lower power state when the graphics are idle. Finally, we can drop some clocks on the gpu itself. All of these things can be reenabled between frames when GPU activity is triggered, and so there should be no user visible graphical changes. Signed-off-by: Jesse Barnes <jesse.barnes@intel.com> Signed-off-by: Matthew Garrett <mjg@redhat.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-08-05drm/i915: Fix read outside array bounds in restoring the SWF10 range.Roel Kluin
dev_priv->saveSWF1 is a 16 element array, but this reads up to index 22, and restored values from the wrong registers. Signed-off-by: Roel Kluin <roel.kluin@gmail.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-07-10drm/i915: Avoid saving/restore the modesetting registers twice in KMS modeZhao Yakui
In KMS mode we now use the normal mode-setting paths to set the modes back to the current configuration, so we don't need to also run the more limited non-KMS implementation of modesetting for resume. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-06-18drm/i915: Add Display Port supportKeith Packard
Signed-off-by: Keith Packard <keithp@keithp.com>
2009-06-04drm/i915: Save/restore cursor state on suspend/resume.Eric Anholt
This may fix cursor corruption in X on resume, which would persist until the cursor was hidden and then shown again. V2: Also include the cursor control regs. Signed-off-by: Eric Anholt <eric@anholt.net> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2009-04-30drm/i915: save/restore fence registers across suspend/resumeKeith Packard
This makes software fallbacks not do tiling wrong on i965 and later after resume. It also should fix 945 performance reduction after resume which would have disabled tiling without causing any visible effect. Signed-off-by: Keith Packard <keithp@keithp.com> [anholt: Fixed up the 915 case to not save/restore the new regs] Signed-off-by: Eric Anholt <eric@anholt.net>
2009-03-10drm/i915: Don't restore palettes through VGA registers.Pierre Willenbrock
The VGA registers just hit the pipe registers that we already set through MMIO. This fixes strange colors on resume. Signed-off-by: Pierre Willenbrock <pierre@pirsoft.de> Signed-off-by: Eric Anholt <eric@anholt.net>
2008-11-26drm/i915: Save/restore HWS_PGA on suspend/resumePeng Li
It fixes suspend/resume failure of xf86-video-intel dri2 branch. As dri2 branch doesn't call I830DRIResume() to restore hardware status page anymore, we need to preserve this register across suspend/resume. Signed-off-by: Peng Li <peng.li@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-11i915: Save/restore MCHBAR_RENDER_STANDBY on GM965/GM45Keith Packard
This register is set by the 2D driver to prevent lockups, and so it needs to be preserved across suspend/resume too. This makes my X200s work. Signed-off-by: Keith Packard <keithp@keithp.com> Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Dave Airlie <airlied@linux.ie>
2008-10-18new chip name is GM45Jesse Barnes
Author: Zhenyu Wang <zhenyu.z.wang@intel.com> i915: official name for GM45 chipset Signed-off-by: Zhenyu Wang <zhenyu.z.wang@intel.com> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-10-18separate i915 suspend/resume functions into their own fileJesse Barnes
[Patch against drm-next. Consider this a trial balloon for our new Linux development model.] This is a big chunk of code. Separating it out makes it easier to change without churn on the main i915_drv.c file (and there will be churn as we fix bugs and add things like kernel mode setting). Also makes it easier to share this file with BSD. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Dave Airlie <airlied@redhat.com>