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path: root/drivers/gpu/drm/i915/intel_pm.c
AgeCommit message (Expand)Author
2014-01-27drm/i915: move module parameters into a struct, in a new fileJani Nikula
2014-01-27drm/i915: We implement WaDisableRCCUnitClockGating:snbVille Syrjälä
2014-01-27drm/i915: WaApplyL3ControlAndL3ChickenMode isn't applicable for VLVVille Syrjälä
2014-01-27drm/i915: We implement WaDisableL3CacheAging:vlvVille Syrjälä
2014-01-27drm/i915: WaPsdDispatchEnable seems to be another name for WaDisablePSDDualDi...Ville Syrjälä
2014-01-27drm/i915: We implement WaDisableL3Bank2xClockGate:vlvVille Syrjälä
2014-01-25drm/i915: Fix FBC1 enable messageVille Syrjälä
2014-01-25drm/i915: Don't preserve DPFC_CONTROL bits ILK/SNBVille Syrjälä
2014-01-25drm/i915: Actually write the correct bits to DPFC_CONTROL on CTGVille Syrjälä
2014-01-25drm/i915: Use 1/2 compression ratio limit for 16bpp on FBC2Ville Syrjälä
2014-01-25drm/i915: Improve FBC plane defines a bitVille Syrjälä
2014-01-25drm/i915: Don't set DPFC_HT_MODIFY bit on CTG/ILK/SNBVille Syrjälä
2014-01-25drm/i915: Don't set persistent FBC mode on ILK/SNBVille Syrjälä
2014-01-25drm/i915: Don't write IVB_FBC_RT_BASEVille Syrjälä
2014-01-25Merge branch 'topic/ppgtt' into drm-intel-next-queuedDaniel Vetter
2014-01-24drm/i915: Don't use i915_preliminary_hw_support to mean pre-productionDamien Lespiau
2014-01-16Merge commit origin/master into drm-intel-nextDaniel Vetter
2014-01-10drm/i915: Fix 915GM self-refresh enable/disableVille Syrjälä
2014-01-10drm/i915: i830M has watermarks like i855Daniel Vetter
2014-01-10drm/i915: Drop I915_ prefix from HAS_FBCDaniel Vetter
2014-01-08drm/i915: use crtc_htotal when calculating ilk watermarksJesse Barnes
2014-01-07drm/i915: Simplify watermark/init_clock_gating setupVille Syrjälä
2014-01-07drm/i915: Enable watermarks for BDWVille Syrjälä
2014-01-07drm/i915: Fix watermark code for BDWVille Syrjälä
2013-12-18Merge commit drm-intel-fixes into topic/ppgttDaniel Vetter
2013-12-18drm/i915: Make pin count per VMABen Widawsky
2013-12-17drm/i915: s/haswell_update_wm/ilk_update_wm/Imre Deak
2013-12-17drm/i915: simplify platform specific code in hsw_write_wm_valuesImre Deak
2013-12-17drm/i915: Try to fix the messy IVB sprite scaling workaroundVille Syrjälä
2013-12-17drm/i915: Move ILK/SNB/IVB over to the HSW WM codeVille Syrjälä
2013-12-17drm/i915: Disable LP1+ watermarks safely in initVille Syrjälä
2013-12-17drm/i915: Linetime watermarks are a HSW featureVille Syrjälä
2013-12-17drm/i915: Disable FBC WM on ILK, and disable LP2+ when FBC is enabledVille Syrjälä
2013-12-17drm/i915: Don't merge LP1+ watermarks on ILK/SNB/IVB when multiple pipes are ...Ville Syrjälä
2013-12-17drm/i915: Fix LP1+ watermark disabling ILKVille Syrjälä
2013-12-17drm/i915: Fix LP1 sprite watermarks for ILK/SNBVille Syrjälä
2013-12-17drm/i915: Avoid computing invalid WM levels when sprites/scaling is enabledVille Syrjälä
2013-12-17drm/i915: Add ILK/SNB/IVB WM latency field supportVille Syrjälä
2013-12-17drm/i915: Add IVB DDB partitioning controlVille Syrjälä
2013-12-17drm/i915: Use IS_VALLEYVIEW() to test the is_valleyview flagDamien Lespiau
2013-12-13drm/i915: get a PC8 reference when enabling the power wellPaulo Zanoni
2013-12-13drm/i915/bdw: Implement ff workaroundsBen Widawsky
2013-12-13drm/i915/bdw: Force all Data Cache Data Port access to be Non-CoherentBen Widawsky
2013-12-12drm/i915: Rework the FBC interval/stall stuff a bitVille Syrjälä
2013-12-12drm/i915: FBC_CONTROL2 is gen4 onlyVille Syrjälä
2013-12-12drm/i915: Gen2 FBC1 CFB pitch wants 32B unitsVille Syrjälä
2013-12-12drm/i915: touch VGA MSR after we enable the power wellPaulo Zanoni
2013-12-12drm/i915: extract hsw_power_well_post_{enable, disable}Paulo Zanoni
2013-12-12Merge tag 'drm-intel-fixes-2013-12-11' of git://people.freedesktop.org/~danve...Dave Airlie
2013-12-12Merge branch 'bdw-fixes' of git://people.freedesktop.org/~danvet/drm-intel in...Dave Airlie
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