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2011-02-01drm/i915: Trivial spelling mistake 'assertiing'Chris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-31drm/i915: Suppress spurious vblank interruptsChris Wilson
Hugh Dickins found that characters in xterm were going missing and oft delayed. Being the curious type, he managed to associate this with the new high-precision vblank patches; disabling these he found, restored the orderliness of his characters. The oddness begins when one realised that Hugh was not using vblanks at all on his system (fvwm and some xterms). Instead, all he had to go on were warning of a pipe underrun, curiously enough at around 60Hz. He poked and found that in addition to the underrun warning, the hardware was flagging the start of a new frame, a vblank, which in turn was kicking off the pending vblank processing code. There is little we can do for the underruns on Hugh's machine, a Crestline [965GM], which must have its FIFO watermarks set to 8. However, we do not need to process the vblank if we know that they are disabled... Reported-by: Hugh Dickins <hughd@google.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-28drm/i915: Record all error ringbuffersChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-27drm/i915: Defer reporting EIO until we try to use the GPUChris Wilson
Instead of reporting EIO upfront in the entrance of an ioctl that may or may not attempt to use the GPU, defer the actual detection of an invalid ioctl to when we issue a GPU instruction. This allows us to continue to use bo in video memory (via pread/pwrite and mmap) after the GPU has hung. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-27drm/i915: Check wedged status before throttlingChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-26drm/i915/sdvo: Add BUILD_BUG_ON to warn if the structs are ever miscompiledChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-26drm/i915/sdvo: Use a compact test for determining a multi-function deviceChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-25drm/i915: Reset crtc after resumeChris Wilson
Based on a patch by Takashi Iwai. Reported-by: Matthias Hopf <mat@mshopf.de> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=27272 Tested-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-25drm/i915/crt: Force the initial probe after resetChris Wilson
Upon resume, like after a cold boot, we need to forcibly probe the analog connector and cannot rely on the hotplug status. Based on a patch by Takashi Iwai. Reported-by: Stefan Dirsch <sndirsch@suse.de> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=26952 Tested-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-25drm/i915: Reset state after a GPU reset or resumeChris Wilson
Call drm_mode_config_reset() after an invalidation event to restore any cached state to unknown. Tested-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-25drm/i915/sdvo: If at first we don't succeed in reading the response, waitChris Wilson
We were not pausing after detecting the response was pending and so did not allow the hardware sufficient time to complete before aborting. This lead to transient failures whilst probing SDVO devices. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=30235 Reported-by: Knut Petersen <Knut_Petersen@t-online.de> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-25drm/i915: use VDD AUX override to make panel power sequencing look betterJesse Barnes
Rather than power cycling the panel when there are no bits to display, use the VDD AUX bit to power the panel up just enough for DP AUX transactions to work. This prevents a bit of unnecessary ugliness as mode sets occur on the panel. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-25drm/i915: remove now unnecessary delays in eDP panel power sequencingJesse Barnes
Now that we're doing the right thing elsewhere, these are no longer necessary. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=31114 Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-25drm/i915: Refactor self-refresh watermark calculationsChris Wilson
Move the plane->mode config to the point of use rather than repeatedly querying the same information. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-25drm/i915: Silence a few -Wunused-but-set-variableChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-24Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson
Merge important suspend and resume regression fixes and resolve the small conflict. Conflicts: drivers/gpu/drm/i915/i915_dma.c
2011-01-24drm/i915: Prevent uninitialised reads during error state captureChris Wilson
error_bo and pinned_bo could be used uninitialised if there were no active buffers. Caught by kmemcheck. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-24drm/i915: Use consistent mappings for OpRegion between ACPI and i915Michael Karcher
The opregion is a shared memory region between ACPI and the graphics driver. As the ACPI mapping has been changed to cachable in commit 6d5bbf00d251cc73223a71422d69e069dc2e0b8d, mapping the intel opregion non-cachable now fails. As no bus-master hardware is involved in the opregion, cachable map should do no harm. Tested on a Fujitsu Lifebook P8010. Signed-off-by: Michael Karcher <kernel@mkarcher.dialup.fu-berlin.de> [ickle: convert to acpi_os_ioremap for consistency] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-24drm/i915: Handle the no-interrupts case for UMS by pollingChris Wilson
If the driver calls into the kernel to wait for a breadcrumb to pass, but hasn't enabled interrupts, fallback to polling the breadcrumb value. Reported-by: Chris Clayton <chris2553@googlemail.com> Tested-by: Chris Clayton <chris2553@googlemail.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-24drm/i915: Disable high-precision vblank timestamping for UMSChris Wilson
We only have sufficient information for accurate (sub-frame) timestamping when the modesetting is under our control. Reported-by: Chris Clayton <chris2553@googlemail.com> Tested-by: Chris Clayton <chris2553@googlemail.com> Reviewed-by: Mario Kleiner <mario.kleiner@tuebingen.mpg.de> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-24drm/i915: Increase the amount of defense before computing vblank timestampsChris Wilson
Reported-by: Chris Clayton <chris2553@googlemail.com> Tested-by: Chris Clayton <chris2553@googlemail.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-24drm/i915,agp/intel: Do not clear stolen entriesChris Wilson
We can only utilize the stolen portion of the GTT if we are in sole charge of the hardware. This is only true if using GEM and KMS, otherwise VESA continues to access stolen memory. Reported-by: Arnd Bergmann <arnd@arndb.de> Reported-by: Frederic Weisbecker <fweisbec@gmail.com> Tested-by: Jiri Olsa <jolsa@redhat.com> Tested-by: Frederic Weisbecker <fweisbec@gmail.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-23drm/i915: Recognise non-VGA display devicesChris Wilson
Starting with SandyBridge (though possible with earlier hacked BIOSes), the BIOS may initialise the IGFX as secondary to a discrete GPU. Prior, it would simply disable the integrated GPU. So we adjust our PCI class mask to match any DISPLAY_CLASS device. In such a configuration, the IGFX is not a primary VGA controller and so should not take part in VGA arbitration, and the error return from vga_client_register() is expected. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
2011-01-23drm/i915: Fix use of invalid array size for ring->sync_seqnoChris Wilson
There are I915_NUM_RINGS-1 inter-ring synchronisation counters, but we were clearing I915_NUM_RINGS of them. Oops. Reported-by: Jiri Slaby <jirislaby@gmail.com> Tested-by: Jiri Slaby <jirislaby@gmail.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-23drm/i915: Remove unused code: i915_enable_interrupt()Chris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-20drm/i915/ringbuffer: Fix use of stale HEAD position whilst polling for spaceChris Wilson
During suspend, Linus found that his machine would hang for 3 seconds, and identified that intel_ring_buffer_wait() was the culprit: "Because from looking at the code, I get the notion that "intel_read_status_page()" may not be exact. But what happens if that inexact value matches our cached ring->actual_head, so we never even try to read the exact case? Does it _stay_ inexact for arbitrarily long times? If so, we might wait for the ring to empty forever (well, until the timeout - the behavior I see), even though the ring really _is_ empty." As the reported HEAD position is only updated every time it crosses a 64k boundary, whilst draining the ring it is indeed likely to remain one value. If that value matches the last known HEAD position, we never read the true value from the register and so trigger a timeout. Reported-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-20drm/i915/ringbuffer: Kill an annoyingly frequent debug messageChris Wilson
This is better handled through the tracepoints and just clutters the debug logs. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-20drm/i915: Don't kick-off hangcheck after a DRI interruptChris Wilson
Hangcheck and error recovery is only used by GEM. Reported-by: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-20drm/i915: Initialise ring vfuncs for old DRI pathsChris Wilson
We weren't setting up the vfunc table when initialising the old DRI ringbuffer, leading to such OOPSes as: BUG: unable to handle kernel NULL pointer dereference at (null) IP: [<(null)>] (null) PGD 10c441067 PUD 1185e5067 PMD 0 Oops: 0010 [#1] PREEMPT SMP last sysfs file: /sys/class/dmi/id/chassis_asset_tag CPU 3 Modules linked in: i915 drm_kms_helper drm fb fbdev i2c_algo_bit cfbcopyarea video backlight output cfbimgblt cfbfillrect autofs4 ipv6 nfs lockd fscache nfs_acl auth_rpcgss sunrpc coretemp hwmon_vid mousedev usbhid hid option usb_wwan snd_hda_codec_via asus_atk0110 atl1e usbserial snd_hda_intel snd_hda_codec firmware_class snd_hwdep snd_pcm snd_seq snd_timer snd_seq_device processor parport_pc thermal snd thermal_sys parport 8250_pnp button rng_core rtc_cmos shpchp hwmon rtc_core ehci_hcd pci_hotplug uhci_hcd soundcore tpm_tis i2c_i801 rtc_lib tpm serio_raw snd_page_alloc tpm_bios i2c_core usbcore psmouse intel_agp sg pcspkr sr_mod evdev cdrom ext3 jbd mbcache dm_mod sd_mod ata_piix libata scsi_mod unix Jan 18 15:49:29 lithui kernel: Pid: 3605, comm: Xorg Not tainted 2.6.36.2 #5 P5KPL-CM/System Product Name RIP: 0010:[<0000000000000000>] [<(null)>] (null) RSP: 0018:ffff8801150d1d40 EFLAGS: 00010202 RAX: 000000000001ffff RBX: ffff88011a011b00 RCX: 000000000001a704 RDX: ffff880118566028 RSI: ffff880118566028 RDI: ffff880117876800 RBP: ffff8801150d1d48 R08: ffff8801195fe300 R09: 00000000c0086444 R10: 0000000000000001 R11: 0000000000003206 R12: ffff880117876800 R13: ffff880118566000 R14: ffff880117876820 R15: ffff8801150d1df8 FS: 00007f1038d456e0(0000) GS:ffff880001780000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 0000000000000000 CR3: 00000001187e7000 CR4: 00000000000006e0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000ffff0ff0 DR7: 0000000000000400 Process Xorg (pid: 3605, threadinfo ffff8801150d0000, task ffff88011b016e40) Stack: ffffffffa043b8e6 ffff8801150d1d98 ffffffffa041768b dead000000000000 <0> 0000000000000048 00007f1023f2a000 0000000000000044 0000000000000008 <0> ffff88010d26bd80 ffff880117876800 ffff8801150d1df8 ffff8801150d1ea8 Call Trace: [<ffffffffa043b8e6>] ? intel_ring_advance+0x16/0x20 [i915] [<ffffffffa041768b>] i915_irq_emit+0x15b/0x240 [i915] [<ffffffffa03ea7b1>] drm_ioctl+0x1f1/0x460 [drm] [<ffffffffa0417530>] ? i915_irq_emit+0x0/0x240 [i915] [<ffffffff810dd8f1>] ? do_sync_read+0xd1/0x120 [<ffffffff81025b1f>] ? do_page_fault+0x1df/0x3d0 [<ffffffff810ed5c7>] do_vfs_ioctl+0x97/0x550 [<ffffffff8115c2ea>] ? security_file_permission+0x7a/0x90 [<ffffffff810edb19>] sys_ioctl+0x99/0xa0 [<ffffffff810024ab>] system_call_fastpath+0x16/0x1b Code: Bad RIP value. RIP [<(null)>] (null) RSP <ffff8801150d1d40> CR2: 0000000000000000 Reported-by: Herbert Xu <herbert@gondor.apana.org.au> Tested-by: Herbert Xu <herbert@gondor.apana.org.au> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=29153 Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=23172 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
2011-01-20Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson
Apply the SandyBridge stability fixes from -fixes.
2011-01-19drm/i915: Include TLB miss latency in g4x watermark computationsChris Wilson
Reports of FIFO underruns are still persisting on gm45. References: https://bugs.freedesktop.org/show_bug.cgi?id=27589 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19drm/i915: Disable SSC for outputs other than LVDS or DPChris Wilson
For CRT and SDVO/HDMI, we need to use a normal, non-SSC, clock and so we must clear any enabling bits left-over from earlier outputs. And also seems to correct the LVDS panel on the Lenovo U160. However, at one point, it did cause an "ERROR failed to disable trancoder". So prolonged testing on top of Jesse's refactored and error-checking CRTC logic is desired. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19drm/i915/bios: Change default clock source on PineView to use SSCBryan Freed
The i915 driver normally assumes the video bios has configured several of the LVDS panel registers, and it just inherits the values. If the vbios has not run, several of these will need to be setup. If these are not correct then although the panel looks ok, output from an HDMI encoder (eg, Chrontel CH7036) will be incorrect. Signed-off-by: Mark Hayter <mdhayter@chromium.org> [ickle: minor adjustments] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19drm/i915: Honour LVDS sync polarity from EDIDBryan Freed
The i915 driver normally assumes the video bios has configured several of the LVDS panel registers, and it just inherits the values. If the vbios has not run, several of these will need to be setup. So we need to check that the LVDS sync polarity is correctly configured per any available modelines (e.g. EDID) and adjust if not, issuing a warning as we do. Signed-off-by: Mark Hayter <mdhayter@chromium.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19drm/i915: tune Sandy Bridge DRPS constantsJesse Barnes
These make us increase our frequency much more readily, and decrease them only after significant idle time, resulting in a 20% performance increase for nexuiz. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19drm/i915: Trivial sparse fixesChris Wilson
Move code around and invoke iomem annotation in a few more places in order to silence sparse. Still a few more iomem annotations to go... Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19drm/i915: allow 945 to control self refresh (CxSR) automaticallyAlexander Lam
I changed 945's self refresh to work without the need for the driver to enable/disable self refresh manually based on the idle state of the gpu. This is much better than enabling/disabling self refresh for various reasons, including staying in a lower power state for more time and avoiding the need for cpu cycles. This was originally done manually to workaround issues with the hardware hanging. However, since 944001201: drm/i915: enable low power render writes on GEN3 hardware, automatic CxSR seems stable. Signed-off-by: Alexander Lam <lambchop468@gmail.com> Acked-by : Li Peng <peng.li@linux.intel.com> [ickle: play safe with the ordering and disable CxSR before tweaking any watermark and enable afterwards.] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19drm/i915: Use PM QoS to prevent C-State starvation of gen3 GPUChris Wilson
945 class hardware has an interesting quirk in which the vblank interrupt is not raised if the CPU is in a low power state. (We also suspect that the memory bus is clocked to the CPU/c-state and not the GPU so there are secondary starvation issues.) In order to prevent the most obvious issue of the low of the vblank interrupt (stuttering compositing that only updates when the mouse is moving) is to install a PM QoS request to prevent low c-states whilst the GPU is active. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19drm/i915: skip FDI & PCH enabling for DP_AJesse Barnes
eDP on the CPU doesn't need the PCH set up at all, it can in fact cause problems. So avoid FDI training and PCH PLL enabling in that case. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Tested-by: Yuanhan Liu <yuanhan.liu@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19drm/i915: set phase sync pointer override enable before setting phase sync ↵Jesse Barnes
pointer We need to unlock the phase sync pointer enable bit before we can actually enable the phase sync pointer workaround on Ironlake. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19drm/i915: factor out FDI disable and add FDI assertionsJesse Barnes
Factor out the FDI disable function (make it a mirror of ironlake_fdi_enable) and add some FDI related assertions to the FDI training code (we need an active pipe & plane before we start transmitting bits). Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19drm/i915: add transcoder enable/disable functionsJesse Barnes
Along with assertion checks for the FDI transmitters and receivers (including PLLs). Modify the pipe enable function to check for FDI PLL status as well, when driving PCH ports. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19drm/i915: assert panel is unlocked before writing transcoder timing regsJesse Barnes
Otherwise our writes will be silently ignored. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19drm/i915: add PCH DPLL enable/disable functionsJesse Barnes
With assertions to check transcoder and reference clock state. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19drm/i915: add PLL enable/disable functionsJesse Barnes
For pre-ILK only. Saves some code in the CRTC enable/disable functions and allows us to check for pipe and panel status at enable/disable time. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19drm/i915: add panel lock assertion functionJesse Barnes
When PLLs or timing regs are changed, we need to make sure the panel lock will allow it. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19drm/i915: add pipe/plane enable/disable functionsJesse Barnes
Add plane enable/disable functions to prevent duplicated code and allow us to easily check for plane enable/disable requirements (such as pipe enable, plane status, pll status etc). Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19drm/i915: don't enable plane, pipe and PLL prematurelyJesse Barnes
On Ironlake+ we need to enable these in a specific order. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19drm/i915: Use ACPI OpRegion to determine lid statusChris Wilson
Admittedly, trusting ACPI or the BIOS at all to be correct is littered with numerous examples where it is wrong. Maybe, just maybe, we will have better luck using the ACPI OpRegion lid status... Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-18drm/i915: make the blitter report buffer modifications to the FBC unitJesse Barnes
Without this change, blits to the front buffer won't invalidate FBC state, causing us to scan out stale data. Make sure we update these bits on every FBC enable, since they may get clobbered if we shut off the display. References: https://bugzilla.kernel.org/show_bug.cgi?id=26932 Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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