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path: root/drivers/gpu/drm/nouveau/nouveau_mem.c
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2013-11-08drm/nouveau/drm/pm: remove everything except the hwmon interfaces to THERMBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau/fb: initialise vram controller as pfb sub-objectBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-10-03drm/nouveau: quiet some static-related sparse noiseMarcin Slusarz
Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-10-03drm/nouveau: port remainder of drm code, and rip out compat layerBen Skeggs
v2: Ben Skeggs <bskeggs@redhat.com> - fill in nouveau_pm.dev to prevent oops - fix ppc issues (build + OF shadow) Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-10-03drm/nouveau: start culling unused codeBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-10-03drm/nouveau: port all engines to new engine module formatBen Skeggs
This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-10-03drm/nouveau: move some more code around to more appropriate placesBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-10-03drm/nouveau/instmem: completely new implementation, as a subdev moduleBen Skeggs
v2 (Ben Skeggs): - some fixes for 64KiB PAGE_SIZE - fix porting issues in (currently unused) nv41/nv44 pciegart code Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-10-03drm/nouveau/fb: merge fb/vram and port to subdev interfacesBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-10-03drm/nouveau: implement devinit subdev, and new init table parserBen Skeggs
v2: - make sure not to execute display scripts unless resuming Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-10-03drm/nouveau/agp: move all agp stuff into its own source fileBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-10-03drm/nouveau: restructure source tree, split core from drm implementationBen Skeggs
Future work will be headed in the way of separating the policy supplied by the nouveau drm module from the mechanisms provided by the driver core. There will be a couple of major classes (subdev, engine) of driver modules that have clearly defined tasks, and the further directory structure change is to reflect this. No code changes here whatsoever, aside from fixing up a couple of include file pathnames. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-05-24drm/nouveau/fifo: turn all fifo modules into engine modulesBen Skeggs
Been tested on each major revision that's relevant here, but I'm sure there are still bugs waiting to be ironed out. This is a *very* invasive change. There's a couple of pieces left that I don't like much (eg. other engines using fifo_priv for the channel count), but that's an artefact of there being a master channel list still. This is changing, slowly. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-05-24drm/nouveau/fifo: remove all the "special" engine hooksBen Skeggs
All the places this stuff is actually needed tends to be chipset-specific anyway, so we're able to just inline the register bashing instead. The parts of the common code that still directly touch PFIFO temporarily have conditionals, these will be removed in subsequent commits that will refactor the fifo modules into engine modules like graph/mpeg etc. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-05-24drm/nouveau/fence: minor api changes for an upcoming reworkBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-05-24drm/nouveau/pm: some more delays for ddr3 reclockingBen Skeggs
These numbers from the binary driver's daemon scripts, and fix the transition to perflvl 3 on my T510. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-05-24drm/nvd9/pm: oops, fix timing calcBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-05-23nouveau: add PRIME supportDave Airlie
This adds prime->fd and fd->prime support to nouveau, it passes the SG object to TTM, and then populates the GART entries using it. v2: add stubbed kmap + use new function to fill out pages array for faulting + add reimport test. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-03-13drm/nouveau/pm: several fixes for nvc0 memory timingsRoy Spliet
This patch fixes two small issues in timing generation as spotted on several NVCx cards. In addition, the header of the file is updated to also contain (some of) the current developers of this code. Signed-off-by: Roy Spliet <r.spliet@student.tudelft.nl> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/mem: handle dll_off for ddr2/ddr3Ben Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: fix dll off -> dll on transitionsBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: detect when we need dll disabled for gddr3Ben Skeggs
Fixes minor flickering on NVS295 when at perflvl 0. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: track mr2 for gddr3Ben Skeggs
There's some "extended" GDDR3 chipsets out there with EMRS2 settings that change the layout of MRS/EMRS1 bitmaps.. Sigh.. Still need to track down how exactly we're supposed to handle this. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: introduce ram reclocking helperBen Skeggs
This will probably result in more lines of code, however, we're going to have at least 3 slightly different implementations of this very soon and I'd rather keep the ram reclocking logic separate from the hw specifics. DDR2/DDR3/GDDR3 implemented thus far, others will be added as necessary. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: embed timings into perflvl structsBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: calculate memory timings at perflvl creation timeBen Skeggs
Statically generating the PFB register and MR values for each timing set turns out to be insufficient. There's at least one (so far) known piece of information which effects MR values which is stored in the perflvl entry on some chipsets (and in another table on later ones), which is disconnected from the timing table entries. After this change we will generate a timing set based on an input clock frequency instead, and have this data stored in the performance level data. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: implement DDR2/DDR3/GDDR3/GDDR5 MR generation and validationRoy Spliet
Roy Spliet: - Implement according to specs - Simplify - Make array for mc latency registers Martin Peres: - squash and split all the commits from Roy - rework following Ben Skeggs comments - add a form of timings validation - store the initial timings for later use Ben Skeggs - merge slightly modified tidy-up patch with this one - remove perflvl-dropping logic for the moment Signed-off-by: Roy Spliet <r.spliet@student.tudelft.nl> Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/pm: improve memory timing generationRoy Spliet
- Rename several VBIOS entries to closer match the real world - Add the missing 0x100238 and 0x100240 register values - Parse bit 14 of the VBIOS timing table - "Magic value" -> tCWL, fixing some minor bugs in the process - Also name a few more by their name rather than their number. - Some values seem to be dependent on the memory type. Fix Edits by Martin Peres <martin.peres@labri.fr>: - this is a squash commit - reworked for fixing some style issues Signed-off-by: Roy Spliet <r.spliet@student.tudelft.nl> Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/pm: style fixesMartin Peres
Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nv50: hopefully handle the DDR2/DDR3 memtype detection somewhat betterBen Skeggs
M version 2 appears to have a table with some form of memory type info available. NVIDIA appear to ignore the table information except for this DDR2/DDR3 case (which has the same value in 0x100714). My guess is this is due to some of the supported memory types not being represented in the table. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau: move vram detection funcs to chipset-specific fb codeBen Skeggs
Also, display detected memory type in logs - though, we don't even try to detect this yet. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nouveau/bios: pass drm_device to ROMPTR, rather than nvbiosBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-06drm/nouveau: enable the ttm dma pool when swiotlb is active V3Konrad Rzeszutek Wilk
If the card is capable of more than 32-bit, then use the default TTM page pool code which allocates from anywhere in the memory. Note: If the 'ttm.no_dma' parameter is set, the override is ignored and the default TTM pool is used. V2 use pci_set_consistent_dma_mask V3 Rebase on top of no memory account changes (where/when is my delorean when i need it ?) CC: Ben Skeggs <bskeggs@redhat.com> CC: Francisco Jerez <currojerez@riseup.net> CC: Dave Airlie <airlied@redhat.com> Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2011-09-20drm/nouveau/pm: Document and expose CL and WR for 0x1002CxRoy Spliet
Signed-off-by: Roy Spliet <r.spliet@student.tudelft.nl>
2011-09-20drm/nouveau/pm: add initial NV3x/NVCx memtiming support, improve other cardsRoy Spliet
NV30: Create framework for memtm NV50: Improve reg creation, NV50: Use P.version instead of card codename/stepping, NVC0: Initial memtiming code for Fermi, Renamed regs for consistency, Overall redesign to improve readability, Avoid kfree on null-pointer Signed-off-by: Roy Spliet <r.spliet@student.tudelft.nl>
2011-09-20drm/nouveau: make general drm modesetting init commonBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-07-13DRM: remove drm_pci_device_is_pcieJon Mason
drm_pci_device_is_pcie duplicates the funcationality of pci_is_pcie. Convert callers of the former to the latter. This has the side benefit of removing an unnecessary search in the PCI configuration space due to using a saved PCIe capability offset. [airlied: update for new callsite] Signed-off-by: Jon Mason <jdmason@kudzu.us> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-06-27drm/nouveau: Calculate reserved VRAM for PRAMIN value before use.Younes Manton
'drm/nouveau: rework vram init/fini ordering a little' changed the order of instmem.init() and nouveau_mem_vram_init() which resulted in using ramin_rsvd_vram before it was calculated and failing to init any accel on pre-NV50 cards. Since it's only used on <NV50 just calculate it where it's needed and leave it as default 0 for NV50. Signed-off-by: Younes Manton <younes.m@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-06-27drm/nouveau: fix nouveau_mem object leakMarcin Slusarz
It's a regression from "drm/nouveau: create temp vmas for both src and dst of bo moves". Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-06-23drm/nouveau: rework vram init/fini ordering a littleBen Skeggs
Commit "drm/nouveau: add some debug output if nouveau_mm busy at destroy time" revealed an issue where vram mm takedown would actually fail due to there still being nodes present, causing nouveau to leak a small amount of memory on module unload. This splits TTM/nouveau_mm a bit more cleanly and ensures nouveau_mm fini isn't done until all gpuobjs are also destroyed. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-06-23drm/nouveau: remove 'chan' argument from nouveau_bo_newBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-06-23drm/nouveau: create temp vmas for both src and dst of bo movesBen Skeggs
Greatly simplifies a number of things, particularly once per-client GPU address spaces are involved. May add this back later once I know what things'll look like. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-06-23drm/nouveau: store bo's page size in nouveau_boBen Skeggs
Was previously assuming a page size of 4KiB unless a VMA was present to override it. Eventually, a buffer won't necessarily have a VMA at all at some stages of its life, so we need to store this info elsewhere. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-06-07drm/nv40: fall back to paged dma object for the momentBen Skeggs
PCI(E)GART isn't quite stable it seems, fall back to old method until I get the time to sort it out properly. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-06-07drm/nouveau: fix leak of gart mm nodeBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nouveau: Associate memtimings with performance levels on cards <= nv98Martin Peres
v2 (Ben Skeggs): fix ramcfg strap, and remove bogus handling of perf 0x40 Signed-off-by: Martin Peres <martin.peres@ensi-bourges.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nouveau: Fix a crash at card takedown for NV40 and older cardsJimmy Rentz
NV40 and older cards (pre NV50) reserve a vram bo for the vga memory at card init. This bo is then freed at card shutdown. The problem is that the ttm bo vram manager was already freed. So a crash occurs when the vga bo is freed. The fix is to free the vga bo prior to freeing the ttm bo vram manager. There might be other solutions but this seemed the simplest to me. Signed-off-by: Jimmy Rentz <jb17bsome@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nouveau: move set_tile_region to nouveau_exec_engineBen Skeggs
In the very least VPE (PMPEG and friends) also has this style of tile region regs, lets make them just work if/when they get added. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nouveau: improve memtiming table parsingRoy Spliet
Improves the parsing of the memory timing table on NV50-NV98revA1 chipsets. Added stepping to drm_nouveau_private to make sure newer NV98 (105M) is zero rather than incorrect. Signed-off-by: Roy Spliet <r.spliet@student.tudelft.nl> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nouveau: Fix missing whitespace checkpatch.pl errors.Emil Velikov
This patch fixes messages such as ERROR: space required after that ',' ERROR: spaces required around that '=' Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Signed-off-by: Francisco Jerez <currojerez@riseup.net>
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